JPS58220473A - Drive circuit for field effect transistor - Google Patents

Drive circuit for field effect transistor

Info

Publication number
JPS58220473A
JPS58220473A JP57102974A JP10297482A JPS58220473A JP S58220473 A JPS58220473 A JP S58220473A JP 57102974 A JP57102974 A JP 57102974A JP 10297482 A JP10297482 A JP 10297482A JP S58220473 A JPS58220473 A JP S58220473A
Authority
JP
Japan
Prior art keywords
effect transistor
field effect
transformer
switch element
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57102974A
Other languages
Japanese (ja)
Inventor
Yoshihiko Fukuhara
福原 「か」彦
Taisuke Oguchi
泰介 小口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57102974A priority Critical patent/JPS58220473A/en
Publication of JPS58220473A publication Critical patent/JPS58220473A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To break the high speed of an FET and to reduce the power consumption of a drive circuit by forming the third coil in a transformer, and abruptly discharging the charge of a gate capacity at the time of interrupting the FET. CONSTITUTION:A parallel circuit of the tertiary coil 33 of a transformer 3, a resistor 7 and a capacitor 8, and a switching element 6 are connected in series with a power source 1, the starting end of the coil 33 is connected to the collector of the element 6, and when the element 6 is conducted, a current which reversely excites a magnetic core is flowed. The element 3 is conducted simultaneously upon breaking of the switch element 2, a negative voltage is induced at the secondary coil 32, charge which is stored in the gate capacity of an FET 5 is abruptly discharged through the coil 33, and the FET5 is interrupted at a high speed. The resistor 4 can be sufficiently large or removed, the power consumption can be ingored, and power consumption of the resistor 7 may be sufficiently low, the power consumption of the drive circuit is reduced, the configuration is made simple and the operating characteristics can be preferably adapted for a practical use.

Description

【発明の詳細な説明】 本発明は変成器を介して電界効果トランジスタを駆動す
る駆動回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for driving a field effect transistor via a transformer.

電界効果トランジスタは制御電極であるゲートが容量性
であるため、特に電力用電界効果トランジスタを高速に
スイッチング動作させるためには比較的大きいゲート容
量を高速に充電および放電させる駆動回路が必要となる
Since the gate, which is a control electrode, of a field effect transistor is capacitive, a drive circuit that can charge and discharge a relatively large gate capacitance at high speed is required, especially in order to operate a power field effect transistor at high speed.

第1図は従来の電界効果トランジスタの駆動回路の一例
を示すもので、Iは直流電源、2はスイッチ素子、3は
変成器、4は抵抗、5は電界効果トランジスタである。
FIG. 1 shows an example of a conventional drive circuit for a field effect transistor, where I is a DC power supply, 2 is a switch element, 3 is a transformer, 4 is a resistor, and 5 is a field effect transistor.

なお、変成器3の巻線の黒丸は巻始め端を示す。Note that the black circle of the winding of the transformer 3 indicates the winding start end.

直流電源1と変成器3の第1の巻線31とスイッチ素子
2が直列に接続され、変成器3の第2の巻線32が電界
効果トランジスタ5のゲートとソース間に接続され、抵
抗4が電界効果トランジスタ5のゲートとソース間に接
続されている。
The DC power supply 1, the first winding 31 of the transformer 3, and the switch element 2 are connected in series, the second winding 32 of the transformer 3 is connected between the gate and source of the field effect transistor 5, and the resistor 4 is connected between the gate and source of the field effect transistor 5.

スイッチ素子2の導通により変成器3の第2の巻線に誘
起する信号を電界効果トランジスタ5のゲートに印加し
て電界効果トランジスタ5を導通させ、スイッチ素子2
の遮断により電界効果トランジメタ5のゲート信号がな
くなることにより電界効果トランジスタ5を遮断する。
A signal induced in the second winding of the transformer 3 by the conduction of the switch element 2 is applied to the gate of the field effect transistor 5 to make the field effect transistor 5 conductive, and the switch element 2 is turned on.
The field effect transistor 5 is cut off because the gate signal of the field effect transistor 5 disappears due to the cutoff of the field effect transistor 5 .

第2図は第1図の動作を説明するだめの波形を示すもの
で、ここではスイッチ素子2としてノ(イポーラトラン
ジスタ、電界効果トランジスタ5としてエンノ・ンスメ
ント形のMO8電界効果トランジスタを用いた例につき
説明する。
FIG. 2 shows waveforms to explain the operation of FIG. 1. Here, an example is shown in which a non-polar transistor is used as the switching element 2, and an eno-insment type MO8 field effect transistor is used as the field effect transistor 5. I will explain about it.

Aはスイッチ素子2の入力電圧、Bはスイッチ素子2の
コレクタ・エミッタ間電圧、Cは電界効果トランジスタ
5のゲート・ソース間−圧のそれぞれの波形を示す。
A indicates the input voltage of the switch element 2, B indicates the collector-emitter voltage of the switch element 2, and C indicates the waveform of the gate-source voltage of the field effect transistor 5.

時刻t。でスイッチ素子2が導通すると、スイッチ素子
2のコレクタ・エミッタ間は短絡して波形Bの電圧はO
となり、変成器3の第1の巻線31には直流電源1の電
圧v1が印加し、このだめ、変成器3の第2の巻線32
には電界効果トランジスタ5を導通させるために必要な
閾値vth以上の信号電圧v2を誘起し、波形Cに示す
ように電界効果トランジスタ5のゲート・ソース間に加
えられ、電界効果トランジスタ5龜導通する。
Time t. When switch element 2 becomes conductive, the collector and emitter of switch element 2 are short-circuited, and the voltage of waveform B becomes O.
Therefore, the voltage v1 of the DC power supply 1 is applied to the first winding 31 of the transformer 3, and the voltage v1 of the DC power supply 1 is applied to the first winding 31 of the transformer 3.
A signal voltage v2 higher than the threshold value vth necessary to make the field effect transistor 5 conductive is induced, and is applied between the gate and source of the field effect transistor 5 as shown in waveform C, thereby making the field effect transistor 5 conductive. .

時刻t1でスイッチ素子2が遮断すると変成器3の第2
の巻線32には逆極性の電圧が誘起するが、電界効果ト
ランジスタ5のゲート容量が大きい場合にはそのゲート
容量に充電された電荷を放電するため長い時間を要する
。このため、抵抗4の値を小さくしてやれば上記ゲート
容量と抵抗4の積で決まる時定数で上記放電時間を短縮
し、電界効果トランジスタ5を短期間に遮断させること
が可能となる。しかし、抵抗4を小さくすると、第一に
スイッチ素子が導通している時刻t。からtlの期間に
抵抗4が消費する電力が増加し、第二に゛′時刻t。か
、C,、tlの期間に変成器3の第1の巻線31に蓄積
された電流は抵抗4の値に逆比例して放出される期間が
大きくなるため、時刻t2において再度スイッチ素子2
が導通する時までに完全に放出できず点線の波形B′及
びC′に示すようKなって電界効果トランジスタ5を駆
動する信号振幅が低下する問題が生ずる。
When the switch element 2 is cut off at time t1, the second
A voltage of opposite polarity is induced in the winding 32, but if the gate capacitance of the field effect transistor 5 is large, it takes a long time to discharge the charge stored in the gate capacitance. Therefore, by reducing the value of the resistor 4, the discharge time can be shortened by the time constant determined by the product of the gate capacitance and the resistor 4, and the field effect transistor 5 can be turned off in a short period of time. However, if the resistor 4 is made smaller, the first thing that occurs is the time t when the switch element is conductive. The power consumed by the resistor 4 increases during the period from tl to tl, and secondly, from time t. The current accumulated in the first winding 31 of the transformer 3 during the period C,, tl is discharged for a longer period inversely proportional to the value of the resistor 4, so that the current accumulated in the first winding 31 of the transformer 3 is discharged from the switch element 2 again at time t2.
A problem arises in that the signal cannot be completely emitted by the time it becomes conductive, and the amplitude of the signal driving the field effect transistor 5 decreases as shown in the dotted waveforms B' and C'.

本発明はこれらの問題を解決するために、変成器3に第
3の巻線33を設け、電界効果トランジスタ5が遮断す
る時刻に電界効果トランジスタ5のゲート容量電荷を急
速に放電して、電界効果トランジスタ5を高速に遮断す
ると共に、電界効果トランジスタ5の駆動回路の消費電
力を低減したもので、以下図面により詳細に説明する。
In order to solve these problems, the present invention provides a third winding 33 in the transformer 3, and rapidly discharges the gate capacitance charge of the field effect transistor 5 at the time when the field effect transistor 5 is cut off. The effect transistor 5 is cut off at high speed and the power consumption of the drive circuit for the field effect transistor 5 is reduced.This will be explained in detail below with reference to the drawings.

第3図は本発明による電界効果トランジスタの駆動回路
の構成を示す一実施例図で、変成器3は第1、第2及び
第3の巻線31.32及び33を有し、6はスイッチ素
子、7は抵抗、8はコンデンサを示し、その他の符号は
第1図と同じである。
FIG. 3 is an embodiment diagram showing the configuration of a driving circuit for a field effect transistor according to the present invention, in which the transformer 3 has first, second and third windings 31, 32 and 33, and 6 is a switch. The elements, 7 is a resistor, 8 is a capacitor, and other symbols are the same as in FIG.

変成器3の第3の巻線33と、抵抗7及びコンデンサ8
の並列回路と、スイッチ素子6は電源1に対して直列に
接続されていて、その第3の巻線m 33には変成器3
の磁心を逆極性に励磁する電流が流れるようになってい
る。
The third winding 33 of the transformer 3, the resistor 7 and the capacitor 8
and the switch element 6 is connected in series with the power supply 1, the third winding m33 of which is connected to the transformer 3.
A current flows through the magnetic core to excite it with opposite polarity.

第4図は第3図の動作を説明する動作波形であり、Aは
第2図と同じくスイッチ素子20入力電圧、Dはスイッ
チ素子6の入力電圧、B′はスイッチ素子2のコレクタ
・エミッタ間電圧、C′ハ電界効果トランジスタ5のゲ
ート・ソース間電圧である。スイッチ素子2とスイッチ
素子6は交互に導通(まだは遮断)する動作をおこない
、波形AとDは補対の関係にある。時刻t。でスイッチ
素子2が導通すると電界効果トランジスタ5のゲートに
は波形C′に示すようにV2なる電圧が誘起して電界効
果トランジスタ5を導通させる。この時、スイッチ素子
6は遮断しているからその動作は第1図の動作と全く同
一である。時刻t1でスイッチ素子2が遮断すると、同
時にスイッチ素子6が導通するため、変成器3の第2の
巻線32には負極性の電圧が誘起し、電界効果トランジ
スタ5のゲート容量に蓄えられた電荷は急速に放出され
、電界効果トランジスタ5は高速な遮断特性が得られる
。上記ゲート容量に蓄えられた電荷の放出による放電電
流はコンデンサ8、変成器3の第3の巻線33・スイッ
チ素子6の直列回路を流れるため、コンデンサ8が時刻
t1で急速に充電され、その後時刻t2で再びスイッチ
素子2が導通し、スイッチ素子6が遮断するまで抵抗7
とコンデンサ8の並列接続回路を通して変成器3の第3
の巻線33に励磁電流が流れるため、その第3の巻線間
電圧は徐々に減少し、その結果、波形C′に示すように
電界効果トランジスタ5のゲート・ソース間電圧は時刻
t2に近ずく程零に近ずく特性となる。時刻t2でスイ
ッチ素子6が遮断すると、コンデンサ8に蓄えられた電
荷は抵抗7を通して放出できる。
4 is an operating waveform explaining the operation of FIG. 3, where A is the input voltage of the switch element 20 as in FIG. 2, D is the input voltage of the switch element 6, and B' is the voltage between the collector and emitter of the switch element 2. Voltage C' is the gate-source voltage of the field effect transistor 5. Switching element 2 and switching element 6 perform an operation of conducting (but still cutting off) alternately, and waveforms A and D are in a complementary pair relationship. Time t. When the switch element 2 becomes conductive, a voltage V2 is induced at the gate of the field effect transistor 5 as shown by waveform C', causing the field effect transistor 5 to conduct. At this time, since the switch element 6 is cut off, its operation is exactly the same as that shown in FIG. When the switch element 2 is cut off at time t1, the switch element 6 becomes conductive at the same time, so that a negative voltage is induced in the second winding 32 of the transformer 3 and stored in the gate capacitance of the field effect transistor 5. The charges are rapidly released, and the field effect transistor 5 has fast cut-off characteristics. Since the discharge current due to the release of the charge stored in the gate capacitor flows through the series circuit of the capacitor 8, the third winding 33 of the transformer 3, and the switch element 6, the capacitor 8 is rapidly charged at time t1, and then At time t2, the switch element 2 becomes conductive again, and the resistor 7 is turned on until the switch element 6 is cut off.
and capacitor 8 through a parallel connection circuit of transformer 3.
Since the excitation current flows through the third winding 33, the voltage between the third winding gradually decreases, and as a result, the gate-source voltage of the field effect transistor 5 approaches time t2, as shown in waveform C'. The characteristic is that the value approaches zero. When the switch element 6 is cut off at time t2, the charge stored in the capacitor 8 can be released through the resistor 7.

以上の説明から明らかなように本実施例では変成器3の
第3の巻線33を通して電界効果トランジスタ5のゲー
ト容量に蓄積された電荷を放出するだめ、第1図の動作
と異なり抵抗4は十分に大きい値でよく、または抵抗4
を除去してもよいため、抵抗4の消費電力は無視できる
。また、コンデンサ8に蓄積された電荷は大半が時刻t
1で電界効果トランジスタ5のゲート・ソース間電圧を
正極電位(波形C′のv2)から負極電位に変化させる
だめのものであるだめ、コンデンサ8の電荷を放出する
抵抗7の消費電力も十分に小さい値でよい。また、スイ
ッチ素子2が遮断している期間(例えば時刻t1からt
2の期間)に変成器3の磁心は第3の巻線33に流れる
励磁電流に逆極性に励磁されるため、スイッチ素子2が
導通した時電界効果トランジスタ5のゲート・ソース間
電圧は、より低下しないことは明らかである。
As is clear from the above description, in this embodiment, the electric charge accumulated in the gate capacitance of the field effect transistor 5 cannot be discharged through the third winding 33 of the transformer 3. Unlike the operation shown in FIG. A sufficiently large value is sufficient, or resistor 4
may be removed, the power consumption of the resistor 4 can be ignored. Furthermore, most of the charge accumulated in the capacitor 8 is at time t.
1 is only used to change the gate-source voltage of the field effect transistor 5 from the positive potential (v2 of waveform C') to the negative potential, so the power consumption of the resistor 7 that discharges the charge of the capacitor 8 is also sufficient. A small value is fine. Also, the period during which the switch element 2 is cut off (for example, from time t1 to t
During period 2), the magnetic core of the transformer 3 is excited with the opposite polarity to the excitation current flowing through the third winding 33, so when the switch element 2 is conductive, the gate-source voltage of the field effect transistor 5 becomes more It is clear that there is no decline.

また、上記の実施例ではコンデンサ8は抵抗7と並列に
接続されていたが、コンデンサ8の片端が直流電源1の
正極性側でなく負極性側に接続、すなわち、変成器3の
第3の巻線33とスイッチ素子6の直列回路と並列にコ
ンデンサを接続しても本発明の効果は変らないことは明
らかである。
Further, in the above embodiment, the capacitor 8 was connected in parallel with the resistor 7, but one end of the capacitor 8 is connected to the negative polarity side of the DC power supply 1 instead of the positive polarity side, that is, the third terminal of the transformer 3. It is clear that the effects of the present invention do not change even if a capacitor is connected in parallel with the series circuit of the winding 33 and the switch element 6.

以上説明したように、本発明は3巻線の変成器を用い、
スイッチ素子2及び6を交互に動作させて上記変成器の
磁心を交互に逆極性に励磁し、電界効果トランジスタ5
のゲート容量負荷を急速に放電してその高速遮断を可能
にすると共に、駆動回路の消費電力の低減を図ったもの
であり、その構成は簡単で動作特性は良好であり、実用
に供し効果大なるものがある。
As explained above, the present invention uses a three-winding transformer,
Switch elements 2 and 6 are operated alternately to alternately excite the magnetic core of the transformer to opposite polarities, and field effect transistor 5 is
In addition to rapidly discharging the gate capacitance load of the gate capacitor to enable high-speed shutoff, it also aims to reduce the power consumption of the drive circuit.The structure is simple and the operating characteristics are good, making it highly effective for practical use. There is something.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電界効果トランジスタの駆動回路の一例
を示す図、第2図は第1図の動作を説明するだめの波形
図、第3図は本発明の電界効米トランジスタの駆動回路
の構成を示す一実施例図、第4図は第3図の動作を説明
するだめの波形図である。 1 ・・・・・・・・直流電源、 2,6  ・・・・
・・・・・スイッチ素子、3・・・・・・・・・変成器
、 4,7  ・曲面抵抗、 5・・・・・・・・・電
界効果トランジスタ、 8 ・パ°° コンデンサ。 第1図 第2図 1oH12
Fig. 1 is a diagram showing an example of a conventional field effect transistor drive circuit, Fig. 2 is a waveform diagram for explaining the operation of Fig. 1, and Fig. 3 is a diagram showing an example of a field effect transistor drive circuit of the present invention. FIG. 4 is a waveform diagram for explaining the operation of FIG. 3, which is a diagram showing one embodiment of the configuration. 1 ・・・・・・DC power supply, 2, 6 ・・・・・・
...Switch element, 3...Transformer, 4,7 ・Curved resistor, 5...Field effect transistor, 8 ・Per°° capacitor. Figure 1 Figure 2 1oH12

Claims (1)

【特許請求の範囲】[Claims] 直流電源と変成器の第1の巻線とスイッチ素子が直列に
接続され、その変成器の第2の巻線が電界効果トランジ
スタのゲート・ソース間に接続された電界効果トランジ
スタの駆動回路において、上記直流電源と抵抗と上記変
成器に設けた第3の巻線と他のスイッチ素子とを直列に
接続し、上記抵抗と並列に、まだは上記第3の巻線と上
記他のスイッチ素子との直列回路と並列にコンデンサを
接続し、上記スイッチ素子と上記他のスイッチ素子を交
互に動作させるようにしたことを特徴とする電界効果ト
ランジスタの駆動回路。
In a field effect transistor drive circuit in which a DC power supply, a first winding of a transformer, and a switch element are connected in series, and a second winding of the transformer is connected between the gate and source of the field effect transistor, The DC power source, the resistor, the third winding provided in the transformer, and another switch element are connected in series, and the third winding and other switch element are connected in parallel with the resistor. A drive circuit for a field effect transistor, characterized in that a capacitor is connected in parallel with the series circuit of the above, and the above switch element and the above other switch element are operated alternately.
JP57102974A 1982-06-17 1982-06-17 Drive circuit for field effect transistor Pending JPS58220473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57102974A JPS58220473A (en) 1982-06-17 1982-06-17 Drive circuit for field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57102974A JPS58220473A (en) 1982-06-17 1982-06-17 Drive circuit for field effect transistor

Publications (1)

Publication Number Publication Date
JPS58220473A true JPS58220473A (en) 1983-12-22

Family

ID=14341715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57102974A Pending JPS58220473A (en) 1982-06-17 1982-06-17 Drive circuit for field effect transistor

Country Status (1)

Country Link
JP (1) JPS58220473A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6354820A (en) * 1986-08-25 1988-03-09 Origin Electric Co Ltd Driving circuit for eield effect transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128923A (en) * 1979-03-29 1980-10-06 Kyosan Electric Mfg Co Ltd Driving circuit for switching transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128923A (en) * 1979-03-29 1980-10-06 Kyosan Electric Mfg Co Ltd Driving circuit for switching transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6354820A (en) * 1986-08-25 1988-03-09 Origin Electric Co Ltd Driving circuit for eield effect transistor

Similar Documents

Publication Publication Date Title
US4461966A (en) Circuit for controlling at least one power-FET
JPS6314589B2 (en)
EP1369981A2 (en) Driving circuit employing synchronous rectifier circuit
US4967101A (en) Pre-drive circuit
JPS59172B2 (en) Field effect transistor drive circuit
JPS63204814A (en) Power transistor driving circuit
JPS58220473A (en) Drive circuit for field effect transistor
JPH0226818B2 (en)
JPS62108588A (en) Charge and discharge device
JPH0634588B2 (en) Power supply
JPS61182324A (en) Gate driver
JP2876172B2 (en) Switch circuit
EP0206104A2 (en) FET gate driver circuit
JP2803287B2 (en) Driving method of pulse generation circuit
JPH0413950B2 (en)
JP2003133619A (en) Voltage clamp method of peaking capacitor and pulse power supply device
JPS61107623A (en) Input circuit for delay action type piezo-electric relay
JPH0633714Y2 (en) Insulated gate type power semiconductor device high frequency drive circuit
JPH0363850B2 (en)
JPH0540592Y2 (en)
JPH06276724A (en) Gate drive circuit
JPH06152363A (en) Gate driving circuit
JP2002136115A (en) Switching power supply
JPH0823672A (en) Switching power unit and its insulating method
JPS6116619A (en) Driving circuit for field effect transistor