JP2876172B2 - Switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit, and more particularly to a switch circuit for a circuit whose load varies greatly.

[0002]

2. Description of the Related Art Conventionally, a switch circuit is generally constructed so as to be made conductive only during a certain period of time when an input signal is applied, and is used for a pulse width modulation circuit as shown in FIG. 5, for example. That is, the pulse width modulation circuit 1
Input terminals 2a and 2b to which a power source 2 is to be connected, and a load 3
Are connected to the output terminals 3a and 3b,
a and 3b, a coil 6 having one end connected to the + input terminal 2a via the switch circuit 5 and the other end connected to the + output terminal 3a, And a diode 7 connected to the negative output terminal 3b, and the negative output terminal 3b is connected to the negative input terminal 2b.

The pulse width modulation circuit 1 constructed as described above
According to the above, the voltage from the power supply 2 is applied to the load 3 at the output voltage Vo via the switch circuit 5 and the coil 6, and the switch circuit 5 is turned on for a certain period of time. The load current Ids flows through the load 3 as indicated by the arrow.

[0004]

However, in this case, the relationship between the output voltage Vo and the load current Ids, as indicated by the solid line in FIG. 6, shows that the output voltage Vo sharply increases as the load current Ids decreases. Since the difference between the output voltage Vo at the time of no load and the output voltage Vo at the time of load does not become linear (shown by a dotted line), it is difficult to perform appropriate control by monitoring the output voltage Vo. there were.

In view of the above, it is an object of the present invention to provide a switch circuit in which the on-time becomes longer when the load current is small, and becomes shorter as the load current increases. .

[0006]

In order to achieve the above object, a switch circuit according to the present invention comprises a main FET and a current detection resistor connected in series between switch terminals to be turned on and off, The drain and the gate are connected to the gate and the source of the resistor, respectively, and the source is connected to the other end of the resistor opposite to the main FET via the first switching element. , A driving power supply connected to the gate of the main FET via a second switching element, and an external signal triggered input to the first switching element and the second switching element. And an input terminal for turning off the first switching element and turning on the second switching element.

[0007]

According to the above construction, when the external signal is pulse-inputted, when the external signal is at the H level having a predetermined pulse width, the main FET is turned on to make the switch terminals conductive, and the external signal returns to the L level. When the gate of the main FET
The electric charge accumulated between the sources is discharged through the discharging resistor, and the voltage generated at both ends of the current detecting resistor is input to the gate of the sub-FET to partially conduct the sub-FET. The electric charge accumulated between the gate and the source of the main FET according to the load current flowing between the switch terminals is discharged through the sub-FET. Therefore, the on-time of the main FET is reduced as the load current increases. Therefore, by incorporating this switch circuit into a pulse width modulation circuit or the like, the difference between the output voltage at no load and the output voltage at load is linear. And appropriate control can be performed by monitoring the output voltage.

[0008]

FIG. 1 shows an embodiment of a switch circuit according to the present invention. In this figure, the switch circuit 10 includes:
A main FET 13 and a current detecting resistor 14 connected in series between switch terminals 11 and 12 to be turned on / off.
And a resistor 16a with respect to the gate of the main FET 13 and the source of the main FET 13.
, The drain and the gate are connected to each other, and the source is connected to the opposite side of the resistor 14 from the main FET 13, that is, to the end on the switch terminal 12 side via the first switching element, in the illustrated case, the transistor 15. A sub FET 16 for discharging, a second switching element to the gate of the main FET 13, a driving power supply 18 connected via a transistor 17 in the illustrated case, a base of the first transistor 15 and a second transistor An input terminal 20 is connected to the base of the sub-FET 17 via a resistor 19, and a resistor 21 is connected in parallel between the drain and the source of the sub-FET.

The switch circuit 10 according to the present invention is configured as described above.
When a pulse signal having a pulse width of a predetermined time Tw is input as shown by
7 is turned on, and the voltage from the power supply 18 is applied to the gate of the main FET 13 via the transistor 17. As a result, the main FET 13 is turned on, and the connection between the switch terminals 11 and 12 is made conductive.
At this time, with respect to the input signal P, the conduction state of the main FET 13 and the voltage Vgs between the gate and the source are as shown in FIG.
It is shown as follows.

Here, when the input signal P becomes zero or less after the lapse of the time Tw, the transistor 17 is turned off and the transistor 15 is turned on. Thereby, the main FET 13
Is gradually discharged through the resistor 13a and the resistor 21. When the voltage Vgs becomes equal to or lower than the minimum voltage Vth required for the main FET 13 to maintain conduction by this discharge,
The main FET 13 is turned off. In this case, the main FET 13
Means that the ON state is maintained for a time longer than the pulse width Tw of the input signal P. The on-time is the load current Id
is maximum when s is zero, and as the load current Ids increases, the product of the resistor 14 and the load current Ids, ie, Ve
By reducing the output voltage Vgs equivalently by this amount, the on-time is reduced. The reduction of the ON time is determined by the resistance value of the resistor 14.

A voltage Ve is generated at both ends of the resistor 14, and the voltage Ve is applied to the gate of the sub-FET 16 via the resistor 16a. This sub-FET 16 is an enhancement type F configured so that the gate-source voltage starts conducting from zero.
Since the ET is used, the equivalent impedance between the drain and the source has a characteristic that is inversely proportional to the voltage between the gate and the source. When the voltage between the gate and the source increases, the equivalent impedance between the drain and the source increases. Will decrease. Therefore, the generation of the voltage Ve causes the sub-FET 16 to partially conduct, and discharge can be performed through the sub-FET 16 together with the resistor 21.

Thus, the factors that determine the on-time of the main FET 13 with the increase in the load current Ids are: 1. A decrease due to the generation of the voltage Ve in the resistor 14. The gate of the main FET 13 by turning on the sub-FET 16
This means that the charge between the sources is discharged through the sub FET 16. Thus, as the load current Ids increases, the on-time of the main FET 13 gradually decreases as shown in FIG. 3, and eventually approaches Tw.

FIG. 4 shows another embodiment of the switch circuit according to the present invention. In order to send an input signal from a control side having a different potential, the power supply 18 of FIG. The secondary side of the pulse transformer 22 is connected to the rectifier diode 23, the smoothing capacitor 24, the drive FET 25, the gate resistor 26, the resistor 27 and the capacitor 28 for absorbing the excitation energy of the pulse transformer 22, and the surge absorber. Capacitor 2 for
Except for having a resistor 9 and a resistor 30, the configuration is substantially the same as that of the embodiment of FIG.

[0014]

As described above, according to the present invention, when a pulse of an external signal is input, the main FET is turned on when the external signal is at the H level with a predetermined pulse width to make the switch terminals conductive. When the external signal returns to the L level, the electric charge accumulated between the gate and the source of the main FET is discharged through the discharging resistor, and the voltage generated at both ends of the current detecting resistor is applied to the gate of the sub FET. input.
As a result, the sub-FET is partially turned on, and the electric charge accumulated between the gate and the source of the main FET is discharged via the sub-FET in accordance with the load current flowing between the switch terminals. Therefore, as the load current increases, the on-time of the main FET can be shortened. Therefore, by incorporating this switch circuit into a pulse width modulation circuit or the like, the difference between the output voltage at no load and the output voltage at load is linear. And appropriate control can be performed by monitoring the output voltage. Thus, according to the present invention, there is provided an extremely excellent switch circuit in which the on-time becomes longer when the load current is small, and becomes shorter as the load current increases.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a switch circuit according to the present invention.

FIG. 2 shows an input signal and an FET in the switch circuit of FIG.
3 is a time chart showing the gate voltage and the operation state of FIG.

FIG. 3 shows FE with respect to current in the switch circuit of FIG.
6 is a graph showing an operation state of T.

FIG. 4 is a circuit diagram showing another embodiment of the switch circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating an example of a pulse width modulation circuit including a conventional switch circuit.

FIG. 6 is a graph showing a relationship between an output voltage and a load current in the pulse width modulation circuit of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 switch circuit 11 switch terminal 12 switch terminal 13 main FET 14 current detecting resistor 15 transistor 16 sub-FET 17 transistor 18 power supply 19 resistor 20 input terminal 21 discharging resistor 22 pulse transformer 23 diode 24 capacitor 25 FET 26 resistor 27 resistor 28 capacitor 29 Capacitor 30 Resistance

Claims (1)

(57) [Claims] 1. A main FET and a current detecting resistor connected in series between switch terminals to be turned on and off, a drain and a gate connected to a gate and a source of the main FET, respectively, and a source connected to the resistor. A discharge sub-FET connected to the end opposite to the main FET via a first switching element, a discharge resistor connected in parallel to the sub-FET, and a discharge resistor connected in parallel to the gate of the main FET. A drive power supply connected via the second switching element, and an external signal being trigger-input to the first switching element and the second switching element to turn off the first switching element and the second switching element And an input terminal for turning on the switch.