JPS59176867A - Digital picture processor - Google Patents

Abstract

PURPOSE:To decrease the hardware quantity of a digital picture processor by sharing a hardware logic for extraction of features which is used for four-, six- and eight-coupled processes respectively which form a pattern with addition of a picture data converter. CONSTITUTION:The picture data 5 is converted into the 2-dimensional data by a picture segmenting part 150 and stored in a buffer 200. The type and the coupling way of the features extracted out of a CPU are set to a function register. A coupling designation signal 75 and a feature designation signal 80 are transmitted to a picture data converting part 500 in the form of four-, six- and eight- coupled decode-out signals 65-67 and a feature designation decode-out signal 70 respectively. A picture data converting part converts the 2-dimensional array data into ''1'' and ''0'' or transmits the data in accordance with a double input and through an AND gate. Then a feature data group 90 is transmitted to a multiplexer via a feature extracting logic group 550. Thus a feature data 30 is delivered out of the group 90.

Description

[Detailed description of the invention] The present invention relates to a digital image processing device.

[Background of the invention]

In digital image processing, as a first stage of image processing, sampling is required to extract samples at discrete points from an image (continuous function of density values related to position). There are two ways.

One method is to take out samples on the regularly arranged square array shown in FIG. 1(a), that is, on grid points in the grid of the substrate. The other method is to take samples at the intersections of the regular hexagonal array shown in FIG. 1(b). Parts of images sampled using the former method are shown in FIGS. 2A and 2C. B for the latter
Shown below. Here, Xl (i=1 to 8) is image data corresponding to one quantized pixel after sampling.

In digital images, line segments, figures, etc. are constructed by a series (connection) of these pixels, and the concept of how to connect these pixels is 4-connection, 6-connection, and 8-connection ([Digital Image Processing J. Rosenfeld, author.

Supervised translation by Makoto Nagao, p.347-p.349).

The 4-connection is a concept of configuring line segments, figures, etc. by connecting pixels in four directions, Xl + Xl + XS + X7, for the image data of interest Xo, as shown by A in FIG. 8 connection, as shown by C in Figure 2, X1 to X8
The idea is to connect pixels in eight directions to form line segments, figures, etc.

6 concatenation, for the image obtained in Figure 1), XI + Xl + Xl + XS as shown in B in Figure 2.
+x? Line segments, figures, etc. are constructed by connecting pixels on all six sides of +xl. For 4,8 concatenation, Xo is n-1 rows.

The arrangement of the neighboring image data does not change no matter where it is in the nth row, etc., whereas in 6-connection, the arrangement of the neighboring image data differs depending on the row (even row, odd row) in which xo exists. There is a difference.

In B of Fig. 2, when Xo exists in the nth row (here, it is an odd numbered row), xl + Xl for Xo.
+Xl Hx5 T x71 XS becomes neighboring image data in which pixels are connected. If Xo exists in an even row, then Xl + xl 1 X41x5 +
x6 + x7 becomes neighboring image data. The matters relating to 6-concatenation in the main text will hereinafter refer to the case where the former Xo exists in an odd numbered row, but the latter case is also based on the same concept as the former.

These ideas are generally used depending on the nature of a given image, the ease of image processing, etc.

For example, given the image shown in Figure 3(a), 4
When considered in connection, the black area, which is a graphic element, is four individual elements, but in 8-connection, it can be considered that four pixels are connected in a donut shape. If these are shown in extremes, they will be as shown in FIGS. 3(b) and 3(C). In this way, because the target image has completely different properties depending on the concept of connectivity, it is necessary for the digital image processing system to have a function that allows the use of these images differently. , becomes.

The above concept is mainly applied to a processor that performs processing for extracting various features unique to a given image, such as contour extraction and geometric features such as end points and defects.

FIG. 4 shows a conventional system in which these functions are realized by hardware.

Image memory 100 in which images for one frame are stored
The sequential image data 5 read out from the image data section 150 is converted into two-dimensional data by an image cutting section 150 comprising two shift registers having a storage capacity for one row. This converted data is then stored in the two-dimensional array buffer 2.
00 as two-dimensional array data of 3×3 (pixels).

Nine pieces of image data are simultaneously sent from the two-dimensional array buffer 200 to the 4.6.8 connected feature extraction logic group 250.300.350 via the two-dimensional image data bus 10. The 4-connection feature extraction logic group 250 stores hardware that executes multiple feature extraction algorithms based on the 4-connection concept with reference to the nine xo-XS image data included in the two-dimensional image Gator bus 10. It has the function of extracting predetermined features based on logic. 6-connection, 8-connection feature extraction logic group 300'.

350 also has similar functions based on the concept of 6-connection and 8-connection, respectively. 4, 6 extracted from each of 4, 6.8 connected feature extraction logic group 250.30'0.350
．． The 8-connected feature data 15, 20° 25 is input to the multiplexer 400. 4,6 in multiplexer 400
．． One of the 8 connected feature data 15.20.25 is selected and the feature data 30 is output and further stored in a storage memory 450 having a storage capacity of 17 V-mu.

The operating principle of the conventional method has been explained above, but in the conventional method, it is necessary to prepare different logic for each connection of 4, 6, and 8, and the amount of hardware is large. This has the disadvantage that the system development period increases. Well, in the conventional configuration, each logic is
It is configured as a plurality of logic groups of 1 to n, and requires 3n hardware.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital image processing device with a simple configuration that requires less hardware.

[Summary of the invention]

4.6.8 The feature extraction algorithms differ depending on the concept of connection. Here, taking as an example an algorithm for contour extraction (extracting a boundary line between an area where an object exists and a background area), Table 1 shows the differences between the algorithms. However, this algorithm is applied to images in which the target image is quantized into binary values of uO# or 1''.The area where the object exists is 1
”, the background area is 0”.

Table 1: Friend, △: AND logic Data X, -x8 are referenced. However, in the case of 6 concatenation -XITX2IX
3IXSIX7Ix8 6 neighbors, 8 connections, XI
Only four neighbors of r X3 + X5 + X7 are referenced. For 6 connections, X4, X, but for 8 connections, X2 + X4 + X6. X8 is image data that is not subject to processing. Therefore, in the present invention, when extracting contours, by forcibly converting the image data value to 1 for these non-target image data, that is, image data that is unnecessary for processing, the four-connected contour extraction algorithm is , 6-connection, and 8-connection. Table 2 shows the above. However, in the case of 6-concatenation, as shown in Table 2, the row where Xo exists and x2
+”8 and X7 +
, 8 connections are arranged on a square lattice similar to the 8-connection.

In contour extraction in Table 2, the 4-connection algorithm can be shared by converting non-target image data to zrII+, but in the case of other feature extraction, such as expansion processing (a function that expands the object toward the background) By converting the non-target image data (different from the case of contour extraction) to 0'', the 8-concatenation algorithm can be shared.In this way,
The feature extraction algorithm extracts non-target image data (X
2゜X4 + xfl +
Although the selection of algorithms that can be shared among the 8 connections differs, the above three selections significantly reduce the hardware logic for geometric feature extraction that can realize all 4°6.8 connections.

[Embodiments of the invention]

The present invention will be explained below with reference to FIG. 5, which is a specific embodiment. Sequential image data 5 read out from the image memory 100 is converted into two-dimensional data by the image cutting section 150, and stored in the two-dimensional array buffer 200 as 3×3 (
(pixels) is stored as two-dimensional array image data. The process up to this point is the same as the case shown in FIG. The function register 700 stores the CP in advance before entering the feature extraction process.
U ((:: internal processing U
nit ) 650 via the CPU bus 85 and the method of connecting them are set by program processing. The data set to the function register 700 is not limited to this. For example, if a dip switch or the like is used as the function register 700, data can be manually set. The concatenation designation signal 75 set in the function register 700 is input to the first decoder 750 and decoded. A 4,6.8 concatenated decoded out signal 65°66.67, which is the decoder output, is sent to the image data converter 500. Similarly, the feature designation signal 80 set in the function register 700 is transmitted to the second decoder 80.
0 and is decoded, a feature designation decode out signal 70 is sent to the image data conversion section 500. The number of feature decode out signals 70 depends on the number of internally stored feature extraction logics. The image data converter 500 converts the 4,6.8 concatenated decoded out signal 65°66.67 and the feature specified decoded out signal 70.
Based on the wJJ image data X2 (35) +x4(40)+X stored in the two-dimensional array buffer 200
g (45) +xa' (50) are respectively converted to 1.0 or passed through without being converted. In each feature extraction logic of the feature extraction logic group 550, only one of the feature extraction logics of 4, 6.8 connections is stored as common to each connection.

These feature extraction logic groups 550 include converted image data x 1 (61) which is the output of the image data converter 500.
+Xl(62) lX6'(63) +X5(6
4) and the image data xQ l xl I xl + Xl + x stored in the two-dimensional array buffer 200
7 is input via the image data bus 55. and,
These 600 are sent out. In the multiplexer 600, one feature is selected according to the feature designation signal 80 set in the function register 700, and the feature data 30 is selected.
is output and further stored in the position where the image data x (1) of interest exists on the feature storage memory 450. This is repeated until all the data is read out in the scanning direction of the television.In the configuration of this embodiment, the input image data is an image captured by a television camera instead of the image memory 100, and the television camera It is possible to extract features in synchronization with the scanning time of (real-time processing).

Here, a specific circuit example of the image data converter 500 is shown in FIG. 6, taking contour extraction as an example. Based on the conversion method of the image data X21 X4 + Xl +xB at the time of contour extraction shown in Table 2, and Nagiji 501~512.
520 and OR circuits 513 to 516 are configured.

For example, the image data X440 sent from the buffer 202 in the two-dimensional array buffer 200 is converted by AND logic with the 4, 6.8 concatenated decoded out signals 65, 66, 67. In the case of 4 connections, AND circuit 50
3, the output is input to the OR circuit 513 as the image data x440 is passed through as is. In addition, in the case of 6 connections, the AND circuit 502 forcibly converts them to 1, and in the case of 8 connections, the AND circuit 501 forcibly converts them to 1, and the OR circuit 502
13.

The OR circuit 513 outputs the converted data of the image data
It is ANDed with the contour designation signal 71, which is one of 0. The output of the AND circuit 517 becomes the final converted image data x4'62. At this time, the AND circuit 517 outputs open collector output (AND circuits 518, 519, 52
0 is the same), converted image data X when extracting other features
4/ and wired or. This allows the basic logic to be expanded in many stages. Image data X* 3
5, Xi 45, and Xll 50, the converted image data X2' 61 and x6' are respectively
63.

xg'64 can be obtained.

According to one embodiment of the present invention, by providing an image data converter that can be implemented with simple logic,
．． It is possible to combine the nine-domain logic, which is prepared separately for eight connections, into one, which reduces the amount of hardware required and eliminates the effort of developing extra hardware logic, reducing the development period. This has the effect of shortening the time.

FIG. 7 shows another embodiment of the invention. Fifth
The difference from the diagram is that the image data conversion unit 500, which was composed of random logic, is replaced with a ROM (Read Qnly).
The difference is that the image data conversion table 525 has been realized using the image data conversion table 525 (Memory). 2-dimensional array buffer 20
Image data Xx (35) I X4 sent from 0
(40) l XS (45) l Xi (50)
, the connection designation signal 75 that designates the connectivity of 4, 6.8 connections set in the function register 700, and the feature designation signal 80 are converted into the image data conversion table 525.
By inputting the ROM address into the ROM address input section, the same function as in the case of FIG. 5 can be realized. In this embodiment, depending on the number of features to be extracted, for example, if the system configuration has about four feature extraction functions, 1kX
A single small capacity ROM of about 4 bits can replace the image data converter 500 and its surrounding decoders 750 and 800, shown in FIG. This makes it possible to downsize the hardware. FIG. 8 shows data stored in the image data conversion table 525 at the time of contour extraction. In this case, the image data conversion table 525 has image data
2 (35), X4 (40).

xa (45) and xs (50) are further 2 bl
Connect designation signal 7 to the address input of t (2' + 2")
5, the feature designation signal 80 is input to the upper address input of the remaining numbers.

〔Effect of the invention〕

According to the present invention, it is possible to share the feature extraction hardware logic prepared for each of the 4, 6, and 8 concatenation processes by adding an image data converter that can be realized with a simple circuit. becomes. Therefore, it is possible to provide a DigiMole image processing device with a simple configuration that requires less hardware.

[Brief explanation of the drawing]

Figures 1 (a) to (b) are sampling point diagrams of images, Figure 2 is an array diagram of image data after sampling, Figures 3 (a) to (C) are sample images, and Figure 4 is FIG. 5 is a block diagram of an embodiment of the present invention when a conventional feature extraction method is used. FIG. 6 is a circuit diagram showing a part of the embodiment of the present invention in detail. is a block diagram showing another embodiment of the present invention,
FIG. 8 is a ROM table diagram used in another embodiment. 5... Sequential image data, 10... Two-dimensional image data bus, 15... 4-connected feature data, 20...
...6 connected feature data, 25...8 connected feature data,
30...Feature data, 35...Image data X2.4
0...Image data X4.45...Image data X6.
5゜...Image data X8.55...Image data XO
+Xl+X3' + XS * x7.61 "・Converted image data X2', 62... Converted image data x4',
63... Converted image data x 6/, 64... Converted image data x 8/, 65... 4°6.8 concatenated decoded out signal, 70... Feature specified decoded out signal,
75...Connection designation signal, 80...Characteristic designation signal, 8
5...CPU bus, 90...Characteristic data group, 100
...Image memo! J, 150... image cutting section, 20
0...2-dimensional array buffer, 250...4 connected feature extraction logic group, 300...6 connected feature extraction logic group, 350...8 connected feature extraction logic group, 400...
... Multiplexer, 450 ... Feature storage memory, 5
00... Image data conversion unit, 525... Image data conversion table, 550... Feature extraction logic group, 60
0...Multiplexer, 650...CPU. 700...Function register, 750...Deco diagram (revised) Depth 1 riU(b,) 2nd
Japanese L 6th lesson 7th

Claims (1)

[Claims] 1. An image cutting unit that converts serially transferred image data into a two-dimensional array, and image data (X,) of the position of interest and its neighboring image data (Xt) output from the image cutting unit.
~Xs), and a buffer memory that sequentially stores four data (
l + X4 +
, or image data converted to its original state (X*
'r X4'+x6',X8'), image data (xO+ The image data (X
l'rx4'+X6Z A digital image processing device comprising: