JPS59174710U - amplifier - Google Patents
amplifierInfo
- Publication number
- JPS59174710U JPS59174710U JP6509483U JP6509483U JPS59174710U JP S59174710 U JPS59174710 U JP S59174710U JP 6509483 U JP6509483 U JP 6509483U JP 6509483 U JP6509483 U JP 6509483U JP S59174710 U JPS59174710 U JP S59174710U
- Authority
- JP
- Japan
- Prior art keywords
- ground
- ground side
- signal source
- source device
- device output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は信号源機器と増幅器とを接続したときの電源回
路による影響の説明に供する等価回路図。
第２図は従来の増幅器のブロック図。第３図は本考案の
一実施例を示すブロック図。第４図は第３図におけるイ
ンピーダンス変換回路の等価回路図。
第５図はインピーダンス変換回路の周波薮特性図。
第６図は本考案の他の実施例を示すブロック図。
１・・・信号源機器、２・・・増幅器、３および６・・
・接続線、７・・・インピーダンス変換回路。FIG. 1 is an equivalent circuit diagram for explaining the influence of a power supply circuit when a signal source device and an amplifier are connected. FIG. 2 is a block diagram of a conventional amplifier. FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of the impedance conversion circuit in FIG. 3. FIG. 5 is a frequency characteristic diagram of the impedance conversion circuit. FIG. 6 is a block diagram showing another embodiment of the present invention. 1...Signal source equipment, 2...Amplifier, 3 and 6...
・Connection line, 7... Impedance conversion circuit.
Claims (1)
号源機器出力端子のグラウンド側Ｃ１と増幅の基準とな
るグラウンドＧ２との間に゛接続されかつ前記入力端子
のグラウンド側Ｃ２または前記信号源機器出力端子のグ
ラウンド側Ｃ０と前記グラウンドＧ２との間のインピー
ダンスを低域周波数において前記入力端子のグラウンド
側Ｃ２または前記信号源機器出力端子のグラウンド側Ｃ
１と前記グラウンドＧ２とを接続する接続線のインピー
ダンスより低インピーダンスに変換するインピーダンス
変換回路を備えてなることを特徴とする増幅器。Connected between the ground side C2 of the input terminal to which the signal is supplied or the ground side C1 of the signal source device output terminal and the ground G2 that serves as the reference for amplification, and the ground side C2 of the input terminal or the signal source device output The impedance between the ground side C0 of the terminal and the ground G2 is set to the ground side C2 of the input terminal or the ground side C of the signal source device output terminal at a low frequency.
1 and the ground G2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6509483U JPS59174710U (en) | 1983-05-06 | 1983-05-06 | amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6509483U JPS59174710U (en) | 1983-05-06 | 1983-05-06 | amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59174710U true JPS59174710U (en) | 1984-11-21 |
| JPH0136344Y2 JPH0136344Y2 (en) | 1989-11-06 |
Family
ID=30195289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6509483U Granted JPS59174710U (en) | 1983-05-06 | 1983-05-06 | amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59174710U (en) |
-
1983
- 1983-05-06 JP JP6509483U patent/JPS59174710U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0136344Y2 (en) | 1989-11-06 |
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