JPS59174601U - controller - Google Patents
controllerInfo
- Publication number
- JPS59174601U JPS59174601U JP6906183U JP6906183U JPS59174601U JP S59174601 U JPS59174601 U JP S59174601U JP 6906183 U JP6906183 U JP 6906183U JP 6906183 U JP6906183 U JP 6906183U JP S59174601 U JPS59174601 U JP S59174601U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- signal
- output
- digital
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Feedback Control In General (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す構成ブロック図である
。
１・・・プロセッサ部、４・・・アップダウンカウンタ
ー、６・・・ウオッチドックタイマ−１８・・・クロッ
ク発生器。FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Processor part, 4... Up/down counter, 6... Watchdog timer 18... Clock generator.
Claims (1)
信号を選択する選択器、この選択器の出力をプロセッサ
に取り込むためにディジタル信号に変換するアナログデ
ィジタル変換器、プロセッサからのディジタル信号を保
持するプリセット可能なアップダウンカウンター、アッ
プダウンカウンターの保持するディジタル信号をアナロ
グ信号に変換するディジタルアナログ変換器、プロセッ
サから周期互にイニシャライズされこのイニシャライズ
が一定時間以上実行されないとき出力信号を変化させる
ウオッチドックタイマ−１手動操作の増加あるいは減少
の信号が存在するときにクロック信号を通過させるゲー
ト回路、手動操作状態をプロセッサに取り込む入力回路
、プロセッサからの前記ディジタル信号を前記アップダ
ウンカウンターにセットする出力回路とを具備し、前記
アップダウンカウンターは、ウオッチドックタイマ−の
出力によりプロセッサからのディジタル信号をプリセッ
トし保持するか、あるいは前記ゲート回路からのクロッ
ク信号によるカウント動作を行なうかを選択するととも
に、カウント動作を選択した場合にはプロセッサの入力
部に設けられた手動操作状態の増加あるいは減少の信号
によりカウント動作が規定される動作をすることを特徴
とする調節計。A processor, a selector that selects an analog signal according to the output from this processor, an analog-to-digital converter that converts the output of this selector into a digital signal for input to the processor, and a presettable up-down that holds the digital signal from the processor. A digital-to-analog converter that converts the digital signal held by the up-down counter into an analog signal, and a watchdog timer that is periodically initialized by the processor and changes the output signal when the initialization is not executed for a certain period of time - 1 Manually operated watchdog timer a gate circuit for passing a clock signal when an increase or decrease signal is present; an input circuit for inputting a manual operation state into the processor; and an output circuit for setting the digital signal from the processor to the up-down counter; The up/down counter selects whether to preset and hold the digital signal from the processor using the output of the watchdog timer, or to perform a counting operation using the clock signal from the gate circuit, and when the counting operation is selected. The controller is characterized in that the counting operation is determined by a signal indicating an increase or decrease in a manual operation state provided at the input section of the processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6906183U JPS59174601U (en) | 1983-05-11 | 1983-05-11 | controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6906183U JPS59174601U (en) | 1983-05-11 | 1983-05-11 | controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59174601U true JPS59174601U (en) | 1984-11-21 |
Family
ID=30199223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6906183U Pending JPS59174601U (en) | 1983-05-11 | 1983-05-11 | controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59174601U (en) |
-
1983
- 1983-05-11 JP JP6906183U patent/JPS59174601U/en active Pending
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