JPS59173736A - Defect detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a defect inspection device, and more particularly to an automatic defect inspection device capable of inspecting defects in a reticle by comparison against a stored database. The present invention relates to a reticle inspection device.

[Prior art]

Automatic photomask inspection equipment has been in common use for many years. As such a device, L.
ev7 and P, 5and1. By and. No. 4.247,203, filed January 27, 1981, entitled "Automatic Photomask Inspection System and Apparatus" and by the same inventor. No. 4.347.001 filed on August 31, 1982, titled "Automatic Photomask Inspection System and Apparatus". These devices discovered defects by comparing images of adjacent dice and recognizing differences between the two as defects.

However, these inspection systems cannot detect repeatable defects in photomasks by comparison, and can only inspect multi-die photomasks and cannot inspect single-die reticles. It had the disadvantage that it could not be done.

Reticle inspection equipment using comparison with database,
By NJS Corporation. Optical Microlink 2F Technology's 5PIE Vol. 3
44 mid-1980-(1982).

208-215, entitled ``Reticle Inspection Technique Comparing Pattern to Data'' on pages 208-215. Here, the optically formed display image of the reticle is
A display image formed from a database used in the manufacture of the reticle is compared. However, the sensitivity of depression inspection using this method is not very good.

[Summary of the invention]

The main purpose of the present invention is to provide an improved automatic inspection device for reticles and photomasks.

Another object of the present invention is to provide an inspection station that can optionally inspect for defects by comparison between dice or against displayed images of a stored database.

Another object of the present invention is to provide a die-to-die comparison defect detector expansion module that inputs stored titer/I/display images for comparison against a reticle or photomask.

Another object of the present invention is to provide a reticle inspection system having timing and control functions for synchronizing an idealized database image of a reticle with a measured image of the reticle.

Another object of the present invention is a reticle and photomask inspection device that includes an alignment device f that dynamically aligns images to prevent alignment errors from being detected as defects, and a reticle and photomask inspection device that detects defects by comparing two-dimensional images. The goal is to provide the following.

Another object of the present invention is to provide a comparative reticle and photomask inspection system that includes an alignment device that corrects alignment errors.

Another object of the invention is to provide an apparatus for inspecting a reticle by comparing a measured two-dimensional pixel image against a database, including an apparatus for adjusting the dimensions of the vixels to correct for alignment errors. It is to be.

Another object of the present invention is to provide a reticle and photomask inspection apparatus that has the ability to arbitrarily select high-speed operation with low accuracy.

These purposes include support equipment, irradiation equipment (illumination),
Optical equipment, detection equipment, database generator,
This can be achieved by the inspection device of the present invention, which includes a signal processing device. The illumination device illuminates the reticle or photomask to be inspected, while the optical device projects an image of the reticle or photomask onto the detection device. The support device moves the reticle or photomask at a constant speed so that the entire surface to be inspected can be sequentially examined by the detection device. The detection device is responsive to the intensity of light falling on it and is periodically scanned to obtain a measured two-dimensional image of the reticle or photomask.

The database generator generates a comparable two-dimensional image of the reticle or photomask.
ion),, '(rformulate)'f
Ru. The measurement and database images of the reticle or photomask are input into a signal processing device for alignment (alignment).
nment) and defect detection. While shifting the images from memory VC, the alignment circuit measures and corrects for misalignment between images, so that the defect detection system can effectively find defects by comparing the images. moreover,
The present invention utilizes JI to further correct misalignment.
It has a device for adjusting the dimensions of the IJ fixed image. Also,
A second measured image of the multi-cell reticle or photomask may be generated for comparison with the database image.

In particular, the apparatus of the present invention can perform effective defect inspection because the two images are fully dynamically (and precisely aligned).

〔Example〕

Embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 1 shows a reticle inspection device [20] of the present invention. This reticle inspection device 2o includes an inspection station 22 that inspects all defects on the reticle 24, and a digital image of the reticle from a stored database.
Reticle Inspection Adapter (RIA)
e In5pection Ada, pter) 2
B. Inspection station 2211:
j. The reticle to be inspected is the photomask 24f.
Air-bearing stage 2 mounted on a granite table 30 with supporting brackets in place
Contains 8. This stage 28 is a step-mo~
The combination of guide screws 32 and 34 allows rotation in the X and Y directions. The reticle holder 3B is rotatable in the θ direction relative to the motor 3BK. Place the reticle to be inspected on the reticle holder and hold it at θ
The structure of the reticle (fe'atures)
) 'y: Align in the X and Y directions.

Inspection is performed by comparing two digital images of a small area of one reticle 240. One digital image of the reticle is formed by an optical device.

The other digital image is optionally created by an optical device or from a stored database.

The optical device is placed under the granite table 30 and is inserted into the reticle 24 through the opening in the table 30 (7).
The optical system also includes a left inspection optic 42, a right inspection optic 44, and a binocular bi-head 46 and a left detector. (LD, Lef
t Detector ) 48 and right detector (RD , Right ) etect, or) 5
Project the reticle (1) image onto 0. The operator can view the magnified image of the reticle through the binocular lens 46.

Inspection optics 42.44 are described in U.S. Pat. No. 4,247,2
The type of automatic focus circuit (AFC, au
tomatic focus circuit)
52 can be automatically focused.

The reticle inspection device 20 can also inspect seven otomasks for defects as well as reticles.

When inspecting a photomask, the left and right inspection optical devices 42 and 44 are used to focus on the same part of adjacent dies.
Place. The optical image of this adjacent die (
The optical representation) is formed by the left and right detectors 48,50, after which defects are found by comparison.

The position of the switch 54 can be optical or memorized.
The database image fTh is determined to be used for comparison with the optical image from the left detector 4B. When switch 54 is in the position shown in FIG. 1, the stored database image of the reticle is sent from reticle inspection adapter 26 to inspection station 22 via RIA interface 56. Another switch 58 connects to the output i RIA interface 56 of the left skewer 4B for calibration. Details of this will be described later. Assuming switch 58 is in the position shown in FIG.
') Enter into 60. Right pixel memory (RPM,
Right Pixel Memory) 62
B. Store the image of either reticle measured by the right detector 50, or stored in the database and regenerated by the reticle inspection adapter. The selection is determined by the position of switch 54.

The left and right vixel memories 60, 62 are first-in-first-out (FIFO) type memory circuits that contain only a small portion of the entire optical and database image at any given time.

The data stored in the left and right pixel memo IJ 60, 62 is sent to the defect analyzer (DA, l') effect An
alyser) 64 to locate the defect in the reticle 24. To fully electrically align the two images of the reticle, an alignment correction device (AC) is used.

Alignment) 66 is used. System timing control device ff1i (STC, System Tim
ing Control 68 generates timing signals that coordinate the sequence of the inspection process and synchronize all of the reticle optical and database images. These alignment correction device 65 and system timing control device 687 ((J') will be described later.
8 and defect analyzer 64 and the inspection station ma/
1 clob 1 is input to the cocessor 7o, respectively.

Inspection Station Maguro Prosenna γlj, Stage Position Senna (SPS, Stage Po5itio)
nSensor) 787:” The received program
According to instructions and data, X drive device 7
2. Fully control the position and movement of the air-bearing stage 28 via the Y drive device 14 and theta drive device 76. Drive device? Preferably, 2, 74, and γ6 are step motor controllers, and the sensor 78 is an optical encoder for the X and Y axes. program·
The instructions may be pre-recorded on the microprocessor TO via a floppy disk 80, or on the keyboard 84 or manual control device (MC).
1) Operator instructions or a visual image of the reticle entered manually by the CRT
It is displayed on the display 88. The defect take obtained from the inspection is output to the printer 90.
Alternatively, it is stored in the tape cassette 82.

The autofocus circuit 52 focuses the fc image of the reticle 24 onto the left detector 48, while the inspection station microprocessor roux and Y drive 72.7
4 and moves the stage 28 along the curved path, so that all parts of the reticle can be continuously examined by the detector 48 on the left side. When a photomask is inspected by comparing adjacent dies vctq, the right detector 50 also inspects the inspection area.

FIG. 2 shows the tortuous path. When the two-stage 28 is moving at a constant speed, the inspection operation is carried out in a translational movement in the X direction. Between translational movements in the X direction, the stage is moved and rearranged in the Y direction in preparation for the next translational movement in the X direction.

For convenience, the structure of the reticle parallel to the X direction will be referred to as a horizontal line, and the structure of the reticle parallel to the Y direction will be referred to as a vertical line.

The image sensing elements of the detectors 48, 50 are photosensors that respond to the intensity of light falling on them.

The photosensors are arranged at equal intervals vc along one line parallel to the Y direction. The range of the reticle to which the photosensor responds is determined by the inspection optical device 42.44.
is a function of the magnification of The photosensor U can examine an area of the reticle that is one unit wide in the X direction and N units long in the Y direction. This N is the number of photosensors. By moving the stage 28 in the X direction at a constant speed and periodically scanning the electrical output of the photosensor, an image of the reticle can be formed.

FIG. 3 shows an image formed during a full X-direction translation of the stage. This image is Swath (5w1t
h) 92, and consists of N pixels in the Y direction and vcL pixels in the X direction.

This L is determined by the number of scans performed on the photosensor during the translational movement in the X direction. Each scan of the N 7-otosensors forms l vertical rows of swaths.

When the outputs of each of the N 7-point sensors are scanned L times, an N×L swath is formed. A vixel is a rectangular element that constitutes a swath. Each pixel corresponds to a rectangular portion of the reticle.

The X dimension of each pixel is determined by the spacing of the photosensors and the optical magnification, and the X dimension is determined by the stage speed in the X direction and the frequency of full scanning of the outputs of the seven photosensors. Each vixel has an X and Y address that corresponds to the position of the portion of the reticle that the photosensor observes. The vixel address is calculated from the position of the stage when measuring the output of the photosensor. Each vixel has a value corresponding to the intensity of light hitting the photosensor. In the present invention, vixel values can be displayed as white, gray, or black. Of course, multiple brightness values may be used.

The length of the swath Li-t is determined by the program instructions and extends over the area to be inspected. Adjacent swaths overlap to compensate for misalignment factors such as distortion, positioning, and thermal expansion. Since the dimensions of the vixels are preferably on the order of 1/271 chroma, it is necessary that the same vixels overlap each other.

Since storing a complete pixel map of reticle 24 requires a large amount of memory, inspection is performed continuously while all optical and database images are being formed.

The speed of alignment between the optical and database images, as well as the speed of defect detection, entirely determines the throughput of the reticle inspection system and therefore/its productivity.

Now, returning to FIG. 1, the function of the reticle inspection adapter 26 will be explained. The purpose of the reticle inspection adapter is to generate pixels from a stored database and provide these pixels to the inspection station 22 for comparison with the pixels generated by the left detector 48. The database used by reticle inspection adapter 26 is a converted version of the database used to manufacture reticles. An off-line computer (not shown) converts the manufacturing database to swath width format and stores it on magnetic tape or disk. This transformed database consists of a series of opaque geometric turns placed in a clear field.
ue geometrical patterns). The position of this geometric pattern is defined by the slope and coordinate position of these edges. In an inspection operation, the transformed database is reconstructed into a pixel image by reticle inspection adapter 26. The advantages over this type of database-defined pixel perfect image are:
Memory demands are significantly reduced. Yet another advantage is that, due to data rate limitations, it is faster to reconstruct a pixel image than to read it from mass storage.

The reticle inspection adapter 26, under the control of the RIA microprocessor 94, performs the task of reconstructing the database and providing a series of pixels to the inspection station 22. All components of the reticle inspection adapter 26 are interconnected by a tape drive (TP).

Tape Drive) 98 and Disk Drive (DD).

Disc Drive 100 performs all storage of database and reconfiguration program instructions. Memory 102 retains program instructions during operation. Pattern memory 104 holds a portion of the database while it is being read from tape or disk drive 98,100. The pattern memory 104 includes a pattern generator (PG, Pa
tern Generator) 106. This notation generator 106 converts the geometric patterns of the database into black and white pixels and subsequently stores them in a bit map memory (BMM).
Memory ) 108 stores the results.

To provide synchronization between the optical and database images of the reticle 24, the reticle inspection station 2
The output of the stage position sensor 78 is monitored via the second stage monitor 110U and the system timing control device 68. At an appropriate time, stage monitor 110 converts a digital scan converter (DSC) to send a series of pixel values corresponding to a database image + pit map memory 1087) to RIA interface 56.
al 5can Converter) 112 vc
Instruct. Digital scan converter 112 generates gray pixels at the white-to-black and black-to-white transitions to simulate all edge transitions detected by the detection station. This series of pixel values (database image) is stored in the right pixel memory for alignment and comparison with the pixel values from the left detector 48 (optical image).

FIG. 4 illustrates the operation of the defect analysis portion of the detection, alignment and inspection station 22. The left detector 48 consists of the left sensor 114 (the aforementioned seven sensors), an analog-to-digital (A/D) converter 118, a level converter 122, and the right detector 50 consists of the right sensor 116. (the aforementioned photo sensor), an analog-to-digital (A/D) converter 120, and a level converter 124: E-Ra. When scanning the photosensor one at a time, the A/D converter and level converter output a series of pixel values representing white, gray, and black. The sensor generates a signal that is proportional to the intensity of light that falls on it. The sensor signal strength is converted to one of 16 digital values by an A/D converter and further converted to one of three values by a level converter. A buffer/switch 126 routes the left detector output to the reticle inspection adapter for calibration.

A buffer/multiplexer 128 selectively connects the right detector or RIA interface 56 to the right pixel memory 62. This depends on whether you select all die, /die comparison, or reticle/database comparison.

Once the left and right vixel memories 60, 62' are filled with pixel data, the alignment and defect detection process begins. As mentioned above, the pixel memory does not hold part of the pixel image of the reticle.

For example, in this embodiment, these memories hold only the pixel values from the 16 most recent scans. At the end of each scan, the oldest scan is shifted out of memory and
Create the newest scanning room.

Each pixel memory thus holds a matrix of size Nx16, corresponding to the vixels from the 16 most recent scans. Alignment and defect detection are functions that occur continuously as the pixel data passes through the pixel memory.

Alignment is performed using an alignment error detection circuit (AED).
ent Error Detection) 130 and memory address control circuit (MAC, Memory A
ddressControl) 132 by an alignment correction device 66 having a pixel memory 60.6.
It will be held in 2 minutes. That is, the alignment error detection circuit 13
0 compares portions of the vixel memory and instructs the memory address control circuit 132 to define these portions to minimize alignment errors. This will be discussed later.

Defect detection is performed on the same portion of the vixel memory used by the alignment circuit. Defect detector (DEF DET)
, Defect Detector) 134 B
Compare the aligned vixel memories and define a defect as the difference between them. The operation of defect detector 134 is detailed in US Pat. No. 4,247,203. Defect cascade device (DEF CON, Defect Conc
atenator ) 136 is responsive to the output of the defect detector. Since most defects are large enough to be detected many times, this device 136 operates to collect the detected defects. The results of the defect analysis are sent 1 to the inspection station microprocessor 70 for recording.

System timing controller 68 provides several timing and control functions to inspection station 22 and reticle inspection adapter 26. One function is to control the overall length of the swath by tracking the position of stage 28 with the aid of stage position sensor γ8.

Another function is to trigger the full scan of sensors 114 (and 116). The system timing controller 68 triggers the scanning process and thus controls the size of the pixels in the X direction. Additionally, the system timing controller compensates for calibration and alignment errors by adjusting the x-direction vixel dimensions. Yet another function of the system timing controller is to provide a pixel clock signal that regulates the flow of pixel data through alignment error detector 130 and vixel memory 60,62. Synchronization between optical and database vixels is performed by the system timing controller via the RIA interface 56.

5 and 6 illustrate the method used to synchronize reticle inspection adapter 26 to inspection station 2'2. At the beginning of the swath, the stage 28 is accelerated from rest, advances at a constant speed until near the end of the swath, and then decelerates and comes to a stop. Next, take an appropriate amount
After moving in the direction, the next swath begins. To know when swaths start and stop, and to match adjacent swaths, system timing controller 68 monitors the overall stage position as indicated by stage position sensor T8. To do this, microprocessor 70 registers servo trigger register 1.
The servo φ address is loaded into 38 (FIG. 6). When the stage moves, the encoder clock signal from the stage position sensor 78 clocks the stage position servo signal.
Servo address register 140 for displaying address
'e Increment. The comparator 14 detects that the stage has reached the stored servo address.
2 is displayed, the signal is sent to the current status register (C8R, Current Stat
eRegilIter) 146. This register 146 outputs appropriate control signals. In FIG. 5, (A) indicates servo address trigger 1. (B) is enable pixel clock, (C) is enable RIAS ■) is pixel address trigger, tap)
indicate enabled defect detection, respectively. Servo address triggers 148, 150' (FIG. 5) are used to count the pixel addresses with the pixel clock fully enabled and the reticle inspection adapter (RIA) 26k enabled.

After the second servo Φ address Φ trigger 150 enables the reticle inspection adapter 26, the alignment corrector 966
While the Bixel Memo IJ f is being aligned, the stage
Monitor 110 counts the pixels and triggers a valid test interval. Pixel Kai Clock and Enable R
The IA register is coupled to an AND gate 152 to increment a vixel address register 154 and count the pixels. When the vixel count reaches the value prestored in the vixel trigger register 156, the comparator 158 outputs a full signal to the current state register 146 via the multiplexer 144. This begins the inspection process, which continues until the next vixel address trigger 160 is reached. The RIA microprocessor 94 is a Bixel-
Load the address trigger into the vixel trigger register 156 according to the program instructions.

The test station microprocessor 70 is operative to control the multiplexer to selectively connect the appropriate comparators to the registers 146 and to load the servo address register 138 into the servo address register 138. Additionally, microprocessor 70 has a Next Status Register (NSR).

NextSt,ate,Register) 16
Load the next control instruction into 2. Since this register operates as an instruction buffer, register 146 is updated quickly without being delayed by updates from microprocessor 70.

FIG. 7a shows images of the left and right vixel memo IJ 60, 62. Each pixel memory contains 16 columns of pixel values. Each column consists of N rows, where N is the number of photosensors. The alignment corrector 6'6 and the defect analyzer 64 observe only a portion of the pixel memory (which is eight columns wide).

These parts of the pixel memory are inspected in the left and right inspection windows 16.
It is called 4.166. This test window is located in pixel memory with respect to left and right window origin addresses 168, 170. This window origin address is
6 Define the upper right corner of the window. The X dimension of the inspection window is 8 pixels, and the Y dimension is D less than N. The task of the alignment corrector 66 is to place two inspection windows in each pixel memory so that the images within the windows are aligned.

Once the images are aligned, the defect analyzer can accurately detect defects by comparing the two windows without being triggered by alignment errors.

To align the two inspection windows 164, 166, the alignment error detection circuit 130 (FIG. 4) detects the data at each pixel alignment clock cycle by observing the pixel values in the left and right alignment matrices 172, 174. Collect. The alignment matrix consists of 2 rows high and 8 columns wide and is named according to Figure 7b. At the beginning of the scan cycle, an alignment machine (IJ Lux) is placed at the top of each inspection window. At each pulse of the pixel clock, the alignment circuit examines the pixel values of the alignment matrix to determine horizontal and vertical structure. Each pulse of the vixel clock lowers the alignment matrix by one vixel (in the -Y direction). This process is a luxury
Continue throughout the scan until positioned at the bottom of the IJ sock window. At this point, the alignment circuit determines whether the alignment is correct.

If alignment correction is required, the memory address control circuit 132
calculates the left and right window origin addresses 168, 170 i again to relocate the window in pixel memory. Before starting the next scan, the oldest column of pixel data is shifted out of pixel memory and the newest column is shifted in. The next scan starts with the alignment matrix placed on top of the repositioned window.

The left and right inspection windows 164 and 166 are skewed in the Y direction.
KW is shifted by skew X5KW in the X direction. Y.S.
KW is left and right window origin address 168°170(
7) Calculate by the difference in the Y coordinate, xsKw, u, and the difference in the X coordinate. By advancing the lower window sufficiently in the X direction and delaying the other window sufficiently, the maximum alignment error that can be tolerated is 8 pixels. Similarly, in the Y direction, the maximum allowable alignment error is D.

The defect detector 134 performs defect detection on the pixels in the left and right defect inspection matrices 176 and 178.

These matrices are aligned matrix 1 at its center
8 rows high with 72,174.

It consists of 8 columns in width. As the defect detection matrix 1 moves downward through the inspection windows 164, 166', the alignment matrix follows +7x. Therefore, it can be seen that if the alignment windows are properly aligned, then the defect inspection matrix is also properly aligned.

This alignment correction method has several advantages.

One is that it is a continuous process and does not require stopping or restricting the vixel flow. This is easy to calculate since the misalignment error is simply the difference between the two origin addresses. Average YS in l swath
By monitoring the KW value, significant X alignment errors can be corrected from swath to swath by varying the amount of indexing in the Y direction. Also, significant X-alignment errors can be reduced by adjusting the X dimension of the optical vixels according to methods described below to speed up or slow down the optical image so that it aligns with the database image.

Alignment error detection is performed by the circuit shown in FIG. This circuit consists of a 2x8 left-right alignment matrix 17
2.174 (Figure 7a) to show the amount of alignment error. This circuit consists of four basic sections: (1) an X error detector that measures all alignment errors in the Y direction;
80; (2) an X-error detector 182 that measures the alignment error in the X direction; (3) a goodness detector 184 that measures alignment characteristics; , an alignment processor 186 that determines whether alignment correction is required. X error, X error, goodness detector (c), alignment (m)
B. Alignment Matrix Buffer
-) 188 and operates on the vixel values of the 'fc alignment matrix. This buffer updates each cycle of the Bixel Q clock.

The purpose of the X error detector 180 is to recognize and detect horizontal structures and count the number of pixels whose horizontal structures are offset from each other. To perform these tasks, Y
Error detector recognizes horizontal edges and colors! First thing to do
Stage Logic Unit (FSL, .

First Stage Logic) 190 and second stage logic (SSL, 5econd Log) that determines the effective measurement interval and direction of error.
ic) 192, three counters 194, 196, 198 for counting the measured errors, and 20 latches. It is configured.

To perform the horizontal edge and color recognition functions, first stage logic 190 examines the contents of two pixels within each alignment matrix. For example, pixel full pixel in row 0 and columns 0 and 1 (0,0 and o,1)
Monitor in clock cycles. For example, both pixels o,.

and 0.1 is white at the pixel clock to, t
A valid horizontal edge is encountered when at l both vixels are gray and at t2 both vixels are black.

Here tO+Ll+t2 are three consecutive pixel clock cycles. Also, in to, pixel clock o=o, 1 are both white, and in tl, pixel clock 0. .

and 0.1 also meet a valid horizontal edge if both are black. These effective horizontal edges are denoted as W>G>B and W>B, respectively. Therefore, when the valid horizontal edge transitions B>G>W and B>W are encountered at 174 (FIG. 7a), first stage logic 190 outputs a positive pulse on the RE output line. . B>G>W or B
>, W transition is completed, the ItW line is toggled to a logic high and the pixels 0, 0 and 0 . The color of l indicates that the current day is out. If the W>G>B or W>B transition is completed, RW I''i goes logic low, indicating that pixels 0°0 and 0.1 are now black.

LE and LW are equal to RE and RW, but display the edges or colors of pixels 0,0 and 0°1 of the left alignment matrix 172. The left and right colors must match (l-j
:No, but when the colors of pixels 9, 9 and 0.1 of the right alignment matrix match and the colors of pixels 0, 0 and 0.1 of the left alignment matrix match, the signal BA
D/ri becomes logic low. If the pixels 0.0 and 0.1 in the left or right alignment matrix do not match, BAD is logic high and the diagonal edge
al edge) 7%.

FIG. 9 is a diagram showing the logic built into the first stage logic (PAL) circuit. This logic is used for the left and right alignment matrices to determine the values of LE and LW and R3 and RW. Five states are defined as shown below. The state l, denoted by reference numeral 202, is if the color is not the same as that of pixel 0,0 or pixel 0,1 (denoted by M), or GAG, or W>G>W, or f
C occurs when considering the B>G>B transition. BAD is a logic high if the left or right logic is in state 1''C. State 2, indicated by reference numeral 204,
and 0.1 are both white. State 3, denoted 206, occurs when the vixels 0.0 and 0,1 go into transition W)G at the same time. State 4 indicated by 208
occurs when pixels 0, O and 0.1 have a transition W>B or a transition W>'G>B. State 4 can be entered directly from state 2 or via state 3.

Once in state 4, the edge is displayed by pulsing RE or LE, and the color is changed to black by toggling OFF or LW to a logic low. State 5, denoted 210, occurs when both vixels 0°0 and 0.1 have transitions B>G at the same time. State 2 has transition B
>W directly - or the transition B>G>W can be entered from state 4 via state 5. When going from state 4 or state 5 to state 2, RE or LE pulses, indicating a valid horizontal edge, and RW or LW is toggled to a logic high, indicating that the color is the current day.

The functions of the second stage logic 192 operate on the data generated by the first stage logic to fully recognize the valid alignment error measurement interval, fully recognize the characteristics of the alignment error, and counter 194, 196, 198. and output a signal to latch 200 to count the number of measurement intervals and the number of net alignment errors in the Y direction. When one alignment matrix displays horizontal edges and changes to a different color from the second alignment matrix,
A valid measurement interval begins. This valid measurement interval ends when the second alignment matrix (") displays the IJ lux horizontal edge and changes to the same color as the first matrix (").

For example, assuming that initially both matrices are white, ie, both are in state 2, when the left matrix encounters the edge, it shifts to black 9, or state 4. After three pixel clock cycles, when the right ma) IJ lux edge is encountered and shifted to black, the measured alignment error is three pixels. In this example, assuming that after 10 pixel clock cycles, the left matrix shifts from displaying edges to white, this means that when the right matrix shifts from displaying edges to , begins another valid measurement interval that ends after 3 pixel clock cycles.

Again, the measured alignment error is 3 pixels.

In this example, the detected fish feature is 13 pixels long, and the left vixel is offset by 3 pixels from the right vixel.

The alignment error is measured twice and is found to be 3 pixels each time. Therefore, it can be seen that the direction of the error is "Hayabusa left leading".

Y second stage logic 192 performs YEM on each pixel clock cycle of the valid measurement interval.
(Y error measurement) Counter 194 is incremented. The YEM counter counts up on each clock cycle that the left matrix is leading;
Counts down in each clock cycle that the right matrix is leading. Therefore, the count in the YEM counter is the net number of pixels as a measure of Y alignment error. Also, the Y second stage logic device is
At each left leading effective measurement internocle, NYES
Increment the (net number of Y error samples) counter 196 and decrement said counter at each right leading interval. Therefore, the count in the NYES counter is the net number of measurement intervals. The NYTS counter 198 is incremented at each valid measurement interval regardless of the direction of the error and displays the total number of valid error intervals. If a simultaneous encounter is encountered, the ink 1 is counted. These numbers are processed by the alignment processor 186 to determine when correction of the Y alignment is required and to determine the magnitude of the correction.

P defined in FIG. io u, second stage logic device 192
This is a diagram showing the logic built into AL.

The symbols in Figure 1O are as follows. RE=LE
, 2R'W= LW= BAD = logic high, -/RE
= /LE-/RW=/LW-/'BAD-logical low, rice is logical product (and), +t is logical sum (or)
'e means. The five states are defined as follows. State A, indicated by reference numeral 212, is a stopped state, i.e. there is no valid measuring ink nozzle because both matrices are the same color or the BAD signal is high indicating that there is no horizontal edge. That's the situation.

For example, state A is a left alignment matrix in which the IJ lux pixels 0,0 and 0.1 are both white and black, and the right alignment matrix's vice pixels 0,0 and 0.1 are both black over white, That is, RW US LW, or /RW US/L
Occurs when W.

If the two horizontal edges are displayed as LE body RE at the same time from IJ Lux, the state will remain in state A. This is because this occurs when the two images are aligned.

The remaining four conditions occur during the valid measurement interval. The transition from state A7), indicated at 212, to state B, indicated at 214, occurs when both matrices are white and the left matrix displays the horizontal edges and the change to black. This transition is LE rice / LE rice / RE rice R
Logically expressed as W/BAD, this is represented by the edges of the left ma) II lux pixels 0,0 and 0,1 (LE), and the left ma) IJ lux pixels 0. O and 0゜1 are the current points f) (/LW), and the right ma) IJ socks pixels 0,0 and 0,1 do not indicate the edge (/RE), 7) One right (C/BAD) where pixels 0.0 and 0.1 of the matrix are both white (RW) and the BAD signal is a logic low.
It means everything. In state B, Y'FJi counter 194U counts up by 1 for each pixel clock. The direction of this error measurement is β with the left leading edge since the edge is represented by the left matrix.

As mentioned above, the valid measurement interval ends when the second matrix (right in this example) displays an edge and changes color to the color of the first matrix (black in this example). /LW rice/RW rice/ shown in Figure 1O
BAD, the left one) l) Tux pixels 0,0 and 0,1 are black and C, /LW) , :6 one right ma) l)
Pixels 0, 0 and 0.1 of Tux are black (/RW),
Furthermore, it means that the BAD signal is at a logic low (/BAD,). In such cases, measurements are omitted. S in FIG. 10 represents an omitted instruction. However, state B
When the second left edge is encountered and the left edge is turned white, no valid measurements are taken. On the other hand, in state B, if the left "z" or right matrix is displaying a BAD signal,
– No valid measurements are taken. LW*RW+B like this
In case of AD, the state is AK return 9 and the current measurement is invalidated.

FIG. 10 shows such a transition kT.

The three loosening conditions also operate in a similar manner. 2 in state A, left and right alignment matrix is black (/RW tree/LW)
, the left matrix changes the left color to white (LW)
! Upon displaying (LE) the logic changes to state C, shown at 216. In state C, the YEM counter counts up since this is the left leading measurement interval.

If the right matrix shows a shift to white (RW), the measurement interval is valid and the state changes to state A11
ZL, the above interval is omitted.

However, if the left matrix displays a 7 jump to black (/LW), or if the BAD code goes to a logic high, the state changes AVC and the interval ends.

Y second stage logic device 192: If in state B shown at 214 or state C shown at 216, state A
A valid measurement interval can be ended without going back. This occurs when displaying the left and right alignment edges simultaneously, thereby transitioning from state B to state C, or from state C to state B. For example, if the logical unit is in state BK, the left side is black (/
LW), and the right side becomes white (RW). Same vixel
In the clock pulse, when the left changes to white (LW) and the right changes to black (/RW), the state changes to state C and the measurement interval of state B is omitted.

Also, when the right matrix changes to white (RW), the logic device changes to state A and the second measurement interval (phrase omitted; in this case, the double measurement interval is valid).

The two residual states, state 218 and state E 220, behave similarly to state B 214 and state C 216, except that the alignment error characteristics are reversed. do. The left side remains white and the right side changes to black, thereby reaching state A from state A. A valid measurement interval occurs when the left shifts to black.

State E is reached from state A by shifting the right to white and keeping the left to black. A valid measurement interval occurs from state El- when the left shifts to white. As described above, the transition from state D71) to state E, or from state E to state E, occurs at the left and right coincident edges. The YEM counter also runs back down on each pixel-clock cycle in state or E because the error indicated by these two states is right leading. NYES counter is also in state B
Count down at each valid measurement incle pal that meets D and E.

FIG. 11 shows the Y second stage logic unit & 192° Y counter 194, 196, 198 . and a timing diagram showing the operation of the latch 200. Left and right vixel memo 176
A fraction of 0.62 is shown in X-Y coordinates rotated 1/4 mm counterclockwise.

The left and right alignment matrices 172 and 174 move in the right direction (-Y direction) when time progresses from time toax to t25.
to move to. The output signal of the Y2nd stage logic is defined in FIG. 11 as follows: CLK occurs at each valid measurement interval. CEYEM that displays states other than state A is state B, C, and D.
If Saitama is E, then logic is high. YEMDIR is
Indicates direction of Y alignment error and is logic high if state B or C. Note that the error is left leading. R.E.
LOAD is generated by a T transition indicating the end of an inactive measurement interval. CEYER occurs at each valid measurement interval. YERDIR is a logic high if the previous state was rarely state B or C. CEYT
OT occurs at each valid measurement interval and at the valley matching edge.

The above-mentioned outputs of Y second stage logic 192 are output to counters 194, 196, 198, and latte 200.
operate. YEI! , 7[Counter 194 is CEY
To the pixel clock, according to the direction enabled by EM and indicated by YEMDIR,! ,
It will be locked. When reaching an ineffective measurement interval,
RELOAD reloads the last valid read fL stored in YEM latch 20. YEM counter output Y
EM is input to the YEM latch, which is updated after each valid measurement interval by LCLK. NYES
Counter 196 indicates -r at each valid measurement interval.
Enabled by CEYER, YERDiR
The count is counted up in the direction that is completely displayed, that is, for a left leading error, and it is counted down for a stone leading error. NYTS counter 198 is CE
Enabled by YTOT and clocked by the pixel clock, counts the total number of matched edges in addition to the valid measurement interval. .

The timing diagram shown in FIG. 11 will be explained.

to...left and right ma) Display IJ Lux White.

tl... left side) I met the horizontal edge of IJ Lux,
Changes with black.

LE toggles to pulse L, LW to logic low.

Condition B: Left leading error.

If YEM, count up by one.

φ up.

t3...The right matrix meets the horizontal edge and turns black.

RE pulses and RW toggles to a logic low.

State A: Waiting state.

LCLK pulses to indicate the entire valid measurement interval.

YEiVl Lunch loads the YEM value.

The NYES and NYTS counters count-amplify by one.

L4...Stay in state A.

t5...Stay in state A.

to ・Remain in state A.

t7... left ma) 17 tux meets the edge and changes to white.

LE pulses and LW goes high.

Condition C: Left leading error.

YEM counts up by one.

t8...Staying in state C, YEM increases the count by one.

t9...The right matrix meets the edge and turns white.

RE pulses and RW goes high.

State A0 LCLK pulses to indicate valid measurement interval.

YEM5ychi loads the YEM value.

The NYES and NYTS counters count up by one.

tlo...Stay in state A.

t, I +... left ma) I met the edge of the IJ sock,
Changes to black.

LE pulses and LW goes low.

Condition B: Left leading error.

YEM　U　Count up by one.

tl2...YEM counts up by one until it reaches 1 in state B.

tl3... left ma) It meets the edge of the IJ sock and turns white.

Right ma) It meets the edge of IJ Lux and turns black.

LE pulses and LW goes high.

RE pulses and RW goes low.

Edges match and change to state C: right leading error.

L CL I (pulses and displays the entire valid measurement interval.

YEM latch loads all YEM values.

Count up by YEMU.

The NYES and N Y T S counters are incremented by one.

tl4: Remains in state C, and YEM counts up by one.

tl5...The right matrix meets the edge and turns white.

RE pulses and RW goes high.

To state o LCLK pulses to indicate valid measurement interval.

The YEM latch loads the YEM value.

The NYES and NYTS counters count up by one.

tts...The left matrix meets the edge and turns black.

LE pulses and LW goes low.

Condition B: Left leading error.

YEM counts and amps one.

t17...Left ma) There is a tag on the edge of IJ Lux, which changes to white.

Condition A.

LCLK does not pulse: invalid measurement interval.

RELOAD pulses and the YEM latch reloads the YEM counter.

t18...Right ma) It meets the edge of IJ Lux and turns black.

RE pulses and RW goes low.

Condition D = Right leading error.

YEM counts and tarans one.

t19...The left matrix meets the edge and turns black.

LE pulses and LW goes low.

States A0 T, CL K pulse to indicate a valid measurement interval.

Load YEN latch BYEM value.

NYES Counter Fi counts down by one.

The NYTS counter counts up by one.

t20...Stay in the state.

tel...The right matrix meets the edge and turns white.

RE pulses and RW goes high.

Condition E: Right leading error.

The YEM counter counts down by one.

t22...Left) It meets the edge of IJ Lux and turns white.

LE pulses and LW goes high.

State A0 LCLK pulses to indicate valid measurement interval.
Ru.

YEM latch is YEM @ fully loaded.

NYES The counter counts down by one.

NY1'S counter increases by one.

t23°°left ma) It meets the IJ Lux edge and turns black.

Right ma) It meets the edge of the IJ sock and turns black.

LE pulses and V goes low to L.

RE pulses and RW goes low.

A change in state A.

NYTS counter [counts up by one.

t24: Remain in state A.

t2g...The left matrix meets the edge and turns white.

The right matrix meets the edge and turns white.

LE pulses and LW goes high.

BE pulses and RW goes high.

State A talent.

The NYTS counter counts up by one.

Returning to FIG. 8, the operation of the X error detector 182 will be explained. The purpose of the X error detector is to inspect the left and right inspection windows 16.
4,166 (Figure 71a) and to determine the polarity of the alignment error in the X direction. , the work of the X error detector 180 is somewhat simpler.

To accomplish this task, the X error detector includes an X logic circuit 222 that recognizes vertical edges and two counters 224, 226 that accumulate counts of measured errors.

The X logic circuit 222 has as an input the buffer 188K
Memorized 2X'8 left and right alignment ma) I am using IJ socks. Unlike the Y logic circuit, the X logic circuit uses 14 pixels in columns 0 and 1 and rows 1-7. Vertical edge testing is very easy. That is, the vertical edges are either pixels 0.1 and 1.1 both black or gray, pixels 0.2 and 1.2 both white, or pixels 0.1 and 1.1 both white. Both are white or gray, and if pixel 0.2 and l,2 are both black, they are displayed between rows 1 and 2. In the same way, logic tests were carried out, with pixels between 2.3, 3°4, and 4.5
Indicates that there are vertical edges between 5 and 6, and between 6 and 7. The logic devices used for these tests are included in the PAL consisting of the X logic circuit 222E-.

The output of this logic is sent to counters 224 and 226, which count X alignment errors in much the same manner as Y counters 196 and 198. NXES (net number of X error samples) counter 224 is enabled by CEXER output by X logic unit 222.

CEXER has one aligned matrix) IJ lux valid edges and neither matrix has a diagonal line, or both matrices) IJ lux has unaligned valid edges. , and will be a logic high for each valid X error measurement that occurs when neither matrix has a diagonal line. The counting direction of the NXES counter is determined by XERDIR, which is positive for left leading X@column errors and negative for right leading X alignment errors. NXTS (number of X error samples) counter 226
．． ．． is enabled by CEXTOT being a logic high when at least one alignment matrix has a valid edge and neither matrix has a diagonal edge.

12 and Table 1 (shown at the end of the Detailed Description of the Invention section) illustrate the operation of the X logic device 222.
Figure 2 shows a vertical structure 223 having a width of 5 pixels in the X direction and located in the right pixel memory 62 three pixels ahead of the position of the structure 223' in the left pixel memory 1J60. In addition, FIG. 12 shows the alignment matrix in five different scans) IJ Lux 72,
The relative position of 174 is shown. Note that in one scan, the alignment error in the X direction is detected once for each pixel clock pulse. This is because the alignment matrix shifts vertically in the valley long pulses and recalculates the detectable error. X
Since the alignment error is measured from the vertical edge, the same edge and the same error will be encountered in valley clock cycles over the vertical extent of the edge.

Since no vertical edges are encountered between IJ lux rows 1 and 7 for either the left or right alignment machine in scan So2, no alignment error is detected. In scan s3, the right alignment matrix has a valid edge between rows 3 and 4, while the left alignment matrix has not yet encountered an edge.

According to the truth table shown in Table 1, the X logic device 222
Determine the characteristics of the X-alignment error. Let's do two tests here. First, we test whether the pixels in row l of the left matrix match the pixels in row l of the right matrix, and then which matrix has all the edges in the matrix that are closer to row l. test to see if it is. In scan S3, the pixels in row 1 are: the pixels in row 1 on the right are black and the pixels in row 1 on the left are white;
It doesn't match.

For the second test, only the right matrix has internal edges, so it follows that the right matrix has an edge close to row l. The answer to the first test is [
In disagreement J, the answer to the second test can be determined by the "right", so it is determined that it can be determined by the right leading according to the truth table.

In scan S5, both Ma I-IJ socks have edges inside. If we perform the two tests, the pixels in row 1 match and the left matrix has an edge close to row 1. Therefore, the characteristics of the error in scan S5 can also be determined by -right leading. A similar analysis in scans S6 and SgK yields the same result, ie, the right pixel precedes the left pixel. FIG. 12 was constructed assuming that no alignment correction was performed in the scan question to demonstrate the logic of error characterization. However, in reality, since the inspection windows 164, 166 (Fig. 7a) are shifted between scans, the alignment matrix is rearranged to reduce the total alignment error.

Returning to Figure 8, the goodness detector (GL, Goodness)
The functions of sLogic) 184 will be explained. The purpose of the goodness detector is to provide an indication of the characteristics of the alignment. The goodness detector adds the number of vertical and horizontal edges detected in the left and right aligned pixels 0,3;0,4:1,3;1,4, divides by 16, and calculates the result is compared with the number of defects detected by defect detector 134 (FIG. 4). If the number of defects is smaller, alignment is considered acceptable. It should be noted that if the inspection window is severely misaligned, the number of defects will increase considerably in proportion to the misalignment and will exceed the above comparison value.

The circuit that performs this goodness test is the goodness logic PAL2.
28 recognizes horizontal edges in rows 3 and 4 and detects edges in the left and right alignment matrices, except that it occurs in the signals CRE, , CLE'.
Goodness logic PAL 228' operates similarly to stage logic 190. The X logic unit 222 pulses signals RB 3.4 and LB when detecting a vertical edge between rows 3.4 in the left or right matrix.
34 is generated.

CRE, CLE, RE34. LE34 are combined in an OR gate 230 and then divided by υ by a taviter 232. The result and the DEFECT signal from defect detector 134 (FIG. 4) are combined with exclusive OR gate 234.
are combined in The DEFECT signal is inverted by inverter 236 and then input to the direction input of GD counter 23B. This GD counter is the gate 234
It is enabled by the output of the pixel clock and clocked by the pixel clock. In practice, the GD count counts up by one at each of the 16 vertical and horizontal edges detected by the alignment matrix, and counts down by one at each defect detected. Therefore, a positive number on the GD counter indicates good alignment.

X and Y counters 224, 226, 194, 196
．． 198 (c x p,
The alignment processor determines how much alignment correction is required, and if so, which directional force/force. The alignment correction decision is based on the relative amount of net error and total samples. is equal to the number of leading edges on the left minus the number of leading edges on the right.
6 and the NXES counter 224. Total samples equals the number of left leading edges plus the number of right leading edges plus the number of matched edges. The stiffness value is calculated by NYTS counter 198 and NXTS counter 226.

When the absolute value of the net error exceeds V2 of all samples,
At least 75% of errors are left-first or right-first.

From this point of view, it is meant that this alignment error is significant enough to require correction. Note that this correction is performed in a direction determined by the characteristics of the net error.

Figure 13 is a graph showing the process of making this decision (here, CR indicates correction required, NCR indicates correction not required,
Each is shown below. ). Two variables are defined as functions of net error and total samples.

The variable called ``excessive enhancement (PE)'' is the net error (E
) plus the absolute value of the net error minus the total sample (T)
Demeru. The other variable called 'Negative Excess (NE)' is the negative net error plus the absolute value of the net error minus the total samples. It is plotted against normalized fE.

PE ranges from values of -T for EK at O to 1←T for E equal to 1.

If E is greater than or equal to T72, then PE= PE=
Since PE is 0 or more, alignment correction in the + direction is required. Similarly, the filter ranges from values of 1T for EK equal to 0 to +T'' for E equal to -T. Therefore, if NE is greater than or equal to 0, a one-way alignment correction is required. Defects are detected as alignment errors even if the two pixel memories are precisely aligned.Statistically, defects due to errors are concentrated at zero net errors, but in some cases they can be far from zero. By specifying the force and error weight points such that PEt or NE exceeds zero,
A non-correction band can be created around zero net error. This allows significant alignment errors to be corrected while eliminating the operation of searching for zero errors and responding to defects t as alignment errors.

The operation of alignment processor 186 during disasters is more complex than described above. First, PE and NE must be calculated in X, Y since alignment corrections are required in the X and Y directions.

Second, understand the hierarchical structure of alignment correction. That is, the X correction is performed before the X correction. The reason for this is that the total Y error can be measured in one scan due to the direction of movement of the alignment matrix through the inspection window, whereas the X error can only be measured one pixel at a time. Third, the alignment processor uses a weighted average of the net error and all samples from many previous scans to suit the responsiveness of the alignment correction. This weighted average acts to slow down the responsiveness with respect to alignment corrections when the alignment is acceptable over many recent scans, and increases the responsiveness if recent alignment errors are significant. Work like you do.

The five values are stored by alignment processor 186 and used to determine the significance of alignment errors. The positive excess function is calculated in terms of X and YK, and the accumulator
PI and YPE (not shown) are stored in K memory. A negative excess function is also calculated with respect to X and Y and stored in accumulators XNE and YN'E (not shown).
Ru. Goodness parameter (Goodn, ess Para
The accumulation of meter ) is stored in GOOD (not shown). Each of the five accumulators (1-1,/2048
) is attenuated by an exponential attenuation coefficient. At the end of each scan, the X and Y counters are read and an updated value for the accumulator is calculated. By adding the update value to the cumulative value, alignment correction is performed if the sum exceeds zero. If correction in the Y direction is required, the magnitude of correction is YEM/NYTS. Due to the time required to perform the division and determine the X correction, the scan continues and the X correction is performed after the next scan. If a correction in the X direction is required, the magnitude of the correction is l and this is done before the start of the next scan fL.

After the alignment correction is made, the accumulator is reinitialized to a negative value. Otherwise, the alignment error will be over-corrected by the time it takes for the accumulator to return to a negative value. The accumulator is reinitialized by setting it to a value equal to 1/4 of the value of the negative accumulator, and the negative accumulator is set to 3/4 of its original value.
will be initialized again. This allows the alignment correction to be
Final corrections can be made more quickly.

14a and 14b are flowcharts illustrating the operation of alignment processor 186. After the scan is completed, the X and Y counters 194, 196.

198.224,226 contains the net error and full sample results obtained in the scan. Firstly,
Y accumulator update, UYPE and UYNE
is calculated as shown in block 240.

For example, UYPE is N-YES plus NYE S
The absolute value of is minus NYTS. Next, block 242 examines the polarity of NYES.

If U'YPE is greater than zero, a significant amount of positive error has been found. Yes, UYPE
is added to the cumulative value to determine whether the error is significant in light of past errors. This test is performed at block 244, and if the sum is still negative, then
Block 246 performs calculations in the X direction. If the sum of t''L7 is positive as tested in block 244, a positive Y alignment correction is required in block 248.

If so, YEM, NYTS and G
D is the read power 1 from these counters and is stored in the final calculation. Also, the +Y skew flag is set for later use, the X and X counters are reset, and the next scan is started.

After the next scan starts, the accumulator is stored in block 25
Updated at 0. First, the GOOD accumulator sets GD to the current value GOOD in block 252.
o and by multiplying by an exponential damping factor. Next, smooth tightening is set and fc
Follow the flag to block 254. In this example, the +Y skew flag is set, so YP
Block 25 for updating E and YNE accumulators
Proceed to step 6.

Current value of YNE accumulator YNEo I'j: U
It is added to YNE and attenuated by the damping coefficient. 1/4 of that value is stored in YPE and 37'4 is stored in YNE. Proceeding further to block 258, Y/offsela), YSKW? calculate. The current value of the Y offset Y S KW o is read by the alignment processor from the memory address controller 132 and YEM/N
Subtract YTS from this value to update off-seller) YS
produces KW. Next, check Y S KWI and prove that it does not exceed the maximum value. The memory address controller uses YSKWlk to reposition the test window in the next scan.

Also, the XPE and XNE accumulators are attenuated by the attenuation factor, and at the end of the scan, the Y and X counters are reset to begin the next scan. Note that since two scans are required to perform the Y alignment correction, the color/return data at the end of the second scan is unnecessary.

Even when NYES is negative and −Y alignment correction can be performed using the accumulated YNEQ value, calculation is performed through a similar calculation path. The only difference between these calculation paths is
At block 260, the YPE and YNE accumulators are reinitialized as a function of YPE.

If the Y alignment error is not significant enough to warrant correction, proceed to block 246, the X calculation.

First, if the stage is moving in the -X direction, NX
Adjust the direction of the stage by reversing the polarity of ES. Additionally, UXPE and UXNE' are computed at block 262, followed by splitting the flow into positive and negative error branches at block 264. For positive branches, 1. At block 266, the validity of the accumulated positive update error is tested against all zeros. If this error is valid, block 268 sets the +X skew flag and sets the map and X offset.

Increment by X5KW'il. Next, at block 270, test X5KW i and if the magnitude is greater than 7, clamp to the maximum value. At block 272, the updates necessary for the next scan have been completed, so X and ? The counter is reset and the next scan begins. All branches of the X calculation end up in block 2
Reach 72. If a negative correction is required, the -X skew flag is set and X5KW is decreased at block 274.

The accumulator is updated on the next scan regardless of whether alignment corrections have been made. As mentioned above,
The G00D accumulator is updated and decayed at block 252. +X1ffc is -X If the skew flag is set, flow branches to block 27B or 280, and XPE and
Initialize N'FJ. If the flag is not set, at block 282, XPE
PE is updated only by n, which is attenuated by the damping coefficient,
XN'E is updated by UXNE and damped by the damping factor. Next, assuming Y skew 7 lag is not set, in block 284, Y
PE and YN'E are respectively UYPE and UYN
E and damped by the damping coefficient '117. This concludes the update of the accumulator. The alignment processor waits for the current scan to complete before making the next error update.

At the end of each scan, the X5KWO value is checked by a comparator and if its magnitude is greater than 1, the signal E
Set XCESS to true and set the stage direction and
The code 'e of 5KW is reflected in the EXDIR signal. These signals are used in the system timing controller as described below.

FIG. 15 shows a portion of the system timing controller 68 that adjusts the X dimension of the pixels to reduce misalignment in the X direction. In general operation, the system timing controller performs phase lock frequency multiplication. instrument (PLFM
, Phase-1ockedFrequency M
The encoder clock pulses from the X-axis encoder 286 are converted to full pixel clocks by multiplying the encoder clock by ultiplier 28B) and dividing the result by a divider 290. Fifth
The enable pixel clock signal discussed with respect to FIG. 6 is combined with the encoder clock at gate 292 to control the generation of the pixel clock.

X between reticle optical and database image
If there is an alignment error, the system timing controller can adjust the X dimension of the optical pixel to compensate. For example, if the database image was ahead of the optical image, larger optical pixels allow the optical image to catch up with the database. To increase the pixel size in the X direction, a slightly slower pixel-clock frequency may be used so that the stage moves slightly farther in the scan amount. It should be noted that care should be taken not to over-adjust the pixel dimensions, since measurements may be made with a photosensor that integrates the incident light over the duration of the pixel clock cycle.

The alignment correction device informs the system timing controller whether correction is required (EXCESS) and in what direction (EXDIR). Additionally, a scale compensator 294 is used to direct the vixel adjustment process. When first calibrating the inspection station 22,
The encoder clock signal and the optical image of the reticle are sent to the reticle inspection adapter 26 for full comparison with the database. At this time, the calibration coefficient is calculated,
and remembered. This calibration factor is used in a scale compensator to selectively adjust the size of the X pixels to eliminate calibration errors. Decoder 296 combines the scale compensator and alignment corrector and divides the result into divider 29
Send to 0. To adjust the pixel clock frequency,
Divider 290 divides by a slightly larger or smaller number depending on whether the +FM or -FM lines are enabled. Counter 298 counts the number of scans that adjust the pixel clock. Once the pixel adjustments have been accumulated at point 1, where one complete pixel has been added or subtracted, the counter outputs the signal INCX or DECX.
i to inform the memory address controller 132 via i.

Fast inspection times may be required even with low resolution. This corresponds, for example, to inspecting the reticle every 10 days and ignoring small defects.

In order to perform this low resolution, high speed inspection, two things occur. Firstly, the stage (i) moves at twice the normal speed and secondly, adjacent pixels combine to
The goal is to enlarge the resulting pixels. When the speed of the stage doubles, the multiplier of the multiplier 288 decreases,
Keep the same pixel clock frequency. Multiplier selector 300 instructs the multiplier which multiplication factor to use.

3 shows the first chou mapping process;

(a) shows a standard pixel structure. By doubling the stage speed and keeping the pixel clock constant, the pixels become rectangular as shown in (b). Adjacent rectangular pixels are combined according to the chart in Table 2, resulting in a large square pixel as shown in (C).

Table 1 (Truth table used to determine the polarity of the X-alignment error; Table 2 (truth table used for pixel combination for image compression) showing the method used by the alignment error detection circuit) Although the present invention has been described in terms of this embodiment, which is specifically designed to test all tests, it goes without saying that the invention is applicable to other embodiments as well.Thus, the invention is capable of various modifications based on the spirit of the invention. It is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a reticle inspection apparatus according to the present invention including an inspection station portion and a reticle inspection adapter portion; FIG. 2 is a diagram showing a stage movement sequence in the X and Y directions performed in an inspection operation according to the present invention; FIG. 3 is a diagram showing one swath of pixels formed as a result of stage movement in the X direction, FIG. 4 is a pixel generation and alignment correction circuit diagram of the reticle inspection apparatus of FIG. 1, and FIG. Timing diagram of the test station shown in Operating Mode (In this figure, (4) is the servo address trigger, (B) is the enable pixel contention clock, and (Q is the enable (2) pixel clock).
Address trigger (6) indicates enable defect detection; ), FIG. 6 is a block diagram of the scan synchronization circuit used to synchronize the measured and stored images of the reticle or haphazard mask during inspection operation, and FIG. A diagram of the left and right pixel memory showing relative positions, Figure 7b is a diagram showing the classification of pixels in the IJx, and Figure 8 is a block diagram of an alignment error detection circuit that detects alignment errors in the X and Y directions. , FIG. 9 is a logic diagram showing the first stage of Y alignment detection used by the alignment error detection circuit of FIG. 8, and FIG. 10 is a logic diagram showing the first stage of Y alignment detection used by the alignment error detection circuit of FIG. Figure 11 is a timing diagram showing the Y alignment detection function of the alignment error detection circuit in Figure 8, and Figure 12 is the X alignment detection function of the alignment error detection circuit in Figure 8. FIG. 13 is a graph showing the standardized alignment correction coefficient n calculated by the alignment processor section of the alignment error detection circuit of FIG. 8, and FIGS. 14a and 14b are calculations of the alignment processor circuit. 15 is a block diagram of a system timing control circuit used in the reticle inspection apparatus of FIG. 1, and FIG. 16 is a diagram showing the sequence of pixel mapping for image compression. 20... Reticle inspection device, 22... Inspection station, 261I/e-reticle inspection adapter,
40... Medium illuminator, 42. 44... Left and right inspection optical device, 56... RIA interface, 60. 62... Left and right "pixel memory, 66... Alignment correction device, 68... System timing control device, 70 ...Inspection station microprocessor, 98...Tape drive device, 1
00...Disk drive, 104--φ-
Pattern memory, 106 ・φ... Pattern generator, 1
08...Bitmap memory, 110...
Stage monitor, 112 ・@φ... Digital scan converter, 114, 116-ψshima sensor, 118, 1
20 ・−・ψanalog-digital converter, 12
2. 124 . . . Level converter, 126 . . . Buffer/switch, 130 . . . U column-c error detection circuit, 132 . . . Memory address control circuit, 13
4...Defect detector, 140...φ servo address register, 142...Comparator, 144 ・Q
@φ multiplexer, 148. 150... Servo address trigger, 154...
・e pixel address register, 158 ・・・・pixel trigger register, 158 ・etc., ratio scissor, 16
4,166...Inspection window, 172. 174-@hayashi/alignment matrix, 176, 178・φ
...Defect inspection matrix, 180...Y error detector, 182...X error detector, 186-...
Alignment Processor, 188...Fist Alignment Matrix Buffer, 190--...First Stage Logic Unit, 192
...Φ, second stage logic device, 194, 196,
198,224,226...Counter, 222
...X logic circuit, 230 ...OR gate,
232...-9% fiL238...GD counter, 286...X-axis encoder, 288 ・
... Multiplier, 290... Divider, 296...
・・Tecoder, 30.0−・φ・Multiplier selector. Patent applicant: KLA Instruments
Kogetsu Ration Agent Masaki Yamakawa (and 2 others) 1-1--7--
”-'IFIG, 1

Claims (1)

Claims: (1) an apparatus for optically scanning a patterned object such as a reticle, photomask, etc. in a selected manner and forming a scanned image of said object; a first memory device for storing a predetermined amount of said first data; a first memory device for storing a predetermined amount of said first data; a database device including a device storing information representing a pattern and converting the information into second data corresponding to the first data; a second memory device; and a speed at which the optical device scans the object. and a timing control device for storing in the second memory device an amount of second data corresponding to the scheduled amount of the first data;
and a defect detection device for inspecting the first and second data stored in a second memory device and generating a defect signal representing an undetected difference therebetween; Comparing the stored first and second data,
and the first and second defects inspected by the defect detection device.
Is the data defective? and a device for storing and/or displaying the defect signal. (2. In the apparatus according to claim 1, the optical scanning device includes an optical device that generates an optical image of a patterned object, and a device that moves the object in a predetermined manner with respect to the optical device. a movable stage apparatus, the detection apparatus comprising a linear array of N photodetectors disposed at points along the optical axis of the optical apparatus;
a device for scanning the array at a pixel clock rate coupled with a speed of movement of the stage assembly to form the effective area of the pixel segment. (3) In the device according to claim 2, the first
A defect detection apparatus characterized in that the expected amount of data is determined by the required number of most recent scans of an array of photodetectors. (4) In the device according to claim 3, the defect detection device scans a part of the planned amount of first data and a part of the planned amount of second data, and these are called inspection windows. A defect detection device characterized in that this position with respect to the predetermined amount of data is determined by an alignment correction device. (5) The apparatus according to claim 4, characterized in that in each pixel clock period, the alignment device inspects the alignment mud IJ located within the inspection window to determine its alignment. defect detection equipment. (6) The defect detecting device according to claim 5, wherein the defect detecting device inspects all data in the detection window I>x arranged within the inspection window. (7) In the device according to claim 1, the database device includes a medium reading device, a pattern memory that receives information from the medium reading device, and a pattern generating device that generates data from the pattern memory. , a defect detection device comprising: a bit map memory that stores data generated by the pattern generator; and a scan converter that converts the data stored in the bit map memory into second data. . (8) The apparatus according to claim 1, wherein the alignment correction device includes a buffer for receiving scheduled amounts of first and second data from the first and second memory devices; a logic device that compares orthogonal position components of the teeth and generates an orthogonal error signal; a logic device that measures all alignment characteristics of the first and second data and generates a good signal; responsive to the orthogonal error signal, correcting the alignment of the second theta test window with respect to the first theta test window;
and a processor that generates a skew control signal. (9) In the device according to claim 1, the timing control device controls the pixel clock rate in order to synchronize storage of the first data and storage of the second data in the first and second memory devices. A defect inspection device characterized by comprising a device for changing. A defect detection device according to claim 1, wherein the timing control device includes resolution selection means.