JPS59172891A - Still picture transmitter - Google Patents

Still picture transmitter

Info

Publication number
JPS59172891A
JPS59172891A JP58047401A JP4740183A JPS59172891A JP S59172891 A JPS59172891 A JP S59172891A JP 58047401 A JP58047401 A JP 58047401A JP 4740183 A JP4740183 A JP 4740183A JP S59172891 A JPS59172891 A JP S59172891A
Authority
JP
Japan
Prior art keywords
frame memory
address
still picture
entire
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58047401A
Other languages
Japanese (ja)
Inventor
Eiji Yonemoto
米元 英司
Akira Ito
明 伊藤
Yusaku Yamada
雄策 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58047401A priority Critical patent/JPS59172891A/en
Publication of JPS59172891A publication Critical patent/JPS59172891A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems

Abstract

PURPOSE:To recognize an entire picture in a short time as a rough still picture by controlling the sequence of picture data read from a frame memory storing a still picture data. CONSTITUTION:Address converting circuits ACN1 and ACN2 convert an address outputted at each 16 addresses from address counters ADC1 and ADC2 according to a control signal representing the number of transmission times from a control circuit CONT, access a frame memory MEM1, read and transmit the picture element. In selecting one transmission amount as 1/64, an entire rough screen is displayed on a receiving monitor for nearly 1sec at first. Then, accurate screen is displayed gradually in nearly 30sec.

Description

【発明の詳細な説明】 発明の技術分野 本発明は静止画像伝送装置に係わり特に短時間で全体画
像を認識可能な画像伝送方式に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a still image transmission device, and particularly to an image transmission method that allows recognition of an entire image in a short time.

従来技術及び問題点 従来の静止画像伝送装置は、全画素を画面の左上から右
下に向って順に伝送しているため全画面を伝送するため
に音声回線利用の場合約30〜60秒もの時間がかかり
これたけの時間をまたなければ全体画像を認識できなか
った。従ってダム等の監視システムなどにおいて7画品
質の低下を許しても全体を早くみたいという要求に答え
られなかった。
Prior Art and Problems Conventional still image transmission devices transmit all pixels sequentially from the upper left to the lower right of the screen, so it takes about 30 to 60 seconds to transmit the entire screen when using an audio line. The entire image could not be recognized until this amount of time had passed. Therefore, in monitoring systems for dams, etc., even if the image quality was allowed to deteriorate, it would not be possible to meet the demand for speeding up the overall process.

発明の、目的 本発明目的は静止ii!!illの伝送においておおま
かな全体画像を1秒程度の短時間に伝送し、その後全画
像を伝送することにより次第にその画面が精細になると
いう静止画像伝送方式を提供するにある。
Purpose of the Invention The purpose of the present invention is stationary II! ! To provide a still image transmission system in which a rough overall image is transmitted in a short period of about 1 second during ill transmission, and the screen gradually becomes finer by transmitting the entire image thereafter.

発明の構成 本発明は静止画像データを記憶しているフレームメモリ
からの画像データ読出し順序を制御することにより、最
初に短時間でおおまかな全体画像を表示するとともに次
に精細な画像を伝送するようにしたものである。
Structure of the Invention The present invention controls the order in which image data is read from a frame memory that stores still image data, so that first a rough overall image is displayed in a short time, and then a detailed image is transmitted. This is what I did.

この結果、ダム等の監視システムにおいて、全体画像を
まずみたいという要求に答えることが可能となった。
As a result, it has become possible to meet the demand for seeing the entire image first in monitoring systems for dams, etc.

発明の実施例 以下本発明を実施例に基づいて、詳細に説明する。Examples of the invention The present invention will be described in detail below based on examples.

第1図に静止画像伝送装置のブロック図を示す。FIG. 1 shows a block diagram of a still image transmission device.

送信部5ENDでTVカメラ信号がアナログ・デジタル
変換部A/Dでデジタルに変換されてフレームメモリ 
(MEMI)へ記憶される。従来はこのフレームメモリ
MEM1から順次画素データを呼出しDPCM符合化を
行い変調器(MOD)により変調して回線へ送出してい
た。受信部では復調器(DEM)により復調した後DP
CM復号してフレームメモリMEM2へ記1征する。こ
のフレームメモリMEM2に記憶された内容は常時ビデ
オ信号発生部VDGに読み出されD/A変換されモニタ
に表示されていた。
The TV camera signal is converted to digital by the analog/digital converter A/D in the transmitter 5END and stored in the frame memory.
(MEMI). Conventionally, pixel data was sequentially retrieved from the frame memory MEM1, subjected to DPCM encoding, modulated by a modulator (MOD), and sent to the line. In the receiving section, the DP is demodulated by a demodulator (DEM).
The CM is decoded and written to the frame memory MEM2. The contents stored in this frame memory MEM2 were always read out to the video signal generating section VDG, converted into D/A, and displayed on the monitor.

一方本発明では、第2図に示す様に、ディスプレイ画面
すなわち、フレームメモリを複数のブロック例えば16
X46ドツトの大きさで区分し。
On the other hand, in the present invention, as shown in FIG.
Classified by size of x46 dots.

各ブロックから1画素づつランダムに選択して。Randomly select one pixel from each block.

伝送する様にした。I set it to transmit.

従ってこの場合16回の伝送で、1画面の画像伝送が完
了する。図において、各ブロック内の数字は伝送される
順番を示している。
Therefore, in this case, the image transmission for one screen is completed after 16 transmissions. In the figure, the numbers within each block indicate the order of transmission.

第3回により、具体例を説明する。A specific example will be explained in Part 3.

図において、ADCl、ADC2はアドレスカウンタ;
 ACNI  ACN2はアドレス変換回路である。
In the figure, ADCl and ADC2 are address counters;
ACNI ACN2 is an address conversion circuit.

動作について、説明すると、アドレス変換回路AC’N
I、ACN2は制御回路CON T1 からの伝送回数
を示す制御イハ号に従って、アドレスカウンタADCI
、ADC2からの“16″おきに出入 力されるアドレスを、第8図に示す様に変換し。
To explain the operation, address conversion circuit AC'N
I, ACN2 is the address counter ADCI according to the control number indicating the number of transmissions from the control circuit CON T1.
, the addresses inputted and outputted every "16" from the ADC 2 are converted as shown in FIG.

フレームメモリMEMIをアクセスし1画素情報を読み
出して伝送する。
The frame memory MEMI is accessed, one pixel information is read out and transmitted.

本装置によれば1回の伝送量を1/64とすると、まず
1程度度で全体のおおまかな画面が受信モニタに表示で
き、その後30秒程度かけて次第に精細な画面が表われ
てくる。
According to this device, if the amount of transmission at one time is 1/64, a rough image of the entire screen can be displayed on the receiving monitor in about 1 degree, and then a finer screen gradually appears over about 30 seconds.

発明の効果 本発明によれば解像度の低い大まかな静止画像として全
体画像の認識を受信側にて短時間で行うことができる。
Effects of the Invention According to the present invention, the entire image can be recognized as a rough still image with low resolution in a short time on the receiving side.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、静止画像伝送装置の全体を示す図。 第2図は本発明の詳細な説明する図、第3図は本発明の
具体例を示す図である。 図中MEM1はフレームメモリ、ADCI、ADC2は
アドレスカウンタ+’ ACNI’、ACN2はアドレ
ス変換器である。
FIG. 1 is a diagram showing the entire still image transmission device. FIG. 2 is a diagram explaining the present invention in detail, and FIG. 3 is a diagram showing a specific example of the present invention. In the figure, MEM1 is a frame memory, ADCI and ADC2 are address counters +'ACNI', and ACN2 is an address converter.

Claims (1)

【特許請求の範囲】[Claims] TVカメラからの静止画像をフレームメモリーに記憶し
、記憶した静止画像を回線を通して送受信する静止ii
!ll像伝送装置において、フレームメモリを複数のブ
l」ツクに分割し、各ブロックから1画素づつ選択して
伝送するとともに、各プロ、7り内の画素の選択をラン
ダムに行なう様に゛アドレスカウンタ出力をアドレス変
換して、該フレームメモリをアクセスする様にしたこと
を特徴とする静止画像送装置。
Still II, which stores still images from a TV camera in frame memory and sends and receives the stored still images through a line
! In an image transmission device, the frame memory is divided into a plurality of blocks, one pixel is selected from each block and transmitted, and each block is set to an address so that the pixels within the block are randomly selected. A still image sending device characterized in that the frame memory is accessed by converting a counter output into an address.
JP58047401A 1983-03-22 1983-03-22 Still picture transmitter Pending JPS59172891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58047401A JPS59172891A (en) 1983-03-22 1983-03-22 Still picture transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58047401A JPS59172891A (en) 1983-03-22 1983-03-22 Still picture transmitter

Publications (1)

Publication Number Publication Date
JPS59172891A true JPS59172891A (en) 1984-09-29

Family

ID=12774085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58047401A Pending JPS59172891A (en) 1983-03-22 1983-03-22 Still picture transmitter

Country Status (1)

Country Link
JP (1) JPS59172891A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256284A (en) * 1984-06-01 1985-12-17 Nippon Telegr & Teleph Corp <Ntt> Animation picture transmission and reception system
JPS61220577A (en) * 1985-03-27 1986-09-30 Toshiba Corp Method for transmitting and displaying picture
JPH03160880A (en) * 1989-11-18 1991-07-10 Nec Home Electron Ltd Transmission system for dct-sq compressed still picture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256284A (en) * 1984-06-01 1985-12-17 Nippon Telegr & Teleph Corp <Ntt> Animation picture transmission and reception system
JPH0220197B2 (en) * 1984-06-01 1990-05-08 Nippon Telegraph & Telephone
JPS61220577A (en) * 1985-03-27 1986-09-30 Toshiba Corp Method for transmitting and displaying picture
JPH03160880A (en) * 1989-11-18 1991-07-10 Nec Home Electron Ltd Transmission system for dct-sq compressed still picture

Similar Documents

Publication Publication Date Title
JPS6211978A (en) Image accentuating circuit
JPH0359628B2 (en)
JPS6123468A (en) Picture processor
JPS59172891A (en) Still picture transmitter
JPS6073575A (en) Data display
JPH0741267Y2 (en) Still image transmission device
JPH0127622B2 (en)
JPS6339186B2 (en)
JPH02272972A (en) Still picture transmitter
JPS5821985A (en) Transmitting and displaying system of picture information
KR100202560B1 (en) Apparatus and method displaing gray-level image in television having fax function
JPH06303594A (en) Encoding system and decoding system for still picture
JPS5853825B2 (en) Image transmission method
JPH04239891A (en) Television system converter
JPS5848101B2 (en) Zukei Hatsuseisouchi
JPS63189057A (en) Device for compounding video signal
JPH0818934A (en) Image communication equipment
JPS5947914B2 (en) Color image encoding processing method
JPH0144067B2 (en)
JPH05120119A (en) Address converter
JPH0231582A (en) Picture displaying method
JPS60182284A (en) Digital transmission system
JPH0235504B2 (en)
JPS62235886A (en) High resolution television system
JPH04250774A (en) Coding system