JPS59172744A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain conductive connection of high reliability with upper layer wiring having no disconnecting part at the stepped portion and conductive metal filling a through hole having a wide interlayer connecting area by forming a through hole for conductively connecting the upper and lower layers after forming the upper layer wiring. CONSTITUTION:An interlayer insulating film 2 is formed on a lower layer wiring 1, moreover an upper layer wiring 4 is formed on the interlayer insulating film 2. Thereafter the photo resist mask pattern 5 is formed on the cover insulating film 3 with removal of said pattern from the through hole forming area 6. Next, a through hole 7 can be formed with the upper layer wiring 4 used as the mask of interlayer insulating film 2 by executing the reactive ion etching using, for example, the CF4+H2 gas through the mask pattern 5. Then, the through hole 7 is filled with a conductive metal 8 for conductive connection between the lower layer wiring 1 and the upper layer wiring 4. Moreover, the secondary cover insulating film 9 is deposited on the entire part and thereby a multilayer wiring completing the through hole connection can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, which includes a step of electrically connecting a lower layer wiring and an upper layer wiring through a through hole formed in an interlayer insulating film therebetween.

Conventionally, in multilayer wiring including lower layer wiring and upper layer wiring,
A through hole was formed under the upper layer wiring to connect the upper and lower layer wiring, and a conductive connection was made. That is,
FIG. 1 is a cross-sectional view of a wiring part of a semiconductor device manufactured by a conventional method. A through hole is provided in the film, a conductive metal is buried in the through hole and connected to the lower layer wiring 1, an upper layer wiring 4 is formed over the buried conductive metal to form a conductive contact, and then a cover insulation layer is formed. The entire surface is covered with the film 3. In the multilayer wiring formed in this way, dents occur in the through-hole portions of the upper layer wiring 4, leading to breakages in the upper layer wiring 4, and the through hole area is less than the area where the upper layer wiring and the lower layer wiring overlap. Therefore, there was a drawback that sufficient conductive metal could not be filled, resulting in poor connection between upper and lower wiring layers.

An object of the present invention is to provide a semiconductor device that eliminates the drawbacks of the conventional manufacturing method described above, eliminates the fear of disconnection at the through-hole portion, and provides highly reliable four-current connections between upper layer wiring and lower layer wiring. To provide a manufacturing method.

In the method of the present invention, after forming the upper layer wiring on the lower layer wiring via an interlayer insulating film, the upper layer wiring is covered with a cover insulating film, and a mask pattern for forming through holes is formed using photoresist on the cover insulating film. Then, the cover insulating film and the layer insulating film of the through-hole forming portion are etched away by reactive ion etching through the mask pattern to form a through hole in which the upper layer wiring and the lower layer wiring are exposed, and this through hole is removed. is embedded with a metal for conductive connection to make a conductive connection between the upper layer wiring and the lower layer wiring.

Next, the present invention will be explained by examples.

FIGS. 2(a) to 2(d) are cross-sectional views illustrating the manufacturing process of an embodiment of the present invention. First, in FIG. 2(a), an interlayer insulating film 2 is formed on a lower layer wiring 1, an upper layer wiring 4 is further formed on the interlayer insulating film 2, and then a cover insulating film 3 is formed.
A photoresist mask pattern 5 is shown formed on top of the through hole forming portion 6. Next, when reactive ion etching is performed using, for example, CF4+H2 gas through the mask pattern 5, the upper layer wiring 4
serves as a mask for the interlayer insulating film 2, and a through hole 7 shown in FIG. 2(b) is formed. Next, as shown in FIG. 2(C), the through hole 7 is filled with a conductive metal 8 to conductively connect the lower layer wiring 1 and the upper layer wiring 4, and further, as shown in FIG.
As shown in d), a secondary cover insulating film 9 is deposited over the entire surface, and a multilayer wiring with through-hole connections is completed.

According to the method of the present invention, after forming the upper layer wiring, a through hole is formed for conductive connection between the upper and lower wiring. Metals provide reliable conductive connections. In addition, after the upper layer wiring is formed, a through hole is made to connect the upper and lower wirings, and the connection location between the upper and lower wirings can be changed by simply changing the through-hole photomask, providing greater freedom in design. It also has the effect of increasing.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a multilayer wiring through-hole portion of a conventional semiconductor device, and FIGS. 2(a) to 2(d) are cross-sectional views in the order of steps for explaining the method of forming a multilayer wiring according to the present invention. It is. 1... lower layer wiring, 2... interlayer insulating film,
3...Cover insulating film, 4...Upper layer wiring, 5...Photoresist mask pattern, 6...
....Through hole forming part, 7 ....Through hole, 8 ....Embedded metal, 9 ....Secondary cover insulating film. Figure 1 Figure Z

Claims (1)

[Claims] A step of forming an interlayer insulating film on a lower layer wiring formed on a substrate, forming an upper layer wiring on the interlayer insulating film, and further growing a cover insulating film thereon. a step of forming a photoresist mask pattern for forming a through hole for connecting the lower layer wiring and the upper layer wiring on the cover insulating film; and a step of forming a photoresist mask pattern by reactive ion etching through the mask pattern. A process of successively etching and removing the cover insulating film and interlayer insulating film of the through-hole forming part, and burying the through-holes opened by the etching with a conductor - conductive connection between the E-layer wiring and the lower-layer wiring. A method for manufacturing a semiconductor device, comprising the steps of: