JPS59172271A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59172271A
JPS59172271A JP58045287A JP4528783A JPS59172271A JP S59172271 A JPS59172271 A JP S59172271A JP 58045287 A JP58045287 A JP 58045287A JP 4528783 A JP4528783 A JP 4528783A JP S59172271 A JPS59172271 A JP S59172271A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
grounding
electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58045287A
Other languages
Japanese (ja)
Other versions
JPH0449259B2 (en
Inventor
Kinshiro Kosemura
小瀬村　欣司郎
Masafumi Shigaki
雅文 志垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58045287A priority Critical patent/JPS59172271A/en
Publication of JPS59172271A publication Critical patent/JPS59172271A/en
Publication of JPH0449259B2 publication Critical patent/JPH0449259B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve gains at extra-high frequency by mounting a grounding terminal chip reducing ground inductance by shortening the length of a wiring. CONSTITUTION:With a semiconductor chip 21 into which a predetermined field- effect transistor is formed, bonding pads for a source electrode, a drain electrode and a gate electrode are shaped to the surface. A dielectric substrate is loaded on a grounding substrate 22. Grounding terminal chips 23 are fixed to the grounding substrate 22 while being adjoined to the semiconductor chip 21 by a brazing material 24 together with the semiconductor chip 21. The chips 23 consist of small pieces made of a good conductive metal with thickness equal to the semiconductor chip 21, and are composed preferably of gold foil pieces. Metallic wires 25 are grounded by connecting prescribed electrode pads and the terminal chips 23 through wire bonding after fixation.

Description

【発明の詳細な説明】 ■　発明の技術分野 本発明は、半導体装置、より詳しく述べるならば、接地
インタ゛クタンスを抑えた高周波用電界効果トランジス
タ（ＦＥＴ）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a high frequency field effect transistor (FET) with reduced grounding inductance.

（イ）従来技術と問題点 屯界効果トランジスタの半導体チップは放熱を兼ねて接
地基板上にろう材を用いて固着されており、ソース電極
、ドレイン電極およびダート電極の所定電極を接地する
ためには、この半導体チップ表面上に形成された所定電
極のホンディングミ４ツトと接地基板とがポンディング
ワイヤにて接続されている。−例としてソース電極の接
地方法の従来例を第１図および第２図に示す。所定の電
界効果トランジスタの作９込まれている半導体テップ１
は共晶合金（Ａｕ　Ｓｎ、Ａｕ　Ｇｅ、Ａｕ−５ｔなど
）のろう材２によって接地基板３上に固着されている。(B) Conventional technology and problems The semiconductor chip of a field effect transistor is fixed to a grounded substrate using a brazing material for heat dissipation, and in order to ground predetermined electrodes such as a source electrode, a drain electrode, and a dirt electrode. A bonding end of a predetermined electrode formed on the surface of this semiconductor chip is connected to a grounding board by a bonding wire. - As an example, a conventional method of grounding a source electrode is shown in FIGS. 1 and 2. Semiconductor step 1 in which a predetermined field effect transistor is fabricated
is fixed onto a ground substrate 3 by a brazing filler metal 2 made of a eutectic alloy (Au Sn, Au Ge, Au-5t, etc.).

この接地基板３は、例えば、無酸累鋼にニッケルメッキ
層（厚さ：１〜３μｍ）とその上に金メッキ層（厚さ：
２〜５μｍ）とを形成したものである。また、半導体チ
ップ１の両側には少し離れてほぼ同じ高さの誘電体（す
なわち、絶縁性）基板４が前述のろう材（図示せず）に
よって接地基板３に固着されている。この誘電体基板４
にはその表面に入力ストリップ線路５および出カストリ
ップ紳路６が前もって形成されている。これらストリッ
プ線路５および６は、例えば、厚さ１〜５μｍｎの金層
である。そして、半導体テップ１上のπイ昇効果トラン
ジスタの電極部（すなわち、ポンディングパッド）がワ
イヤポンディング法による金属ワイヤ（ν１」えば、金
線）７，８および９によって入力ストリップ線路５、出
力ストリップ線路６および接地基板３にそれぞれ接続さ
れている。This grounding board 3 is made of, for example, acid-free steel with a nickel plating layer (thickness: 1 to 3 μm) and a gold plating layer (thickness:
2 to 5 μm). Further, on both sides of the semiconductor chip 1, dielectric (ie, insulating) substrates 4 of approximately the same height are fixed to the ground substrate 3 by the aforementioned brazing material (not shown) at a distance. This dielectric substrate 4
An input strip line 5 and an output strip line 6 are preformed on its surface. These strip lines 5 and 6 are, for example, gold layers with a thickness of 1 to 5 μm. Then, the electrode part (i.e., the bonding pad) of the π-elevation effect transistor on the semiconductor chip 1 is connected to the input strip line 5 and the output by metal wires (ν1, for example, gold wire) 7, 8, and 9 by the wire bonding method. It is connected to the strip line 6 and the ground board 3, respectively.

例えば、ケ゛−ト電極ノやラド１０が金ワイヤ７によっ
て入力ストリップ線路５へ接続され、ドレイン電極パッ
ド１１が金ワイヤ８によって出力ストリップ線路６へ接
続さ扛、そして、ソース電極パッド１２が金ワイヤ９に
よって接地基板３に接地されている。特に、第２図に示
したように金ワイヤ９はろう制２のはみ出し分に触れな
いように少し離れた位置にて接地基板３に接続する必要
があるので、半導体チップ１の厚さが、例えば、１００
μｍであれば、金ワイヤ９の長袋は約２００／ｊｍとな
る。For example, the gate electrode pad 10 is connected to the input strip line 5 by the gold wire 7, the drain electrode pad 11 is connected to the output strip line 6 by the gold wire 8, and the source electrode pad 12 is connected to the input strip line 5 by the gold wire 7. It is grounded to the grounding board 3 by 9. In particular, as shown in FIG. 2, it is necessary to connect the gold wire 9 to the grounding board 3 at a slightly distant position so as not to touch the protruding portion of the solder 2, so that the thickness of the semiconductor chip 1 is For example, 100
If it is μm, the length of the gold wire 9 will be about 200/jm.

このような構造の電界効果トランジスタをそれほど篩〈
彦い周波斂域で動作させるのであれば開山はあまりない
が、超高周波数（８Ｇｌ（ｚ以上）で動作させるときＫ
ｉよ、金ワイヤによる接地インダクタンスのために利得
が抑制されてしまう。このことは、接地インダクタンス
の増加が超高周波数での利得の減少を招くことかられか
る。なお、例えば、長さ１叫で直径２５μｍの金ワイヤ
のインダクタンスは０．８ｎＨＲ１！である。A field effect transistor with such a structure is not so sieved.
If it is operated in a high frequency band, there will not be much opening, but if it is operated at a very high frequency (8Gl (above z))
i, the gain is suppressed due to the ground inductance caused by the gold wire. This is because an increase in ground inductance leads to a decrease in gain at very high frequencies. For example, the inductance of a gold wire with a length of 1 mm and a diameter of 25 μm is 0.8 nHR1! It is.

（つ）発、明の目的 本発明の目的は、接地インダクタンスを減らして超高周
波数での利イ８を向上さぜた電界効果トランジスタの半
導体装置を提供することである。(1) OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor device of a field effect transistor that reduces ground inductance and improves the gain at extremely high frequencies.

（Ａ　発明の油底 上述の目的が、接地基板と、該接地基板に固着された半
導体チップと、該半導体チップの表面に形成され、ソー
ス電極、ドレイン電極およびケ゛−ト電極を有しかつこ
れら電極のいずれかの電極が前記接地基板に接地される
電界効果トランジスタと、接地基板上に半導体チップに
近接して固着された導電性を有する接地ターミナルチッ
プと、前記接地される電極と前記接地ターミナルチップ
とを接続する配線とを具備して済る半導体装置によって
達成される。(A) The above-mentioned object of the invention is to provide a grounded substrate, a semiconductor chip fixed to the grounded substrate, a source electrode, a drain electrode, and a gate electrode formed on the surface of the semiconductor chip. a field effect transistor in which one of the electrodes is grounded to the ground substrate; a conductive ground terminal chip fixed on the ground substrate in close proximity to a semiconductor chip; the grounded electrode and the ground terminal; This is achieved by a semiconductor device that is provided with wiring for connecting to the chip.

本発明によると、配線の長さを短かくすることによって
接地インダクタンスを減らすことであや、接地ターミナ
ルチップを設けることでそのインダクタンスがある程度
発生するが接地インダクタンス全体から見ると配線によ
るものが大部分でターミナルチップによるものはほんの
わずかであり、接地インダクタンスの低減に寄与してい
る。According to the present invention, the grounding inductance is reduced by shortening the length of the wiring, and although some inductance is generated by providing a grounding terminal chip, most of the grounding inductance as a whole is due to the wiring. The contribution from the terminal chip is only small and contributes to the reduction of ground inductance.

（４）発明の実施態様 以下、添付図面に関連した本発明の好ましい実施態様例
によって本発明の詳細な説明する。(4) Embodiments of the invention Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the invention in conjunction with the accompanying drawings.

第３図に本発明に係る電界効果トランジスタの接地方法
の例を示す。所定の電界効果トランジスタの作り込まれ
ている半導体チップ２１はその表面にソース電極、ドレ
イン電極およびケ゛−ト電極のがンデンダパット（図示
せず）が形成されている。この半導体チップ２１が搭載
される接地基板２２は第１図での接地基板３と同じもの
で、無酸素鋼にニッケルメッキ層および金メッキ層を施
こされたものである。また、この接地基板２２には第１
図での誘電体（例えば、アルミナ）基板４が同様に搭載
されている。本発明による接地ターミナルチップ２３が
半導体チップ２１と共にろう材２４によって半導体チッ
１２１に近接して接地基板２２に固着される。この接地
ターミナルチップ２３は、半導体チップ２１と等しい厚
さを有する良導電金属の小片であり、好ましくは金箔片
である。ろう材２４としてＡｕ−８ｎ、Ａｕ−Ｇｅ、Ａ
ｕ−８ｉなどの共晶合金が使用される。ＡｕＳｎろう材
であれば、３００　℃程度に加熱することによって半導
体テップ２１およびターミナルチップ２３を接地基板２
２に固着する。固着後に、熱圧着法又は超音波ポンディ
ング法によるワイヤポンディングで金属ワイヤ（例えば
、金ワイヤ）２５を所定の電極パッド（図示せず）とタ
ーミナルチップ２３とに接続して接地をとる。金属ワイ
ヤ２５を最短距離となるように接続するならば３０μｍ
程度の長さで艮い。したがって、従来は１２０μｍの長
さの金属ワイヤで接地をとっていたが本発明の場合には
その約Ｈの長さの金属ワイヤで接地をとることができる
ので、接地インダクタンスも約％に低減することができ
る。このことによって超高周波で利得を従来よりも向上
させることができる。FIG. 3 shows an example of a method of grounding a field effect transistor according to the present invention. A semiconductor chip 21 in which a predetermined field effect transistor is built has on its surface a conductor pad (not shown) for a source electrode, a drain electrode, and a gate electrode. The ground substrate 22 on which the semiconductor chip 21 is mounted is the same as the ground substrate 3 in FIG. 1, and is made of oxygen-free steel with a nickel plating layer and a gold plating layer. Further, this grounding board 22 has a first
A dielectric (eg alumina) substrate 4 in the figure is similarly mounted. A ground terminal chip 23 according to the present invention is fixed to the ground substrate 22 together with the semiconductor chip 21 by a brazing material 24 in the vicinity of the semiconductor chip 121 . This ground terminal chip 23 is a small piece of highly conductive metal having the same thickness as the semiconductor chip 21, preferably a piece of gold foil. Au-8n, Au-Ge, A as the brazing material 24
A eutectic alloy such as u-8i is used. In the case of AuSn brazing material, the semiconductor tip 21 and the terminal chip 23 are connected to the ground substrate 2 by heating to about 300°C.
It sticks to 2. After fixing, a metal wire (eg, gold wire) 25 is connected to a predetermined electrode pad (not shown) and the terminal chip 23 by wire bonding using a thermocompression bonding method or an ultrasonic bonding method to establish grounding. If the metal wire 25 is connected at the shortest distance, it is 30 μm.
It has a certain length. Therefore, conventionally, grounding was done using a metal wire with a length of 120 μm, but in the case of the present invention, grounding can be done using a metal wire with a length of about H, so the grounding inductance is also reduced to about %. be able to. This makes it possible to improve the gain at ultra-high frequencies compared to the conventional method.

例えば、ケ９−ト長１μｍ１ゲート幅３００１１ｍを有
する砒化力゛リウム（ＧａＡｓ）を用いたショットキ接
合型電界欠ｊ果トランヅスタ１２　ＧＨｚ　　で動作さ
せるならば、本発明の場合には従来例よりも利得が約１
ｄＢ向士した。For example, if a Schottky junction field-deficient transistor using GaAs having a gate length of 1 μm and a gate width of 30,011 m is operated at 12 GHz, the gain of the present invention is higher than that of the conventional example. is about 1
dB Koushi did.

上述した実施態様例では金属ワイヤの配線を用いている
が、すｄ？ノン状るいはメツシュ状の金属配線でもよい
。In the embodiment described above, metal wire wiring is used. Non-shaped or mesh-shaped metal wiring may be used.

本発明では半導体チップ表面と接地ターミナルチップ表
面とはほぼ同一平面で従来例のような半導体チップ表面
と接地基板との段差がないので、ワイヤデンディングを
容易にかつ確果に行なうことができ、従来よりも多数本
の金属ワイヤを精度良く接続することができる。In the present invention, the semiconductor chip surface and the ground terminal chip surface are almost on the same plane, and there is no difference in level between the semiconductor chip surface and the ground substrate as in the conventional example, so wire ending can be easily and reliably performed. A larger number of metal wires can be connected with higher precision than before.

接地ターミナルチップは金箔片の他に不純物がドープさ
れかつ表面を金でメタライズしたシリコン片、或いは表
面が金でメタライズされたニッケル又は銅片で構成して
もよい。In addition to the gold foil piece, the ground terminal chip may also be composed of a silicon piece doped with impurities and whose surface is metallized with gold, or a nickel or copper piece whose surface is metallized with gold.

（ト）発明の効果 本発明に係る電界効果トランジスタは接地インダクタン
スが低減されておシ超高周波数で高性能動することがで
きる。(G) Effects of the Invention The field effect transistor according to the present invention has a reduced ground inductance and can operate with high performance at extremely high frequencies.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の電界効果トランジスタの部分多ｌ視図で
あり、第２図は第１図中の線■−Ｈに沿った断面図であ
り、第３図は本発明に係る電界効果トランジスタの断面
図である。 １・・・半導体チップ、２・・・ろう材、３・・・接地
基板、４・・・誘電体基板、５・・・入カストリップ絆
路、６・・・出力ストリップ線路、７，８．９・・・金
属ワイヤ、１０．１１．１２・・・デンディングパッド
、２１・・・半導体チップ、２２・・・接地基板、２３
・・・接地ターミナルチップ、２４・・・ろう材、２５
・・・金属ワイヤ。 嫁 Ｎ（′ｌ′） 鯨　　　　　　　餓FIG. 1 is a partial perspective view of a conventional field effect transistor, FIG. 2 is a sectional view taken along line -H in FIG. 1, and FIG. 3 is a field effect transistor according to the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Brazing material, 3... Grounding board, 4... Dielectric substrate, 5... Input strip bonding path, 6... Output strip line, 7, 8 .9... Metal wire, 10.11.12... Dending pad, 21... Semiconductor chip, 22... Ground substrate, 23
...Grounding terminal chip, 24...Brazing metal, 25
...Metal wire. Wife N ('l') Whale Starvation

Claims (1)

【特許請求の範囲】[Claims] １　接地基板と、該接地基板に固着さ扛た半導体チップ
と、該半導体チップの表面に形成され、ソース電極、ド
レイン電極およびケ゛−ト電極を有しかつこれら電極の
いずれかの電極が前記接地基板に接地される電界効果ト
ランジスタと、前記接地基板上に前記半導体チップに近
接して固着された導電性を有する接地ターミナルチップ
と、前記接地される電極と前記接地ターミナルチップと
全接続する配線とを具備してなることを特徴とする半導
体装置。1 A grounded substrate, a semiconductor chip fixed to the grounded substrate, and a source electrode, a drain electrode, and a gate electrode formed on the surface of the semiconductor chip, and any one of these electrodes is connected to the ground. a field effect transistor grounded to a substrate; a conductive ground terminal chip fixed on the ground substrate in close proximity to the semiconductor chip; and wiring that fully connects the grounded electrode and the ground terminal chip. A semiconductor device comprising:
JP58045287A 1983-03-19 1983-03-19 Semiconductor device Granted JPS59172271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58045287A JPS59172271A (en) 1983-03-19 1983-03-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58045287A JPS59172271A (en) 1983-03-19 1983-03-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59172271A true JPS59172271A (en) 1984-09-28
JPH0449259B2 JPH0449259B2 (en) 1992-08-11

Family

ID=12715093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58045287A Granted JPS59172271A (en) 1983-03-19 1983-03-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59172271A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415106A2 (en) * 1989-07-31 1991-03-06 Kabushiki Kaisha Toshiba Lead frames for semiconductor device
WO2013074846A1 (en) * 2011-11-15 2013-05-23 Qualcomm Incorporated Radio frequency package on package circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368074A (en) * 1976-11-29 1978-06-17 Nec Corp Microwave ic device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368074A (en) * 1976-11-29 1978-06-17 Nec Corp Microwave ic device and its manufacture

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415106A2 (en) * 1989-07-31 1991-03-06 Kabushiki Kaisha Toshiba Lead frames for semiconductor device
WO2013074846A1 (en) * 2011-11-15 2013-05-23 Qualcomm Incorporated Radio frequency package on package circuit
US9131634B2 (en) 2011-11-15 2015-09-08 Qualcomm Incorporated Radio frequency package on package circuit

Also Published As

Publication number Publication date
JPH0449259B2 (en) 1992-08-11

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