JPS59171312A - Digital-analog converting circuit - Google Patents

Abstract

PURPOSE:To obtain a D/A converting circuit where the operating speed is accelerated by providing an amplifier amplifying an output of the 1st ladder resistor circuit network and supplying the output to the 2nd ladder resistor circuit network so as to obtain an analog output corresponding to a digital signal inputted to a decoder from the 2nd ladder resistor network. CONSTITUTION:When digital signals D1-Dn are inputted to the decoder 18, switches SW1-SWn, SWY and SW1'-SWn' are controlled switchingly and selectively by an output of the decoder 18 in response to the digital signals. Moving contacts of n1-set of the low-order in the switch groups SW1-SWn are thrown to fixed contacts SW1b-SWnb and (n-n1)-set of switches of high-order are thrown to the fixed contacts SW1b-SWnb, then an analog signal Vont outputted from a ladder resistor circuit network 14 is expressed as shown in the Equation (where vref is a reference voltage). Through the constitution above, since no capacitor is used, the delay in the converting speed due to the charging and discharging time is not produced and high speed is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a successive approximation type D/A conversion circuit for obtaining linear approximation characteristics in, for example, audio PCM demodulation.

[Technical background of the invention]

In general, in audio PCM processing, because the tractram in the audio electrical residue is concentrated in a relatively low level region, large amplitude signals are relatively coarse and small amplitude signals are finely quantized, which is called bit compression and bit expansion. is being carried out.

Figure 1 (,) shows the currently used PCM (telephone)
It shows the encoding format of the bit compression characteristics on the μ companding side (the opposite is true for decompression). This characteristic is such that the interval between adjacent broken lines is twice as large, and each broken line is divided at equal intervals.

FIG. 1(b) shows an enlarged view of the section A-B in FIG. 1(,). FIG. 1(c) shows the encoding format, which is divided into sign bits, segment bits, and step bits as shown.

The characteristics shown in FIG. 1 above should be realized by an A/D converter, and when converted into a decoding format of a D/A converter, it becomes as shown in FIG. 2. In the figure, [ga'-υn-+'+ 2(vn-1'-vn-2')
j, and "gaj = 3 v n-1+ 2υ
It is n-21J.

Expanding this, it becomes as shown in the following formula.

vn゛=3τn-1'-2vn-2'...
・(1) υn-1'''=3vn-2' 2vn-
3'...(2)v4' = 31)5"
-2v2'...(n-2)V3'
=3v2″-2υ1′ ...(n-1)
τ2'=3v1'-2vo'...(n)
The sum of the above formulas (1) to (n) is [vH' = 211n-
1' + vl -2vo'J. Here vo′=
When φ v , l = unit step = 1, t'1
""1. νI == 3. ν5" 7 r va'
It can be expressed as -1.5p.

FIG. 3 shows a conventional A/D conversion circuit for obtaining the characteristics described in 1-C. In other words, Yongtan scolding is 2” (1:2
: 4° 8: 16: 32: 64° 128) One electrode of the 972 group CX1 to Cxs is collectively connected to the movable contact 5XOe of the switch S are the switch groups S X i
~S X 8 movable contacts 5X1e ~ 5X8e K are connected. The fixed contacts SXi & ~5xaa of the switch group Sx+~S
Connected to pivoting contact 5XAe, fixed contact 5X1b -5
x8b are collectively connected to terminal 11 to which reference voltages rf and f are applied, and fixed contacts 5x1d to S
Bd are collectively connected to the output terminal of the buffer circuit 12. Still, the fixed contact SXOa of the switch Sxo is grounded, and the fixed contact 5XAa of the switch S
is supplied with an analog input signal vln, and the fixed contact 5XAb is grounded. -1- Switch SXO
The movable contact sxnc is connected to the other input end of the controller 13, one input end of which is grounded. on the other hand,
The input end of the buffer circuit 12 is connected to a movable contact syoe of a switch SYO. This switch S y
The movable contact 5YQe of O has a capacitance ratio of 1:1:2.
:4:8, one electrode of the capacitor group cY1 to CY5 is connected.

The other electrode of the capacitor CY1 is grounded, and the other electrodes of the capacitors CY2 to CY5 are connected to movable contacts 5y1c to 5y4e of the switches sY1 to sy4, respectively. Fixed contact 5y1 of the above switches sY1 to SY4
a to 5Y4a are grounded, and fixed contacts 5y1b to 5Y4b
is connected to terminal 11 to which reference voltage vref is applied. And each of the above switches Sxo, Sx1 to Sxas
The switching of SXA+Syo and sy1 to sy8Y4 is controlled by the output of a decoder (not shown).

The operation of the above configuration will be explained with reference to FIG. First, in order to discharge the capacitor groups CX1 to Cxa, the switch SXQ is closed by the output of the decoder, and the movable contacts 5x of the switches S X1 to SX8 are closed.
1e ""' 5X9e fixed contact 5x1a~5xaa
and connect the movable contact 5XAe of the switch Sx to the fixed contact 5xAb. Next, when the movable contact 5xAe of the switch SXA is connected to the fixed contact 5XAa, the input signal (analog signal) (in) is supplied to the gears/inputs Cx1-Cx8 and charged. At this time, 1. The level of the potential Vx supplied to the /-taper 13 is -"in. Next, the switch S
Movable contact 5x1e He-8xBe fixed contact 5x1b
” Connect to 5xeb one after another.At this time, the potential vX
is 1.7v or 2ΔV depending on the gear/gushita capacity.
, 4ΔV, SΔ■.

It changes as 16ΔV... If this potential vX exceeds OV? When the output of the regulator 13 is inverted, the movable contact Sxl of this switch Sxi. is connected to the fixed contact 5xid to supply the output of the buffer circuit 13 as a reference voltage. That is, when the gears Cx1 to CX8 are discharged, the switch SYO is closed and the switch SY is closed.
The movable contacts SY1 e to SY4 e of 1 to Sy4 are connected to the fixed contacts SY11L - SY4! Connect to L and gear/disk C
Discharge Y2 to cY5, then switch sY1 to S
y4 movable contact 5Y1c -5y4c fixed contact 5y1
b ” Connect to 5y4b and set the reference voltage “ref”
6-Charge the four-stage gear Cyi to CY4. Then, the switches SY1 to SY4 are selectively connected to the fixed terminal 5y1.
By connecting a to SY4[L, the reference voltage applied to the capacitor Cxi is sequentially lowered to obtain the lower bits.

Note that when forming a D/A conversion circuit, a digital signal is supplied to a decoder (not shown), and each switch S xo □ S Gear Gushita CX1~CX by reversing the above operation.
It is sufficient to obtain analog signals from FI and CYi to CY5 via the configurator 13.

[Problems with background technology]

However, the above configuration has the disadvantage that the operating speed is slow because of the charging and discharging time of the gears and intermediate shutters.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to increase the operating speed of D/
An object of the present invention is to provide an A conversion circuit.

[Summary of the invention]

That is, in the invention of , a first switch group selectively connects one end of each resistor of the first ladder resistance network to the first or second potential supply source by the output of a decoder into which a digital signal is input. An amplifier is provided to connect each one end of the resistor ladder network, and to amplify the output of the first resistor ladder network and supply the amplified output to the second resistor ladder network. Further, a changeover switch is provided for selectively connecting the output end of the amplifier to one end of each resistor of the second ladder resistor network according to the output of the decoder, and one end of each resistor of the second ladder resistor network is provided. the first .
A second switch group is provided which is selectively connected to the output end of the amplifier via a second potential supply source or the changeover switch. An analog output corresponding to the digital signal input to the decoder is obtained from the second ladder resistance network.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 5, 14 is a ladder resistance network (second ladder resistance network) having a resistance value of R22R, and one end of each resistor of this network 14 is connected to a movable contact sw1 of the second switch group sw1 to SWn. e% 5Wr1e is connected. The fixed contacts swI & ~5WnlL of the switch group SWi ~s'5vTl are collectively connected to the reference voltage Vr.
, f (first potential) are connected to the terminal 15 to which fixed contacts 5Wib to SW, b are each grounded (second potential).
At the same time, the fixed contact SW, d-5Wnd is connected to the fixed contact s'wY1a-8- of the switch swy. The movable contact of the above switch swy. is amplifier 16
connected to the output end of the At the input end of this amplifier 16,
A reference potential is supplied from a ladder resistance network (first ladder resistance network) 17. The above ladder resistance network 17
One end of each resistor is connected to the first switch group SW1' to
It is connected to the movable contacts sw1 c' to 5Wne' of swn'. The fixed 9-contacts "W1a' □ SWn a' of the switch group sw1' to swn' are collectively connected to the reference power supply terminal 15, and the fixed contacts 5w1b' to 5Wnb
' are respectively grounded. And each of the above switches SW
1~swn, SWY and SWj +~SW,' are respectively switched and controlled by the output of the decoder 18 to which the digital signals D1~Dn are input, and the ladder resistance network 1
4 to analog signal V. It is configured to output ut. Note that each switch group is, for example, a MOS transistor,
Alternatively, a differential configuration of bipolar transistors is used.

The operation in the above configuration will be explained.

When digital signals D1 to Dn are input to the decoder 18, switches Sw1 to ffn, SWY and sw1 are activated by the output of the decoder 18 according to the digital signals.
'~Island 7 is selectively controlled.

At this time, the relationship between the above formulas (1) to (n) is 20R-2.
R Lug-Resistor Network 14. 2nd switch group SW, ~SW
o and a reference voltage source vref.

That is, the lower n1 movable contacts in the switch group SW1 to SWn are connected to the fixed contact SW (&~s'wn3 side), and the upper n-n1 switches are connected to the fixed contact SW.
11) When the analog signal output from the ladder resistor network 14 is set to vout in the state where it is input to the -swnb side, it is expressed by the following equation.

V ””Vref(2-'+2-2+"・+2-
"'+2-"1) ut 3 Therefore, v n' $ India in Figure 2 is realized.

On the other hand, in Fig. 2, each section is divided into equal parts, but τ
The interval □l-v n-11 is further divided into m equal parts.

That is, since the interval v, T-υn-1' is generated by the ladder resistance network 14 in FIG. 5, the reference voltage vrof applied to this ladder resistance network 14
is divided into m equal parts by the first ladder resistance network 17. Note that the negative characteristic can be obtained by reversing the polarity of the reference voltage vref.

According to such a configuration, since no capacitor is used, there is no reduction in conversion speed due to the charging/discharging time of the capacitor, and it is possible to increase the conversion speed.

FIG. 6 shows the configuration of a D/A converter using the polygonal line approximation method using the circuit shown in FIG.
A buffer circuit 27 is provided at the output stage of No. 6.

In addition, in the embodiment L, a D/A converter is explained.

However, as is well known, this circuit can also be used as an A/D converter. FIG. 7 shows its configuration. That is, the analog signal INa is sampled and held by the sample and hold circuit 28.
The output of the sample and hold circuit 28 is supplied to one input terminal of the comparator 29. The other input terminal of the comparator 29 is supplied with the analog output of the D/A conversion circuit 26 according to the present invention shown in FIG. supplied to [7] 1.1-The control unit 30 supplies control signals to each switch of the D/A conversion circuit 26, and also outputs the dizotal signals D1 to Dn.
get.

〔Effect of the invention〕

As explained above, according to the present invention, a D/A converter circuit capable of increasing the operating speed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an encoding format of bit compression characteristics on the μ companding side of a conventional PCM, and FIG. 2 is a diagram showing a decoding format of a D/A converter.
FIG. 3 is a diagram showing a conventional A/D conversion circuit, FIG. 4 is a diagram for explaining the operation of the circuit shown in FIG. 3, and FIG. 5 is a D/A according to an embodiment of the invention. The diagrams showing the conversion circuit, FIG. 6, and FIG. 7 are diagrams for explaining other embodiments of the present invention, respectively. 14... Second ladder resistance network, 15... Reference potential application terminal, 16... Amplifier, 17... First ladder resistance network, 18... Decoder, SW1 to Jun. ... Second switch group, SW1' to SWn'... First switch group, SWY... Changeover switch, "ref
...Reference potential (fp, l potential). Applicant's agent Patent attorney Takehiko Suzue 13-

Claims (1)

[Claims] The output of a first ladder resistance network and a decoder connected to one end of each resistor of the ladder resistance network and inputting a digital signal selectively connects one end of each resistor to the first or second power source. an amplifier that amplifies the output of the first ladder resistance network and supplies it to a second ladder resistance network; a selector switch selectively connected to one end of each resistor of the ladder resistor network;
is connected to one end of each resistor of the second ladder resistor network, and the output of the decoder connects one end of each resistor to the first... a second potential supply source or a second switch group selectively connected to the output terminal of the amplifier via the changeover switch, the analog output corresponding to the dizotal signal input to the decoder is connected to the output terminal of the amplifier; A D/A conversion circuit characterized in that it is configured to obtain data from a second ladder resistance network.