JPS59171310A - Input circuit - Google Patents

Abstract

PURPOSE:To make the operating permissible range by level ''1'' of input information hardly be changed even when a Vcc level is low or high by connecting a source of a depletion transistor (TR) to a drain of an enhancement TR of an input circuit having a conventional hysteresis characteristic. CONSTITUTION:When a level of an input terminal A is a threshold voltage of an enhancement TRQ2 or below with the level of the input terminal A transitted from ''0'' to ''1'', a TRQ3 is also turned off and an output terminal N1 of an E/D inverter is at level ''1''. The difference from a conventional circuit resides in that a source and a gate of a depletion TRQ6 being a constant current TR are connected to a drain of an enhancement TRQ5 being the 2nd driving circuit, a drain of a depletion TRQ6 is connected to a Vcc, thereby making hardly changed the operating permissible range of input information level ''1'' at the input terminal A depending on the difference of the level of the Vcc.

Description

[Detailed description of the invention] The present invention relates to an input circuit having hysteresis characteristics.

In general, in high-speed semiconductor memory devices, the current of each inverter increases because it is necessary to transfer information at high speed.

The change (di/dt) is large and noise is likely to occur in the reference potential (GND), and the transistors in the output circuit in particular have a large capacity and the output information changes from 1'' to 0# in several ns. A current of mA flows into the GNI (GNI) and generates large noise.Also, when all addresses are switched at the same time in the address inverter circuit, the old /dt becomes large.
Since a large amount of noise is generated on the iGND, the permissible operating range of input information becomes narrower. As a countermeasure to this problem, an input circuit having a hysteresis characteristic that is insensitive to noise is usually used.

FIG. 1 is an example of a conventional input circuit having hysteresis characteristics.

In FIG. 1, a depletion transistor Ql as a load transistor and an enhancement transistor Q2 as a drive transistor are connected to an output terminal N1 of an E/D inverter.

Connect the drain of the enhancement transistor Q3.

Leni 8 is deep V L :/) 97jiX%Q・
4° drain, and the gate is an inverter of the opposite phase of the output terminal N1 of the E/D inverter, p, ! Truly connected. The gate and source of Q4 of the depressed transistor are connected to GND. Enhancement transistor Q5 has a drain connected to Vcc, and a gate connected to a medium power terminal N.
Inverter I2 in phase with the inverter p〈, 〒 with 1
To! -su is '? /E is connected to the output terminal N1 of the inverter to form an input circuit having hysteresis characteristics.

Regarding the operation of this circuit, when the level of input terminal A changes from 10" to 1#, when the level of input terminal A is below the threshold voltage of enhancement transistor Q2, Q3 is also turned off. The output terminal N1 of the E/D inverter is "1" L/H.When the level of the input terminal A rises and begins to exceed the threshold voltage of Q2, the level of the output terminal N1 of the E/D inverter becomes "1". The bottom is exposed and the level of input terminal A is high j5 E
/D When the level of the output terminal N1 of the inverter becomes below the threshold voltage of If, the output of the inverter ■1 becomes 1''
and the enhancement transistor Q3 is turned on and E
The level of the output terminal N1 of the /D inverter is suddenly lowered to completely "0". At this time, in order to make the depletion transistor Q4 less susceptible to the characteristic fluctuations of the depletion transistor Q1, which is a load transistor,
The enhancement transistor Q5 is connected to the enhancement transistor Q3, and is connected to the output terminal N1 of the E/D inverter in order to perform an inverse 9 operation with the enhancement transistor Qβ and to be less susceptible to the characteristic fluctuations of the enhancement transistor Q2, which is a driving transistor. .

Next, when the level of the input terminal A changes from 61" to "OII", the operation is as follows: When the input terminal level is sufficiently at the "1" level, the output terminal N14 of the E/D inverter changes to "0". Even if the level of input terminal A starts to fall, when it is below the threshold voltage of inverter E1, enhancement transistor Q3 is ON and enhancement transistor Q5 is OFF, so during that time the output terminal of D/E inverter is at the level of N1. remains at 10''.Then, when the level of the output terminal N1 of the D/E inverter exceeds the threshold voltage of the isciverter 1, the enhancement transistor Q3dO, FF', i enhancement transistor → Then, Q5 is turned ON, and the output terminal N1 of the CD/E inverter is suddenly turned to →.1-.

The hysteresis characteristic is input information from '0'' to 01#.
When the input information changes from 1 to 0, the level is determined by the capabilities of the depletion transistor Q1, the enhanced multi-sistor Q2, and the rising transistor Q5, and when the input information changes from 1 to 0. is dible → si 1j: ntranji blood z (h and 5 enhancement →
Ratio and Enhancement Transition X/
Q3(r) suspension level is almost determined. It is desirable that the depletion transistor Q4 has various capabilities so that the ratio does not change significantly with respect to the characteristic fluctuations of the enhancement transistor Q2. 1 The characteristics of the conventional circuit shown in Fig. 1 are shown in Fig. 2, but Vcc=
It can be seen that there is a considerable difference in the level of input information "1#" in the hysteresis characteristics of 5.6 V and Vcc=4.4 V.

This is because the drain of the enhancement transistor Q5 is directly connected to Vcc, so the current capacity changes easily depending on the level of Vcc (when Vcc is high).

Input terminal A0 person information... Allowable operating range
1□ Although it is insensitive to push-up noise more than necessary, do not take a wide range of operation tolerance for input information "1#".
6.1.The purpose of the present invention is to eliminate the above-mentioned drawbacks and to provide a hysteresis characteristic in which the 1' tolerance range of the level of input information "1" does not easily change even when the V level is low or high. ′1″l with
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1: The input circuit with hysteresis characteristics of the present invention is a depleted transistor of a load transistor.
::・.

and drive transistor enhancement transistor.
Connect the drain of the enhancement transistor to the output terminal of the D/E inverter connected to the drain of the depletion transistor whose gate and source are grounded to GND. The impa-
The gate of the depletion transistor whose drain was connected to the first drive circuit and the drain of VCCK, and the gate of the enhancement transistor whose drain was connected to the source of the first drive circuit, which was connected to the output of an inverter with an opposite phase made by the FDM inverter. Connect to the inverter output of the same phase.
The source has a second drive circuit connected to the output terminal of the inverter, and has a circuit configuration with hysteresis characteristics that makes it difficult for the operating range of input information "1" to change even when the Vce level is low or high. do.

FIG. 3 is a circuit diagram of an embodiment of the present invention.

The difference in FIG. 3 from the conventional circuit shown in FIG. 1 is that the drain of the enhancement transistor Q5, which is the second drive circuit, is connected to the source and gate of the depletion transistor Q6, which is a constant current transistor. The drain is connected to vee, and the input information N of input terminal A is determined by the difference in the level of Vcc.
, 71 is changing the allowable operating range.

Next, the characteristics of the present invention are shown in FIG. 4. 3. According to the present invention (C), as shown in FIG. 5.
The levels of the 6V input information "1" are almost the same.

This means that when the output circuit information switches from "1" to 0', or when the address inverter circuit switches simultaneously, a large current flows into the GNI (GNI) in a short period of time, so even if noise occurs on the GND, it will cause noise. It is possible to provide an input circuit having a stable hysteresis characteristic that is insensitive to input information and can widen the operational tolerance range of input information NII+ even when Vcc is high.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an example of a conventional input circuit with hysteresis characteristics, Figure 2 is a conventional hysteresis diagram showing the relationship between input level and power level, and Figure 3 is an example of the present invention. A circuit diagram showing hysteresis characteristics, FIG. 4, is a diagram of hysteresis characteristics of the present invention. Ql, Q4, Q6...Depression y
i) Transistor, Q2. Q3. Q5...Enhancement type) transistor, It, I2...
Inverter, ■CC...Power supply, GND...
...Reference voltage, position, A...Input terminal. , 9-$-1) 2nd figure Iθ /, 5 3rd closed OND 4th closed opening

Claims (1)

[Claims] The drain of the enhancement transistor is connected to the output terminal of an E/D inverter consisting of a depletion transistor and an enhancement transistor, the source is connected to the drain of a depletion transistor whose gate and source are connected to a reference potential, and the gate is formed by the inverter. The first one connected to the reverse phase inverter output
The gate of the depletion transistor whose drain was connected to the drive circuit and the electrode, and the gate of the enhancement transistor whose drain was connected to the source were connected to the in-phase inverter output produced by the inverter, and the source was connected to the output terminal of the inverter. An input circuit comprising a second drive circuit and having hysteresis characteristics.