JPS59169694A - Solder and joining method thereof - Google Patents

Solder and joining method thereof

Info

Publication number
JPS59169694A
JPS59169694A JP4214583A JP4214583A JPS59169694A JP S59169694 A JPS59169694 A JP S59169694A JP 4214583 A JP4214583 A JP 4214583A JP 4214583 A JP4214583 A JP 4214583A JP S59169694 A JPS59169694 A JP S59169694A
Authority
JP
Japan
Prior art keywords
solder
lead
tin
alloy
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4214583A
Other languages
Japanese (ja)
Other versions
JPH0431800B2 (en
Inventor
Makoto Kitano
誠 北野
Toshihiro Yamada
山田 俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4214583A priority Critical patent/JPS59169694A/en
Publication of JPS59169694A publication Critical patent/JPS59169694A/en
Publication of JPH0431800B2 publication Critical patent/JPH0431800B2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262Sn as the principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To concentrate the strain in the thermally deforming stage of solder and to obtain a good bonded part by using the solder formed by adhering a low melting tin-lead alloy having a high content of tin on the surface of a high melting lead-tin alloy having a high content of lead and performing soldering at the adequate temp. between both m.p. CONSTITUTION:Solder 8 is manufactured by adhering alloys 8b, 8c, which has the compsn. consisting of >=60% tin and the balance lead and impurities and has a low m.p. and high yield stress, on a part or the whole of the surface of an alloy sheet 8a, which has the compsn. consisting of >=70% lead and the balance tin and impurities and has a high m.p. and yield stress. Such solder 8 is placed between a silicon plate 9 plated thereon with a nickel layer 10 and a copper plate 11, etc. of a semiconductor device, and both plates are soldered at the suitable temp. between the high m.p. of the main sheet 8a and the low m.p. of the auxiliary sheets 8a, 8b. The stress concentration in the thermal deforming stage of the solder 8 is thus prevented. The resistance to thermal fatigue of the solder is improved by controlling the thickness of the solder.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置などの部品の接着に用いられる半田
およびその接着方法に関するものでおる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solder used for adhering components such as semiconductor devices and a method for adhering the same.

〔発明の背景〕[Background of the invention]

従来、半導体装置は、シリコンおよびセラミックなどの
線膨張係数の小さい材料と、銅および鉄などの線膨張係
数の大きい材料とを、半田などの接着材によりa着して
構成されていることは周知のとおシである。このような
半導体装置に温度変化骨により破損するから半導体装置
の信頼性の低下する欠点がある。
It is well known that conventional semiconductor devices are constructed by bonding materials with a low coefficient of linear expansion, such as silicon and ceramics, and materials with a high coefficient of linear expansion, such as copper and iron, using an adhesive such as solder. This is Notooshi. Such a semiconductor device has the disadvantage that the reliability of the semiconductor device is lowered because it is damaged due to temperature changes.

上記のように鉛と錫を主成分とする半田では、半田付け
に伴う合金属の生成によシ熱疲労強度が低下する。この
メカニズムを第1図および第2図を参照して説明する。
As mentioned above, with solder containing lead and tin as main components, the thermal fatigue strength decreases due to the formation of alloy metals during soldering. This mechanism will be explained with reference to FIGS. 1 and 2.

第1図に示すように一対の板1a、1bを鉛と錫を主成
分とする半田2によシ半田付けを行った場合、前記板1
a、lbと半田2との境界には、板1a+ lbの成分
元素と半田2の成分元素から厚さ5μm程度の合金層3
a、3bが生成される。
As shown in FIG. 1, when a pair of plates 1a and 1b are soldered with solder 2 whose main components are lead and tin,
At the boundary between a, lb and the solder 2, an alloy layer 3 with a thickness of about 5 μm is formed from the component elements of the plate 1a+lb and the component elements of the solder 2.
a and 3b are generated.

例えば板1a、lbが銅製であるときには、前記合金層
3a、3bはCu3SnまたはCu6 Snsである。
For example, when the plates 1a, lb are made of copper, the alloy layers 3a, 3b are Cu3Sn or Cu6Sns.

この合金層3a、3bの生成に関与する鉛−錫系半田の
元素は錫だけであシ、tlとんどの場合に鉛は関与しな
いことが文献(日本金属学会々報第21号第8号、p6
281で明らかである。したがって、前記合金層3a、
3bと半田2との境界には、錫成分の低下した合金層4
a+ 4bが生成される。
The element in the lead-tin solder that participates in the formation of the alloy layers 3a and 3b is only tin, and it is reported in the literature (Japan Institute of Metals Bulletin No. 21 No. 8) that in most cases lead is not involved. , p6
281 is clear. Therefore, the alloy layer 3a,
At the boundary between solder 3b and solder 2, there is an alloy layer 4 with a reduced tin content.
a+4b is generated.

一方、鉛成分が70憾以上の半田では、錫成分が低下す
るに伴って降伏応力は低下する。この降伏応力すなわち
半田に1チのせん断ひずみを与えたときに発生する降伏
応力と鉛の割合との関係を図示すると第2図のようにな
る。この図よシ鉛が701以上と、残部が錫とからなる
成分組成の合金の降伏応力は0.9〜2 K4 f /
wx ”であシ、錫が401以上と、残部が鉛とからな
る成分組成の合金の降伏応力は1.2〜ZOKpf/■
2であることがわかる。また、このような半田接着構造
物(第1図に熱ひずみが発生した場合、錫成分の少ない
合金層4a、4bにひずみが集中するため、この部分は
熱疲労破壊を起しやすくなる。
On the other hand, in solder with a lead content of 70 or more, the yield stress decreases as the tin content decreases. The relationship between this yield stress, that is, the yield stress generated when a shear strain of 1 inch is applied to the solder, and the proportion of lead is shown in FIG. 2. As shown in this figure, the yield stress of an alloy with a composition of 701 or more lead and the remainder tin is 0.9 to 2 K4 f /
The yield stress of an alloy with a composition consisting of 401 or more tin and the balance lead is 1.2~ZOKpf/■
It turns out that it is 2. Further, when thermal strain occurs in such a solder-bonded structure (see FIG. 1), the strain concentrates on the alloy layers 4a and 4b, which have a low tin content, making these portions susceptible to thermal fatigue fracture.

さらに半田付は後の稼動中においても、錫と板の成分元
素の固体内拡数を生じて合金層が成長する。この現象は
錫のくわれと称され、半田の金属組織に悪影響を及ぼし
て強度の低下を招く恐れがある。
Furthermore, even during subsequent operation, soldering causes an expansion of the constituent elements of tin and the plate within the solid, resulting in the growth of an alloy layer. This phenomenon is called tin cracking, and may have an adverse effect on the metal structure of the solder, resulting in a decrease in strength.

前記のように半導体装置の半田接着部の熱疲労破壊は、
はとんどの場合、第1図に示す半田2と合金層3a、3
bとの境界の合金層4a、4bにおいて発生する。この
ような熱疲労破壊を防止する手段としては、半導体装置
の温度変化を小さくする手段および半田の熱ひずみが起
シにくい構造とすることが考えられる。ところが、前者
の温度変化を小さくする手段は、半導体装置の環境温度
を一定にする装−置および半導体装置から発生する熱の
放熱効率を向上させる部品を必要とする。
As mentioned above, thermal fatigue failure of solder joints in semiconductor devices is caused by
In most cases, solder 2 and alloy layers 3a and 3 shown in FIG.
This occurs in the alloy layers 4a and 4b at the boundary with b. Possible means for preventing such thermal fatigue failure include reducing temperature changes in the semiconductor device and creating a structure in which thermal distortion of the solder is less likely to occur. However, the former means for reducing temperature changes requires a device that keeps the ambient temperature of the semiconductor device constant and a component that improves the efficiency of dissipating heat generated from the semiconductor device.

一方、後者の熱ひずみを起シにく−する手段は、半田の
厚みを厚くすることが有効である。この理由を第3図を
参照して説明するに、同図は線膨張係数の小さい板5と
線膨張係数の大きい板6とを、半田7を介して接着した
後に加熱した状態を示したものである。その加熱前には
、板5,6の右端面は同一平面に形成されていたが、加
熱後には両板5,6の熱膨張係数差によシ、第3図に示
すように段差Δt(ぼソ一定)を生ずる。この場合、半
田7のひずみγは次の(1)で表わされる。
On the other hand, as a means to prevent the latter thermal strain from occurring, it is effective to increase the thickness of the solder. The reason for this will be explained with reference to FIG. 3, which shows a state in which a plate 5 with a small coefficient of linear expansion and a plate 6 with a large coefficient of linear expansion are bonded together via solder 7 and then heated. It is. Before heating, the right end surfaces of plates 5 and 6 were formed on the same plane, but after heating, due to the difference in thermal expansion coefficient between both plates 5 and 6, a step difference Δt( (constant). In this case, the strain γ of the solder 7 is expressed by the following (1).

γ=Δt/h           ・・・(1)この
(1)式よシ半田7の厚さhが大きいほど、半田7のひ
ずみγは小さくなる。しかるに半田7の厚さhを厚くす
るには、半田7の量を増加するだけでは目的を達成でき
ない。これは、半田7の自重および上板5の重さによシ
、融解した半田7aが流出するからである。
γ=Δt/h (1) According to equation (1), the larger the thickness h of the solder 7, the smaller the strain γ of the solder 7. However, in order to increase the thickness h of the solder 7, simply increasing the amount of the solder 7 does not achieve the objective. This is because the melted solder 7a flows out due to the weight of the solder 7 and the weight of the upper plate 5.

そこで下板6に突起を設ける加工を施し、機械1的に半
田7の厚さを確保する手段が提案されている(%開閉5
3−1399741゜この手段は突起の加工々程を必要
とし、かつこの加工には通常、プレス加工が用いられる
ので、半導体例えばシリコンおよびセラミックなどの脆
性材料には、前記突起を設けることが非常に困難である
Therefore, a method has been proposed in which the lower plate 6 is provided with protrusions to ensure the thickness of the solder 7 mechanically (% opening/closing 5
3-1399741゜Since this method requires a process for machining the protrusions, and press working is usually used for this process, it is very difficult to provide the protrusions on brittle materials such as semiconductors, such as silicon and ceramics. Have difficulty.

〔発明の目的〕[Purpose of the invention]

本発明は上記にかんがみ半田の熱変形時のひずみ集中を
防止し、また半田の厚さを自由に制御して、半田の熱疲
労強度を向上させることを目的とするものである。
In view of the above, the present invention aims to prevent strain concentration during thermal deformation of solder, freely control the thickness of solder, and improve the thermal fatigue strength of solder.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するために、鉛が70憾以上と
、残部が錫または錫に随伴する不純物とからなる成分組
成の高融点合金の表面の一部または全部に、錫が60憾
以上と、残部が鉛または鉛随伴する不純物とからなる成
分組成の低融点合金を適宜手段によシ接層して半田を製
作したものである。また、このような半田を用いた半田
付けは、前記高融点合金と低融点合金の両融点間の適宜
温度で行うようにしたものでおる。
In order to achieve the above object, the present invention has a high melting point alloy having a composition of 70 or more lead and the remainder being tin or impurities associated with tin. The solder is produced by layering a low melting point alloy having a composition of lead and impurities associated with lead with the remainder being lead or impurities associated with lead. Furthermore, soldering using such solder is carried out at an appropriate temperature between the melting points of the high melting point alloy and the low melting point alloy.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第4図において、8はシート状に形成された半田で、こ
の半田8は主シート8aの両側に副シート8b、8Cを
適宜手段例えば圧着、メッキ、蒸着などの手段によりそ
れぞれ接着して構成されている。前記主シー)8aは高
融点260〜327Cで、かつ降伏応力の小さい合金、
例えば鉛: 70 %。
In FIG. 4, reference numeral 8 denotes solder formed in the form of a sheet, and this solder 8 is constructed by adhering sub-sheets 8b and 8C to both sides of a main sheet 8a by appropriate means such as pressure bonding, plating, vapor deposition, etc. ing. The main sea) 8a is an alloy with a high melting point of 260 to 327C and a small yield stress,
For example, lead: 70%.

錫:30%からなる成分組成の合金を圧延加工して作ら
れ、前記副シー)8b、8cは低融点183〜232C
で、かつ降伏応力の高い合金、例えば鉛:4(1、錫=
60幅からなる成分組成の合金を圧延加工して作られて
いる。
Tin: Made by rolling an alloy having a composition of 30%, the sub-sea) 8b and 8c have a low melting point of 183 to 232C.
and alloys with high yield stress, such as lead: 4 (1, tin =
It is made by rolling an alloy with a composition of 60 mm.

第5図は本発明の半田接着方法の第一実施態様を示すも
のである。すなわち予じめニッケル層10がメッキされ
ている線膨張係数の小さいシリコン板9と線膨張係数の
大きい銅板11とを、前記半田8によシ、シかもその主
シー)8aの高融点と副シー)8b、8Cの低融点との
間のカ4宜温度で半田付けを行うことにより、シリコン
板9と銅板11を結合して半導体装置を製作することが
できる。
FIG. 5 shows a first embodiment of the solder bonding method of the present invention. That is, a silicon plate 9 with a low coefficient of linear expansion and a copper plate 11 with a high coefficient of linear expansion, which have been plated with a nickel layer 10 in advance, are applied to the solder 8. A semiconductor device can be manufactured by bonding the silicon plate 9 and the copper plate 11 by soldering at a temperature between the low melting points of C) 8b and 8C.

この場合、ニッケル層10と副シー)8bとの間には、
Nis an 、 Njs Sn4 、 Nis S−
などを主成分とする合金層12aが生成されると共に、
銅板11と副シー)8cとの間には、Cu38nl C
u6 Sns を主成分とする合金層12bが生成され
る。これらの両合金層12a、12bに含まれる錫は、
副シート8b、8cからそれぞれ供給されるので、主y
−18aの成分組成は変化しない。このように主シート
8aのいかなる部分においても、錫成分の低下によるひ
ずみ集中が起らないので、熱疲労強度゛は低下しないか
ら半導体装置の信頼性を向上させることができる。
In this case, between the nickel layer 10 and the sub-sea) 8b,
Nis an, Njs Sn4, Nis S-
An alloy layer 12a mainly composed of
Between the copper plate 11 and the sub-sheet 8c, there is Cu38nlC.
An alloy layer 12b containing u6 Sns as a main component is produced. The tin contained in both these alloy layers 12a and 12b is
Since they are supplied from the sub-sheets 8b and 8c, the main y
The component composition of -18a remains unchanged. In this way, since strain concentration due to a decrease in the tin content does not occur in any part of the main sheet 8a, the thermal fatigue strength does not decrease, so that the reliability of the semiconductor device can be improved.

従来、一対の板を半田によシ接着する場合、その半田の
厚さを100μm程度以上にすることは、困難であった
が、本実施例では高融点の主シート8aの厚さを確保で
きるので、半田8を任意の厚さに設定でき、かつ一様な
厚さを容易にうることかできる。また半田8の厚さを大
きくすると、前記(1)式よシ半田のひずみrは小さく
なるから、半田8の熱疲労強度を向上させることが可能
である。
Conventionally, when bonding a pair of plates with solder, it was difficult to increase the thickness of the solder to about 100 μm or more, but in this embodiment, the thickness of the main sheet 8a with a high melting point can be ensured. Therefore, the solder 8 can be set to have an arbitrary thickness, and a uniform thickness can be easily obtained. Furthermore, when the thickness of the solder 8 is increased, the strain r of the solder becomes smaller according to the equation (1), so that the thermal fatigue strength of the solder 8 can be improved.

第6図に示す第2実施態様は、前記高融点半田で形成さ
れた球状部15aの表面に、低融点半田15bを接着し
て構成された球状半田15によシ、一対の板13.14
を前記両融点間の温度で半田付けを行ったものである。
The second embodiment shown in FIG. 6 has a spherical solder 15 formed by bonding a low melting point solder 15b to the surface of a spherical portion 15a formed of the high melting point solder, and a pair of plates 13, 14.
Soldering was performed at a temperature between the two melting points.

このように球状半田15を使用すれば、球径だけの半田
厚さを確保できるから、半田15の熱変形時のひずみ集
中を防止し、半田15の熱疲労強度を向上させることが
できる。
By using the spherical solder 15 in this manner, the solder thickness can be ensured by the spherical diameter, thereby preventing strain concentration during thermal deformation of the solder 15 and improving the thermal fatigue strength of the solder 15.

この場合、板13の特定点17a、17bと、板14の
特定点16a、16bとを球状半田15によシ接着する
には、まず下板14の特定点16a。
In this case, in order to bond the specific points 17a, 17b of the plate 13 and the specific points 16a, 16b of the plate 14 with the spherical solder 15, first the specific points 16a of the lower plate 14 are bonded.

16b上に各球状半田15をそれぞれ設置し、高融点半
田15aおよび低融点半田15bの両融点間の温度で半
田付けを行う。ついで冷却して球状半田15を下板14
に固定した後に、上板13の特定点17a、17bを各
球状半田15の球状部15a上にそれぞれ設置し、前記
温度で再び半田付けを行えばよい。
Each spherical solder 15 is placed on the solder 16b, and soldering is performed at a temperature between the melting points of the high melting point solder 15a and the low melting point solder 15b. Then, it is cooled and the spherical solder 15 is attached to the lower plate 14.
After fixing, the specific points 17a and 17b of the upper plate 13 are respectively placed on the spherical portions 15a of the respective spherical solders 15, and soldering is performed again at the above temperature.

第7図に示す第3実施態様は、並置された任意数の球状
の高融点半田18aを低融点半田18bにより結合して
なる半田18を用いて、一対の板13.14を上記第2
実施態様(第6図)と同様にして半田付けしたものであ
る。このような半田18を用いると、球状半田18aの
直径だけの半田厚さを確保できるから、半田18の熱疲
労強度を向上させることができる。
In the third embodiment shown in FIG. 7, a pair of plates 13 and 14 are bonded to the second plate using solder 18 formed by bonding an arbitrary number of juxtaposed spherical high melting point solders 18a with low melting point solder 18b.
It is soldered in the same manner as the embodiment (FIG. 6). When such solder 18 is used, a solder thickness equal to the diameter of spherical solder 18a can be ensured, so that the thermal fatigue strength of solder 18 can be improved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半田の熱変形時の
ひずみ集中を防止し、また半田厚さを自由に制御するこ
とにより、半田の熱疲労強度を向上させることができる
。したがって、本発明を半導体装置に適用すれば、その
信頼性を向上させることができる。
As described above, according to the present invention, the thermal fatigue strength of the solder can be improved by preventing strain concentration during thermal deformation of the solder and freely controlling the solder thickness. Therefore, if the present invention is applied to a semiconductor device, its reliability can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第3図は従来の半田における熱ひずみのメ
カニズムの説明図、第2図は鉛−錫からなる半田の成分
組成と降伏力との関係を示す図、第4図は本発明の半田
の一実施例を示す断面図、第5図ないし第7図は本発明
の半田接着方法の実施態様を示す断面図である。 8.15.16・・・半田、8 a *  15 a 
+  18 a ・・・高融点合金、8b、8C,15
b、18b・・・低融点合金。 第  1  図 fJ z 図 rb  gIi合  表 第 3  図 第 4 図 不 5 図 不 乙  図 第 7 図
Figures 1 and 3 are explanatory diagrams of the mechanism of thermal strain in conventional solder, Figure 2 is a diagram showing the relationship between the component composition and yield strength of solder consisting of lead and tin, and Figure 4 is a diagram showing the relationship between the composition and yield strength of solder consisting of lead and tin. 5 to 7 are cross-sectional views showing an embodiment of the solder bonding method of the present invention. 8.15.16...Solder, 8 a * 15 a
+ 18 a...High melting point alloy, 8b, 8C, 15
b, 18b...low melting point alloy. Figure 1 fJ z Figure rb gIi Table Figure 3 Figure 4 Figure 5 Figure 7 Figure 7

Claims (1)

【特許請求の範囲】 1、鉛が70憾以上と、残部が錫に随伴する不純物とか
らなる成分組成の合金の表面の一部・または全部に、錫
が60釜以上と、残部が鉛または鉛に随伴する不純物と
からなる成分組成の合金を適宜手段によ〕接着したこと
を特徴とする半田。 2、鉛が70憾以上と、残部が錫または錫に随伴する不
純物とからなる成分組成の高融点合金の表面の一部また
は全部に、錫が60名以上と、残部が鉛または鉛に随伴
する不純分とからなる成分組成の低融点合金を適宜手段
によシ接着して製作した半田を、前記高融点合金および
低融点合金の両融点間の適宜温度で半田付けを行うこと
を特徴とする半田接着方法。
[Claims] 1. Part or all of the surface of an alloy with a composition consisting of 70 or more lead and the remainder impurities associated with tin, with 60 or more tin and the remainder lead or A solder characterized in that an alloy having a composition consisting of lead and accompanying impurities is bonded by an appropriate means. 2. Part or all of the surface of a high melting point alloy with a composition consisting of 70 or more parts of lead and the balance of tin or impurities associated with tin, with 60 or more parts of tin and the balance of lead or impurities associated with lead. A solder produced by adhering a low melting point alloy with impurities by an appropriate means is soldered at an appropriate temperature between the melting points of the high melting point alloy and the low melting point alloy. Solder bonding method.
JP4214583A 1983-03-16 1983-03-16 Solder and joining method thereof Granted JPS59169694A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4214583A JPS59169694A (en) 1983-03-16 1983-03-16 Solder and joining method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4214583A JPS59169694A (en) 1983-03-16 1983-03-16 Solder and joining method thereof

Publications (2)

Publication Number Publication Date
JPS59169694A true JPS59169694A (en) 1984-09-25
JPH0431800B2 JPH0431800B2 (en) 1992-05-27

Family

ID=12627768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4214583A Granted JPS59169694A (en) 1983-03-16 1983-03-16 Solder and joining method thereof

Country Status (1)

Country Link
JP (1) JPS59169694A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6187396A (en) * 1984-10-05 1986-05-02 株式会社日立製作所 Manufacture of electronic circuit device
JPS6471591A (en) * 1987-09-09 1989-03-16 Sumitomo Spec Metals Joining method for metal or alloy piece
JPH04270092A (en) * 1991-01-21 1992-09-25 Mitsubishi Electric Corp Solder material and joining method
JPH0596395A (en) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp Joining material, joining method and semiconductor equipment
EP0875932A2 (en) * 1997-04-30 1998-11-04 International Business Machines Corporation Semi-conductor substrates and methods
WO2024176947A1 (en) * 2023-02-22 2024-08-29 三菱電機株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6187396A (en) * 1984-10-05 1986-05-02 株式会社日立製作所 Manufacture of electronic circuit device
JPH0528000B2 (en) * 1984-10-05 1993-04-22 Hitachi Ltd
JPS6471591A (en) * 1987-09-09 1989-03-16 Sumitomo Spec Metals Joining method for metal or alloy piece
JPH04270092A (en) * 1991-01-21 1992-09-25 Mitsubishi Electric Corp Solder material and joining method
JPH0596395A (en) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp Joining material, joining method and semiconductor equipment
EP0875932A2 (en) * 1997-04-30 1998-11-04 International Business Machines Corporation Semi-conductor substrates and methods
EP0875932A3 (en) * 1997-04-30 1999-08-04 International Business Machines Corporation Semi-conductor substrates and methods
KR100294968B1 (en) * 1997-04-30 2001-07-12 포만 제프리 엘 Multilayer Solder Sealing Band for Semiconductor Substrate and Manufacturing Method Thereof
WO2024176947A1 (en) * 2023-02-22 2024-08-29 三菱電機株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0431800B2 (en) 1992-05-27

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