JPS59168748A - Digital signal receiving circuit - Google Patents

Abstract

PURPOSE:To simplify the identification of a digital signal by generating a divided voltage of the peak value of a received digital signal and supplying it to a comparator as a reference voltage. CONSTITUTION:A data transmission line 11 is connected to one input terminal 14 of a voltage comparator 13 via an impedance converting circuit 12. A peak value dividing voltage generating circuit 20 is connected between the data transmission line 11 and another input terminal 15 of the comparator 13. The peak value dividing voltage generating circuit 20 consists of a transistor 21 for detecting peak value capacitor 22 for holding peak, and voltage dividing resistors 23, 24, and feeds the reference voltage changed in response to the change in the peak value of the input digital signal to the comparator 13.

Description

TECHNICAL FIELD The present invention relates to a digital signal receiving circuit suitable for receiving digital signals during data transmission between a main device and a terminal device.

BACKGROUND OF THE INVENTION The amount of attenuation of a digital signal transmitted between a main device and a terminal device depends on the loss of the transmission path. Therefore, the level of the digital signal received by the main device or the terminal device is not necessarily constant. For this reason, the conventional data receiving circuit is equipped with an AGC circuit (1) for converting the pulse of an incoming digital signal into a waveform of a constant level, as shown in FIG. The digital signal ■0 controlled by this AGC circuit (1) is the reference voltage that is supplied to one input terminal of the voltage comparator (2) for data identification and is supplied to the other input terminal from the reference power supply (3). It is compared with VR, ie, a threshold value, as shown in FIG. As a result, the digital signal identification output shown in FIG. 2 (G3) can be obtained from the comparator (2). However, since the AGC circuit (1) is used, the receiving circuit becomes complicated and expensive.

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a digital signal receiving circuit that can easily and relatively accurately identify and detect digital signals.

Arrangement of the Invention To achieve the above object, the present invention provides an input terminal that connects one input terminal coupled to a transmission line of a digital signal, the other input terminal to which a reference voltage for identifying the digital signal is supplied, and the digital signal. and an output terminal that outputs an output that identifies the digital signal based on a comparison between the digital signal and the reference voltage, and the digital signal or the digital signal that is supplied to the one input terminal of the comparator. generates a peak divided voltage having a constant divided voltage value of the peak voltage value of the digital signal and that changes in response to a change in the peak voltage value in response to a signal corresponding to the peak voltage value; The present invention relates to a digital signal receiving circuit comprising a peak value divided voltage generating circuit that supplies a reference voltage to the other input terminal of the comparator.

Effects of the Invention According to the above invention, by simply generating a peak value divided voltage of a digital signal and supplying it to the comparator as a reference voltage, the digital signal can be divided into two parts, which is substantially unrelated to the level of the digital signal. It becomes possible to perform identification. Therefore, compared to the case where a conventional AGC circuit is used, the receiving circuit can be made simpler and at a lower cost.

Embodiment Next, a receiving circuit according to an embodiment of the present invention will be described with reference to FIGS. 3 to 6. In FIG. 3, the data transmission line (11) is connected to one input terminal (141) of the voltage comparator aJ via the impedance conversion circuit α. ) is compared with the reference voltage, that is, the threshold voltage, supplied to the other input terminal 0ω, and the digital signal is
Alternatively, it is configured to send out an output of "0" from the output terminal Qθ. The impedance conversion circuit O2 consists of a transistor (171) whose pace is coupled to the transmission line α1] and a resistor 08 connected between the emitter of this transistor aη and the ground common line. The collector of the transistor aη is connected to the +■ DC power supply (25), and the emitter is connected to one input terminal α of the comparator α3). Therefore, this impedance conversion circuit α2
is configured as an emitter-follower circuit and delivers a digital signal at a voltage substantially equal to the voltage of the transmission line circle.

Reference numeral (20) denotes a peak value divided voltage generation circuit, ie, a reference voltage generation circuit, which is connected between the data transmission line and the other input terminal α9 of the comparator aJ. This peak value divided voltage generation circuit consists of a peak value detection transistor υ connected to a transmission line (11), and a peak value detection transistor υ connected between the emitter of this transistor (21) and a common ground line. In addition to the value holding capacitor, there are two voltage dividing resistors (22) connected in parallel to this capacitor (22).
41, and provides the comparator (131) with a reference voltage that changes in response to changes in the peak value of the input digital signal.

Transistor C for peak value detection in the above peak value divided voltage generation circuit (a)? The collector of IJ is connected to the +V power supply line (c) similarly to the collector of transistor αη. Therefore, the transistor (21+ and the resistor K (
23) (241) constitute an emitter follower circuit, and a voltage substantially equal to the voltage of the digital signal supplied to the base of the transistor (211) is obtained at the emitter.2
The two voltage dividing resistors (28 (a)
This constitutes a voltage divider that divides the voltage into 1/R1+R2 and supplies it to the other input terminal a9 of the comparator a3 via the reference voltage line (c). In this embodiment, since R1=R2 is set, a partial pressure ratio of 1/2 is obtained.

When a digital signal arrives at the transmission line Uυ in Figure 3,
A corresponding digital signal VD of "1001" as shown in fal in FIG.
is obtained. On the other hand, the peak value divided voltage generation circuit (20)
is responsive to the digital signal in the transmission line circle, and f in FIG.
A reference voltage ■n shown in al is generated.

To explain this in detail, the peak value detection transistor (2υ is the digital signal) turns on in response to the pulse, and a voltage VP corresponding to the peak value of the pulse of the digital signal VD is obtained at its emitter. This is the capacitor (2
It is held at 21. That is, as shown in the circuit shown in FIG. 5, the peak value Vp of the digital signal VD on the transmission line aυ is used as a power source, and the pn junction between the base and emitter of the transistor circle is used as a switch to charge the capacitor (221). (After being charged to a certain voltage, the transistor CD will not turn on unless a digital signal higher than the charging voltage of this capacitor (2) arrives.On the other hand, if the digital signal VD is 0'' or During the period when the peak value of vn ■P is lower than the charging voltage of the capacitor @, the transistor (21J) becomes reverse biased and turns off as shown in Fig. 6. Therefore, the electric charge of the capacitor (22) is transferred to the resistor (23) ( 24).The value R2 of the resistor (value R1 of 231 and resistor I24)
The discharge time constant C (R1+R2) determined by the value C of the capacitor @ and the value C of the capacitor @ is set so as to obtain an envelope detection output.

The peak value VP of the input digital signal obtained across the capacitor (22) is the voltage dividing resistor C13+ (241 = 1/
2 and the reference voltage VR of VP/2 is applied to the comparator (13
Enter 1.

As a result, the comparator (1, reference voltage VR = Vp/
2 and the digital signal VD having the peak value ■P are compared, and the digital signal identification output shown in (bl in FIG. 4A) is obtained corresponding to the period in which the reference voltage VRjll is higher than the threshold value.

By the way, digital signal receiving circuits are used in various places together with, for example, terminal devices. Therefore, the input level of the digital signal arriving at the receiving circuit differs depending on the place of use. Now, if the receiving circuit shown in Fig. 3 is connected to a place where the transmission path has a large loss, a digital signal with a low peak value VP as shown in Fig. 4B (al) will be input. In other words, since the peak value divided voltage generating circuit (2) generates a reference voltage vR that is approximately 1/2 of the peak value VP of the low-level input digital signal, as shown in FIG. 4B. A digital signal shown in (bl in FIG. 4B) that exactly corresponds to the input digital signal of fat can be obtained at the output terminal a61 of the comparator (L31).

As is clear from the above, the following effects can be obtained according to the embodiment.

The circuit (a) that holds and divides the peak value ■P of the digital signal ■n has fewer parts and has a simpler configuration than the conventional AGC circuit (1), so costs can be reduced.

(B) When the receiving circuit is used in a place where the peak value Vp of the input digital signal is high as shown in FIG. 4A;
As shown in FIG. 4B, the peak value Vp of the input digital signal
Since a reference voltage VR of about half of the respective peak value Vp is automatically obtained both when the signal is used in a place where the temperature is low and when the signal is used in a place where the signal is low, accurate digital signal identification is achieved virtually regardless of changes in the place of use. Detection becomes possible.

C) Since the level of the reference voltage of the comparator (131) is relatively accurately set to approximately 1/2 of the peak value ■P of the digital signal VD, it is possible to accurately identify 0''''1'' of the digital signal. For example, R with a fundamental frequency of 80 kHz
Z-shiram pulse train to 0.5 mm telephone cable l
When the bit error rate was measured by transmitting the data via km and receiving it by the receiving circuit of this embodiment, it was found to be less than 1x10a.

Modification example (al) Operational amplifier AI and diode D shown in Figure 7
1. The digital signal VD may be input to a peak hold circuit consisting of a capacitor C1, and the peak value VP may be held by the capacitor c1.

(b) Instead of the transistor (21), a rectifier diode may be used to detect the digital signal, and the capacitor (221) may be made to hold the peak value ■P.

(In the C1 embodiment, R1=: R2, and 1/2 of the pulse
Although the threshold value, that is, the reference voltage VR is set at the height of , it may be changed in various ways.

(dl Impedance conversion circuit (12+) may be omitted.

(e) A level conversion circuit for the incoming signal is provided in the impedance conversion circuit α2, and a reference voltage that has a constant divided voltage value with respect to the peak value VP of the digital signal of the converted level is set as the peak divided voltage. It may also be sent out from the generating circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional receiving circuit, FIG. 2 is a waveform diagram showing the states of each part in FIG. 1, and FIG. 3 is a circuit diagram showing a digital signal receiving circuit according to an embodiment of the present invention. Figures 4A and 4B are waveform diagrams that theoretically show the states of each part in Figure 3, Figure 5 is an equivalent circuit diagram of the peak value divided voltage generation circuit in Figure 3 during charging, and Figure 6 is the FIG. 3 is an equivalent circuit diagram of the peak value divided voltage generation circuit during discharging, and FIG. 7 is a circuit diagram showing a modified example of the peak value hold circuit. (111...transmission line, a2...impedance conversion circuit, alpha comparator, circle...one input terminal, (
19...Other input terminal, Q61...Output terminal, α
D...Transistor, αa...Resistor, a-Power line, (A)...Peak value divided voltage generation circuit, eυ-
...Peak value detection transistor, (221' -...
Peak value holding capacitor, (231 (241... Resistor for voltage division, (c)... Reference voltage line. Agent Noriji Takano

Claims (1)

[Claims] il+ One input terminal coupled to a transmission line of a digital signal, the other input terminal supplied with a reference voltage for identifying the digital signal, the digital /l/ signal and the reference voltage. a voltage comparator having an output terminal that outputs an output that identifies the digital signal based on a comparison with the digital signal; and the digital signal or a signal corresponding to the digital signal supplied to the one input terminal of the comparator. in response to generating a peak divided voltage that has a constant divided voltage value of the peak voltage value of the digital signal and changes in response to a change in the peak voltage value, and uses the peak divided voltage as the reference voltage. A digital signal receiving circuit comprising: a peak value divided voltage generating circuit that supplies the other input terminal of the comparator; (2) The peak value divided voltage generation circuit includes a peak value hold circuit that holds the peak value of the digital signal, and divides the voltage held by the peak value hold circuit and supplies the voltage to the other input terminal of the comparator. 2. The digital signal receiving circuit according to claim 1, which is a circuit comprising: a voltage divider for supplying a voltage to a voltage divider; (3) The peak value divided voltage generation circuit includes a peak value detection transistor whose base is coupled to the digital signal transmission line and whose collector is connected to a DC power supply, and an emitter of the transistor and a ground line. 2. The digital signal receiving circuit according to claim 1, which is a circuit comprising a peak value holding capacitor connected between said capacitors and a voltage dividing resistor connected in parallel to said capacitor.