JPS59165298A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To update and reproduce optionally voice information having an optional content and length by providing a semiconductor storage element storing a voice signal and a counter control circuit storing the length of information and controlling the storage element at a time remained in the control circuit. CONSTITUTION:When a recording instruction is applied to a control circuit 11, a pulse from a frequency divider 6 is counted with the start of recording. A count stop signal is transmitted from the control circuit 11 by recording stop instruction so as to hold the counted number in a control circuit 10. The recording stop instruction resets a counter 9 at the reproducing operation and starts counting the pulse from the frequency-divider 6 and gives its output to the control circuit 11. The circuit 11 sets an RAM 8 to the read mode so as to transmit the data in the RAM 8 regularly to a data latch circuit 12. A read end signal is outputted when the count number stored in the control circuit 10 and the number of the counter 9 are coincident and resets the counter 9. When the counter 9 receives a reset signal, the reproduction is started again from the beginning of the information and this operation is continued until the next recording instruction is given.

Description

[Detailed Description of the Invention] The present invention provides sound? This relates to a device that records a warning and then repeatedly plays it back.

Conventionally, devices that repeatedly generate audio information of arbitrary length that requires updating use magnetic tape as the recording section.

Since it was composed of magnetic discs and other magnetic drums, movable parts were essential, which resulted in drawbacks in maintainability and the size of the device.

Also, the length of the information is undefined during playback.

To reduce the space between pieces of information.

In order to prevent information from overlapping, the equipment has become more complex. In general, ¥! When voice information is repeatedly provided, the length of the information is usually several minutes at most, considering the human memory capacity, so semiconductor memory devices are sufficient for practical purposes. . If the information does not necessarily exist, a method of speech synthesis using semiconductor memory elements has been put into practical use, but any content can be used.

The length information was updated arbitrarily and playback was not possible.

The present invention aims to eliminate these drawbacks.

Using RAM as a semiconductor memory element in the recording part,
The present invention provides a recording and reproducing apparatus that can arbitrarily update and reproduce voice information of arbitrary content and length, and this will be explained in detail below in terms of sections.

9 is a block diagram showing an embodiment of the apparatus of the present invention, in which 1 is an input terminal for recording signals, 2 is an audio amplifier, 3 is a low-pass filter, and 4 is an AD converter.

5 is a clock generator, 6 is a frequency divider, 7 is a data latitude circuit, 8 is a RAM, 9 is an address counter, 10 is a color control circuit for storing the length of information, 11 is a control circuit, and 12 is a control circuit. Data lanochi circuit, 13 is error detector, 1
4 is the DA converter, 15 is the low frequency filter, 1G is the sound? In the amplifier, 7 is an output terminal for an internal signal, 18 is an input terminal for a recording command, and 19 is an input terminal for a recording stop command.

First, in the operation of the recording system, a recording signal is applied to the input terminal 1 and amplified to a required level by the sound amplifier 2. Since the signal to be recorded is audio, the band is limited by a low-pass filter 3 with a cutoff of 4kl+z, inputted to the AD converter 4, and the clock of the clock generator 5 is used for one generation. and convert it into digital data. In the device 6 of the present invention, z4 A M is used for the recording part. Therefore, if the data is stored as is, even if the recording time is short, the RAM capacity will be enormous and the device will become a doll, so the 1 frequency divider 6 is used. is used to control the data lanochi circuit 7 and compress the data to the extent that normal sound quality is not impaired.Generally, a high-speed successive approximation type converter is used for AD conversion of audio, but in order to compress data to 17n .

To set the clock frequency to 1/n, the conversion time is: As a result, the human input signal changes during the conversion time, and the lower bits of the tental data output from the smart device become inaccurate, resulting in a conversion error and deteriorating the sound quality.

Therefore, generally, a sun full bold circuit is inserted before the +A L) converter 4 to eliminate the effect of the human input signal during conversion.

In the implementation, the clock frequency of the clock generator 5 is set to I
M Ilz and sufficiently high speed, and the output of the AD converter 4 is made into accurate digital data with a line return of 13 μs.

The same JfJj information is transferred to the data lanochi circuit 7 every 13 μS, but the frequency divider 6 is used to reduce the number of groups to 1/1.
By latching the data with a latch signal every 130μS set to 0, the data can be compressed to 1/10.As a result, the Sunful bold circuit becomes simple and the circuit becomes simple, and the RAM capacity can be reduced to 1/2 economically. /10.

The data latched by the data register circuit 7 is output to the data input bus of the RAM 8 by a timing signal from the control circuit 11, but the control circuit 11 outputs the counter output of the address counter 9 + A D g "r from the % unit 4. 13
Synchronization signal every μs and l'? I, upon receiving the recording command given from the i child 18, sends a control signal to the RAM 8 and the RAM
Set 8 to light mode. The data outputted to the data bus is regularly stored in the address of the RAM 8 specified by the address color 9, excluding the control circuit 11.

Next, in preparation for repeated playback, it is necessary to record the length of the information, and when a recording command is applied to the control circuit 1], a cent signal is sent from the control circuit 1 to the address counter 9 and the counter control circuit lO. The counter is set to zero, and at the start of recording, the frequency divider 6 counts pulses every 130 μs.

When a recording stop command is applied to the control circuit 11 via the terminal 19, the control circuit 1 sends out a reset signal to reset the address color/90 counter to zero and a count stop signal to stop the counter control circuit 100 counter. The counted number is held in the counter control circuit 10.

In the operation of the reproduction system, a recording stop command enters the address register 9 via the control circuit 11, resets the counter to zero, and starts counting pulses from the 1 frequency divider 6, simultaneously sending the counter output to the control circuit 11. This control circuit 1] sends an equal control signal to RAM 8 to put RAM 8 into read mode.

RAM in synchronization with the data from the control circuit 11
The data stored in 8 is regularly sent to a data lanote circuit 12.

No. 13 indicating that the W seeping out of the fresh information recorded in RA IV'l 8 has been completed is issued when the count held by the color control circuit 10 matches the count number in the address color/re9. This becomes a reset signal for the address counter 9.

When the address counter 9 receives a reset signal, the counter is returned to zero, and reproduction starts from the beginning of the P+ information, and this operation continues until a secondary recording command is applied to the terminal 18. As a result, reproduction can be repeated for a time corresponding to the length of the recorded signal.

The data latched in the data latch circuit 12.

The error detector 13 checks for code errors in line 1. -D
If the data is incorrect, an error detection signal is sent to the D/1.A exchanger 14. The FI converter 14 is controlled to prevent abnormal sound from being output.

The data is converted into an analog signal by a DA converter 14 and then passed through a low-pass filter 15. sound? The reproduced signal appears at the reproduction signal output terminal 17 via the amplifier 16. Note that the low-pass filter 15 is the same as the low-pass filter 3, and is also a sound filter. The amplifier 16 can be used in common with the audio amplifier 2 by switching between them during recording and reproduction.

Furthermore, a tone signal indicating the end of information can be easily added to the end of the reproduction signal by a recording stop command, and the division of information when introducing or resuming the information can be made clear.

Furthermore, the recording time can be extended using the RAM 8.7 address counter 9. It is clear that this can be done by expanding the counter control circuit IO and the control circuit 11.

During reproduction, by changing the clock frequency of the clock generator 5, reproduction can be easily performed at a speed different from that during recording.

As explained and clarified above, in the case of non-invention, recorded information ¥12
Since the playback period is determined according to the length of the message, not only can you listen to the information constantly, but you can also easily update or cancel the +i'W report.

It can be applied to provide weather, navigation, road, traffic reports, emergency information, etc. that change over time, and is highly reliable because no moving parts are required (it has the advantage of having a semi-permanent lifespan and being able to be miniaturized).

[Brief explanation of drawings]

The drawing is a block diagram of an embodiment of the apparatus of the present invention. 8 ・RAM made up of 8 half-sized memory elements. 10 Counter system t1 circuit, 2 Shin? Amplifier, 3...
・Low pass filter, 4... ADfi controller, 5. Clock generator, 6... Frequency divider, 7... Data latch circuit, 9.
...Address counter, 1]...Control circuit, 12-Data latch circuit, 13-Error detector, 14-DA converter, 15-Low pass filter, 16-Sosei amplifier. Patent applicant Japan Radio Co., Ltd.

Claims (1)

[Claims] Records audio information of undefined length that requires updating. In order to continuously and repeatedly reproduce the sound, the semiconductor memory element is provided with a semiconductor memory element that records at least the aging voice signal and a counter control circuit that stores the length of the information, and the semiconductor memory element is controlled by the time remaining in the counter control circuit. and repeatedly reproducing and transmitting the take of the semiconductor memory element.
2nd record Takasei device.