JPS5916428A - Oscillating output device - Google Patents

Abstract

PURPOSE:To output an output signal in matching with the phase of an input signal, by controlling a phase shift circuit to which an output of an oscillating circuit is inputted with a signal comparing the output of the oscillating circuit with an external input signal. CONSTITUTION:The input signal applied to an input terminal 1 is taken as a sinusoidal wave signal being continuous timewise having a single frequency component and is applied to phase comparison circuits 5, 6. The phase comparison circuit 5 compares the phase of the input signal with that of a signal having 0 deg. of phase and the phase comparison circuit 6 compares the phase of the input signal with that of a signal having 90 deg. of phase respectively and outputs a control signal in response to the phase difference of the two signals. Two signals having the phase of 0 deg. and 90 deg. are applied from the oscillating circuit 4 to a phase shift circuit 7, and the sinusoidal wave signal having a phase, e.g., the same phase as that of the input signal is outputted to an output terminal 2 by changing the ratio of mixing of the signals having phase 0 deg. and 90 deg. or their inverting signals, in response to the control signal from the circuits 5 and 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation output device that outputs an output signal that matches the phase of an input signal.

The present invention is particularly effective when the input signal is a burst signal, and furthermore, it provides a circuit device suitable for constructing a concrete circuit with an integrated circuit.

Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is a block diagram of main parts showing one embodiment of the present invention. In FIG. 1, 1 is an input terminal that supplies an input signal;
2 is an output terminal for taking out an output signal, 4 is an oscillation circuit, 5 and 6 are phase comparator circuits having the same configuration, and 7 is a phase shift circuit.

The oscillation circuit 4 outputs two or less output signals having mutually different phases, and supplies them to the phase comparison circuits 6, 6 and the phase shift circuit 7, respectively. Here, to simplify the explanation, it is assumed that there are two output signals from the oscillation circuit 4, and their phases are o.
o and 900. It is also assumed that the oscillation frequency matches or is very similar to the frequency of the input signal supplied to the input terminal 1. The error varies depending on the system in which the present invention is used, design specifications, etc., but for example, 1
It is about o-2 or less. The signal of phase o0 is supplied to the phase comparator circuit 5, and the signal of phase 9oO is supplied to the phase comparator circuit 6.

On the other hand, the input signal supplied to input terminal 1 is a temporally continuous sine wave signal having a single frequency component, and this is supplied to phase comparator circuits 5 and 6. Phase comparison circuit 5
is the input signal and the phase of the signal whose phase is 0°, and the phase comparator circuit 6
compares the phases of the input signal and the 90° phase signal, and outputs a control signal according to the phase difference between the two signals.

The phase shift circuit 7 is supplied with two signals having phases of 00 and 9o0 from the oscillation circuit 4, and is supplied with two signals having phases of 00 and 9o0 according to control signals from the phase comparison circuits 5 and 6.

The signal of phase o0 and the signal of phase 9o0 are inverted signals, that is, the signal of phase 18o0 and the signal of phase 27o0 are mixed, and the mixing ratio is changed to output a sine wave signal of a certain phase, for example, the same phase as the input signal. Output to terminal 2. This operation will be explained in more detail with reference to FIG. Note that the phase comparator circuits 6, 6 can be constructed by well-known circuits, and a specific circuit diagram will be omitted.

FIG. 2 is a preliminary electric vector diagram for explaining the operation of the phase shift circuit 7. As shown in FIG. In the figure, 20 is a vector indicating the input signal, and 21 is the phase o0 of the output signal of the oscillation circuit 4.
22 is a vector showing a signal with a phase of 90°, 23 is a vector showing a signal obtained by controlling the signal corresponding to the vector 21 by the control signal output from the phase comparator circuit 5, and 24 is a vector. 25 is a vector obtained by combining the vectors 23 and 24, and the output obtained at the output terminal 2. Indicates a vector of signals. The phase shift circuit 7 receives the phase 00 from the oscillation circuit 4 and the phase 9o0.
2 signals from the phase comparison circuits 5 and 6, that is, the signals corresponding to the vector 21 and the vector 22.
These signals are converted into signals corresponding to vectors 23 and 24, respectively, using two control signals, and further synthesized into a signal corresponding to vector 2°.

A specific example of the phase shift circuit 7 is shown in FIG. In the figure, 31 to 42 are transistors, and 61 to 42 are transistors.
54. 56 to 69 are signal input terminals, eO is an output terminal,
61 and 62 are emitter resistors, 63 is a load resistor, and 66 is a DC power supply terminal. Transistors 31 and 32.3
3 and 34, 38 and 36.37 and 38.39 and 40.4
1 and 42 each form an emitter-coupled differential amplifier. These differential amplifiers can be emitter-coupled via emitter resistors as necessary for stability, gain adjustment, etc., but are omitted from the diagram.

Further, a DC voltage (Iasumi pressure) is applied to the bases of the transistors 31 to 42 by a well-known circuit, but this is not shown in the figure.

Input terminals 61 and 63 have vector 2 in FIG.
1 and the signal corresponding to vector 22, that is, the signal of phase 0° from oscillation circuit 4 in FIG.
0 signals are provided, each being transmitted to the bases of transistors 31 and 32. Input terminals 62 and 54
is supplied with a signal of phase 18o0 and a signal of phase 270° from oscillation circuit 4 in FIG. 1, and each is transmitted to the bases of transistors 32 and 34. Transistors 31 and 32, 33 and 34 have a common emitter resistor 61.
62, the input signals at the input terminals 52 and 54 operate in the same way even if the input terminals 52 and 54 have a fixed DC voltage, based on the operating principle of a differential amplifier. In any case, when the above signals are supplied to the input terminals 51 to 64, the collectors of the transistors 31 to 34 have a phase of 0.
o.

A signal current of 180°, 900.2700° flows, and these are connected to transistors 35, 36, 37, 38°, 39, and 4.
0.41 and 42 emitters, respectively.

Input terminals 66 and 57 are supplied with a control signal from the phase comparator circuit 6 of FIG. 1, and input terminals 58 and 69 are supplied with a control signal from the phase comparator circuit 6 of FIG. 1, respectively. Input terminal 56
When the voltage supplied to input terminal 67 is higher than that at input terminal 67, more than half of the collector current of transistor 31 flows through transistor 35. More than half of the collector current of transistor 32 flows into transistor 38, this current is transmitted to load resistor 63, and output terminal 60 receives phase 180.
An output signal of ° appears. This output signal is a signal corresponding to vector 23 in FIG. Therefore, the magnitude of the vector 23 indicating the output signal changes depending on the input voltages of the input terminals 56 and 57, and the phase becomes 0° depending on the magnitude relationship.
The signal is a vector indicating a signal with a phase of 180°.

In exactly the same way, an output signal corresponding to the vector 24 shown in FIG. 2 appears at the output terminal 6o depending on the magnitude of the voltages supplied to the input terminals 58 and 59 and their magnitude relationship.

Transistors 35 and 36.3 are connected to input terminals 57 and 69.
Since 7, 38, 39, 4041, and 42 form a differential amplifier, the same operation is possible even with a fixed DC voltage.

The load resistance 63 is a transistor 36.38.40.42
Since the outputs of these transistors are added and combined, an output signal corresponding to vector 25 in FIG. 2 is obtained at output terminal 60.

Phase comparator circuits 6 and 6 respectively compare the phase of the input signal supplied from input terminal 1 and the phase 00 (currently 1800).
and a signal having a phase of 90° (or 270°) to generate a signal related to the phase difference, such as a proportional voltage, which can be constructed using well-known techniques. However, the output may be one or a pair obtained by using a suitable differential amplifier.

FIG. 4 is a block diagram of main parts showing another embodiment of the present invention. Components having the same functions as those in FIG. 1 are given the same reference numerals. In FIG. 4, 8 and 9 are sample and hold circuits, signals to be held are supplied from phase comparison circuits 5 and 6, respectively, and their outputs are coupled to a phase shift circuit 7. Reference numeral 3 denotes an input terminal for a sampling pulse which determines the period to be sampled and held, and is connected to sample and hold circuits 8 and 9. FIG. 5 is a waveform diagram showing signal waveforms of the main parts for explaining the operation of FIG. 4, and the horizontal axis shows time.

Hereinafter, FIG. 4 will be explained in detail together with FIG. 5.

FIG. 6(a) is a diagram showing an input signal supplied to the input terminal 1 of FIG. 4. The input signal is a sine wave signal having a single frequency as shown in FIG. 6(b).

It is a so-called burst signal that is sampled only during the period from time t to time t2. Figure 5(C) shows the oscillation circuit 4
FIG. 3 is a diagram showing output signals from
shows the signal. FIG. 6(d) shows a sampling pulse supplied to the input terminal 3.

In FIG. 4, the signals shown in FIG. 5(a) from the input terminal 1 and the signals shown in FIG. 5(c) from the oscillation circuit 4 are supplied to the phase comparison circuit 6 from the input terminal 1. A corresponding signal is output from the phase comparator circuit 6 and transmitted to the sample hold circuit 8. The input terminal 3 of the sample and hold circuit 8 is supplied with the sampling pulse shown in FIG. It is transmitted to circuit 7. Furthermore, after time t2, time t
2 is maintained and transmitted to the phase shift circuit 7. The phase comparator circuit 5 is designed so that the time required to generate a control signal according to the phase difference between the two input signals is shorter than the period from time t1 to t2.
The control signal held by the sample and hold circuit 80 has a value sufficient to output a desired signal at the output of the phase shift circuit 7. The phase comparator circuit 6° sample hold circuit 9 also operates in exactly the same manner, but this system controls the phase shift circuit 7 with respect to the signal of phase 9o0 among the outputs of the oscillation circuit 4. The phase shift circuit 7 has exactly the same function and operation as the phase shift circuit 7 shown in FIG. ) is obtained.

As described above, according to the present invention, a stable oscillation output that is phase synchronized with the input can be obtained with a relatively simple circuit configuration. In particular, since the phase shift circuit is constructed without using many components such as capacitors and coils, it provides a circuit device that is optimal for integrated circuits with a limited number of pins.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main part of an embodiment of the present invention, Fig. 2 is an electric vector diagram for explaining the operation of the phase shift circuit used in the same embodiment, and Fig. 3 is a concrete diagram of the phase shift circuit. A wiring diagram showing an embodiment, and FIG. 4 is a block diagram of main parts of another embodiment of the present invention, and FIGS. 5(a), φ), and (C). (d) is a signal waveform diagram of each part in FIG. 4. 1...Input terminal, 2...Output terminal, 4
...Oscillation circuit, 6,6 ... Phase comparison circuit, 7 ... Phase shift circuit, 8.9 ... Sample hold circuit, 31-42. ...Transistor, 61.62...Resistor, 63...Load resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5-B! View-139=

Claims (3)

[Claims] (1) an oscillation circuit, two or more phase comparator circuits each receiving external input signals and two or more oscillation outputs having different phases from the oscillation circuit; An oscillation output device comprising: a phase shift circuit that receives the oscillation outputs having different phases and is controlled by the outputs of the two or more phase comparison circuits. (2) Claim (1) characterized in that the phase shift circuit is configured to be controlled by the outputs of two or more sample and hold circuits that receive the outputs of two or more phase comparison circuits as inputs. ) The oscillation output device described in section 2. (3) The oscillation output according to claim (1), wherein the phase shift circuit is configured to include a double balanced differential amplifier of 2 m or more and a common output load resistance. Device.