JPS59163981A - Image pickup device - Google Patents

Image pickup device

Info

Publication number
JPS59163981A
JPS59163981A JP58037727A JP3772783A JPS59163981A JP S59163981 A JPS59163981 A JP S59163981A JP 58037727 A JP58037727 A JP 58037727A JP 3772783 A JP3772783 A JP 3772783A JP S59163981 A JPS59163981 A JP S59163981A
Authority
JP
Japan
Prior art keywords
clamp
circuit
output
signal
image pickup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58037727A
Other languages
Japanese (ja)
Inventor
Toshio Kaji
敏雄 鍛冶
Shinji Sakai
堺 信二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP58037727A priority Critical patent/JPS59163981A/en
Publication of JPS59163981A publication Critical patent/JPS59163981A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/16Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To improve the yield by controlling a clamp means so as not to clamp a defective part in an image pickup device using an image pickup device. CONSTITUTION:After the duty is improved from an output of a device 100 by a sample-and-hold circuit 12, the result is inputted to a clamp pulse control circuit 13 to detect whether or not any defective signal exists in an optical black period. A clamp pulse applied to a clamp circuit 20 of the next stage is controlled in response to this detected output. DC regeneration is applied to a pedestal level into a reference black level at the clamp circuit 20 and various corrections are given at a process circuit 25 and the result is inputted to an encoder 30.

Description

【発明の詳細な説明】 (技術分野) 本発明は撮像装置、%に改良された直流再生回路を有す
る撮像装置に関するものである。
TECHNICAL FIELD The present invention relates to an imaging device and an imaging device having a highly improved direct current regeneration circuit.

(従来技術) 従来、COD等の撮像デバイスを用いた撮像装置におい
て、直流再生を行うクランプ回路り第1図のように撮像
素子の撮像部1の一部4を遮光して、この部分を画像の
基準黒レベルとしく以後この部分をオグテイカル・ブラ
ックと呼ぶ)、この部分からの信号5を第2図に示すよ
うなタイミングのクランプパルス6によってクランプし
、失われた直流分を再生していた。尚、第1図中2はメ
モリ一部、6は水平シフトレジスタである。第6図は従
来のクランプ回路の等何回路を示す図であるOコンデン
サ7によって信号源8からの信号は第4図aのように平
均値をO■とするAC信号となるOこれに対し第4図す
に示すタイミングにスイッチ9をONすれば、その時点
での電圧が電源Eの電圧EVまで引っばられ、結果とし
て第4図すのような基準黒レベルiEVとする画像信号
が得られる0 ところがこのような構成のクランプ回路において、第5
図aのように撮像デバイス出力のオグテイカル・ブラッ
ク期間にキズ等による欠陥が存在した場合、その欠陥は
一般には電圧変動として出力に現われる。これを6のよ
うなパルスでクランプすると、第6図のようにキズの電
圧もEVに引っばられてしまうために、結果として、基
準黒レベルがEVから△■′だけずれてしまい、再生画
像に影響が出てしまう。このため結果的には撮像デバイ
スの歩留まりの低下につながってしまうという問題があ
った。
(Prior Art) Conventionally, in an imaging apparatus using an imaging device such as a COD, a clamp circuit for DC regeneration shields a part 4 of the imaging section 1 of the imaging element from light as shown in FIG. The signal 5 from this part was clamped by a clamp pulse 6 with the timing shown in Figure 2, and the lost DC component was regenerated. . In FIG. 1, 2 is a part of the memory, and 6 is a horizontal shift register. Figure 6 is a diagram showing a conventional clamp circuit.The signal from the signal source 8 becomes an AC signal with an average value of O■ due to the capacitor 7 as shown in Figure 4a. When the switch 9 is turned on at the timing shown in Fig. 4, the voltage at that point is pulled up to the voltage EV of the power supply E, and as a result, an image signal with the reference black level iEV as shown in Fig. 4 is obtained. However, in a clamp circuit with such a configuration, the fifth
If a defect such as a scratch exists during the ogical black period of the output of the imaging device as shown in FIG. a, the defect generally appears in the output as voltage fluctuation. If this is clamped with a pulse like 6, the voltage of the scratch will also be pulled by EV as shown in Figure 6, and as a result, the reference black level will deviate from EV by △■', and the reproduced image will be will be affected. As a result, there is a problem in that the yield of imaging devices is reduced.

(目 的) 本発明はこのような従来の欠点を除去する事を目的とす
るものであり、特に、撮像デバイスのオプティカル・ブ
ラック等のクランプすべき部分にキズが存在した場合、
キズの存在する部分をクランプしないようクランプ手段
を制御することによって、正しい直流再生を行い、歩留
りを向上させる事を目的とするものである。
(Purpose) The purpose of the present invention is to eliminate such conventional drawbacks. In particular, when there are scratches on the part of the imaging device that should be clamped, such as optical black,
The purpose of this is to perform correct DC regeneration and improve yield by controlling the clamping means so as not to clamp the portion where the flaw exists.

(実施例) 以下実施例に基づき本発明を説明する。(Example) The present invention will be explained below based on Examples.

第7図は本発明の撮像装置の第1実施例のブロック図で
ある。
FIG. 7 is a block diagram of a first embodiment of the imaging apparatus of the present invention.

図中100は撮像デバイスであって例えば第1図示のよ
うなフレーム・トランスファー1ccDが用いられるが
、MO8型X−Yアドレスセンサーでも撮像管であって
も良い。
In the figure, reference numeral 100 denotes an imaging device, and for example, a frame transfer 1ccD as shown in the first diagram is used, but it may also be an MO8 type X-Y address sensor or an imaging tube.

10はこのデバイス100の走査等に必要なドライブパ
ルスを供給するドライバー回路、11はドライバー回路
10に対し、クロックパルスヲ供給するクロック回路で
ある。デバイス1[)[)の出力はサンプルホールド回
路12によってデユーティ−を高めた後、本発明に係る
クランプパルス制御回路13に入力され、オプティカル
ブラックの期間に欠陥信号がないか否かを検出し、この
検出出力に応じて次段のクランプ回路20に供給される
クランプパルスを制御する。クランプ回路20に於てペ
デスタルレベルが基準黒レベルに直流再生されプロセス
回路25に於て各也補正を受けてからエンコーダー60
に入力される。
10 is a driver circuit that supplies drive pulses necessary for scanning of this device 100, and 11 is a clock circuit that supplies clock pulses to the driver circuit 10. The output of the device 1 [) [) is inputted into the clamp pulse control circuit 13 according to the present invention after increasing the duty by the sample and hold circuit 12, and detects whether there is a defective signal during the optical black period. The clamp pulse supplied to the next-stage clamp circuit 20 is controlled in accordance with this detection output. In the clamp circuit 20, the pedestal level is DC-regenerated to the reference black level, and after being subjected to various corrections in the process circuit 25, the encoder 60
is input.

一方、サンプルホールド回路12の出力は色信号を分離
する為のサンプルホールド回路14〜16に供給され夫
々異なるタイミングで点順次信号の中から各色信号成分
が抽出される。
On the other hand, the output of the sample and hold circuit 12 is supplied to sample and hold circuits 14 to 16 for separating color signals, and each color signal component is extracted from the dot sequential signal at different timings.

サンダルホールド回路14〜16の出力は夫々回路16
と同じ構成のクランプパルス制御回路17〜19に入力
され、その後クランプ回路21〜26に於て夫々直流再
生される。
The outputs of the sandal hold circuits 14 to 16 are connected to the circuit 16, respectively.
The signals are input to clamp pulse control circuits 17 to 19 having the same configuration as , and then DC-regenerated in clamp circuits 21 to 26, respectively.

クランプ回路21〜26の出力は夫々グロセス回路26
〜28に於て信号処理されホワイトバランス制御回路2
9に於て互いにレベル調整された後エンコーダー60に
入力されNTSG信号等の標準テレビジョン信号に変換
される。
The outputs of the clamp circuits 21 to 26 are connected to gross circuits 26, respectively.
~ 28, the signal is processed and sent to the white balance control circuit 2
After their levels are adjusted with each other in step 9, the signals are input to an encoder 60 and converted into a standard television signal such as an NTSG signal.

第8図は本発明のクランプパルス制御回路13゜17〜
19の!成の一例を示す図で、サンプルホールド回路1
2の出力は欠陥信号検出回路161に入力され、オプテ
ィカルブラック期間に於て所定レベル範囲外の信号が検
出されるとパルス信号が形成される。132はこのパル
ス信号幅を成る程度床げる為のワンショット回路であっ
て、これはオプティカルブラックに於けるキズに対応す
る信号を後述のクランプパルスが拾わないようKする為
のマージンをかせぐものである。このワンショット回路
162の出力と、クロック回路11より供給され、第9
図しに示すようなオプティカルブラック期間ハイレベル
となるクランプ用パルスとがアントゲ−)133に於て
論理的に乗ぜられて第9図61に示すようなりラングパ
ルスを形成する。
Figure 8 shows the clamp pulse control circuit 13゜17~ of the present invention.
19! This is a diagram showing an example of the sample and hold circuit 1.
The output of No. 2 is input to a defect signal detection circuit 161, and when a signal outside a predetermined level range is detected during the optical black period, a pulse signal is generated. Reference numeral 132 is a one-shot circuit for increasing the width of this pulse signal to some extent, and this provides a margin for preventing the clamp pulse described later from picking up a signal corresponding to a scratch in the optical black. It is. The output of this one-shot circuit 162 is supplied from the clock circuit 11, and the ninth
The clamping pulse, which is at a high level during the optical black period as shown in the figure, is logically multiplied by the analog signal 133 to form a rung pulse as shown in FIG. 961.

一万世ンプルホールド回路120出力aはディレィ回路
1ろ4によって遅延され、位相を合わせる事によって第
9図a′のようになり、第9図61に示すようにキズ部
分の前後に多少の巾をもってクランプを停止する事がで
きる。
The output a of the ten-thousand pull-hold circuit 120 is delayed by delay circuits 1 to 4, and by matching the phases, it becomes as shown in Figure 9 a', and as shown in Figure 9 61, there is some width before and after the scratched part. The clamp can be stopped with .

このように構成する事によりオプティカルブラック部分
に於けるキズの影響を全く受ける事なく正しい直流再生
ができるようになる。
With this configuration, correct direct current reproduction can be performed without being affected by scratches in the optical black portion.

次に第10図(2L)はクランプ回路20に係る構成の
他の例を示す図で、第7V4示のサンダルホールド回路
12の出力をコンデンサー201の電位に揃える為のス
イッチングトランジスタST1〜STnを図示の如、く
複数設け、これらのトランジスタ全天々アンド夛−’ト
AN1〜A N nを介してクロック回路11により順
次第10図(blの如<ONさせるよう構成したもので
ある。
Next, FIG. 10 (2L) is a diagram showing another example of the configuration related to the clamp circuit 20, and shows switching transistors ST1 to STn for aligning the output of the sandal hold circuit 12 shown in No. 7V4 to the potential of the capacitor 201. A plurality of transistors are provided as shown in FIG. 10, and these transistors are sequentially turned on by the clock circuit 11 via the transistors AN1 to ANn as shown in FIG.

そしてワンショット回路162の出力がハイレベルの間
だけトランジスタ(r OFFとする事によりクランプ
動作を停止させるものである。このように構成する事に
より工C化に適したものとなる。
The clamping operation is stopped by turning off the transistor (r) only while the output of the one-shot circuit 162 is at a high level.This configuration makes it suitable for engineering.

又、第11図は本発明の他の実施例の構成を示す図でi
io図迄と同じ番号のものは同じ要素を示す。
Further, FIG. 11 is a diagram showing the configuration of another embodiment of the present invention.
The same numbers as up to Figure io indicate the same elements.

62はキズの有無及び場所に応じて第12図に示すよう
なa−dの4種類のパルスを出力する検出回路である。
62 is a detection circuit that outputs four types of pulses a to d as shown in FIG. 12 depending on the presence or absence and location of a scratch.

又、61はモード設定回路であってクロック回路11の
タイミング出力に応じてオグテイ力ルブラック期間に第
12図中モード1〜モード4までの4種類のクランプパ
ルスを出力する。そして検出回路の出力状態a −dに
応じてこのモード設定回路61の出力モードはモード1
〜モー ド4に夫々切換えられるよう構成されて℃・る
Further, 61 is a mode setting circuit which outputs four types of clamp pulses from mode 1 to mode 4 in FIG. 12 during the tail black period in accordance with the timing output of the clock circuit 11. The output mode of this mode setting circuit 61 is set to mode 1 according to the output states a - d of the detection circuit.
~mode 4 respectively.

又、このように構成すれば全体のクラン7”制御の為の
回路が極めて簡単になる。
Furthermore, with this configuration, the circuit for controlling the entire crank 7'' becomes extremely simple.

(効 果) 以上説明した如く、本発明によれば撮像手段のオプティ
カルブランク部分に傷があった場合でもペテスタル部分
を正しくクランプできるので撮像手段の歩留りを向上さ
せる事ができる。
(Effects) As explained above, according to the present invention, even if there is a scratch on the optical blank portion of the imaging means, the petestal portion can be correctly clamped, so that the yield of the imaging means can be improved.

尚、本発明は2次元撮像デバイスだけでなく1次元の嶽
像デバイスに対しても有効な事は騙う迄もない。
It goes without saying that the present invention is effective not only for two-dimensional imaging devices but also for one-dimensional imaging devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は2ブチイカルブラツクを有する撮像デバイスの
一例を示す図、第2図はオプティカルブラックとクラン
プパルスの関係の−elJを示す図、第6図はクランプ
回路の原理図、第4図はクランプのタイミングを示す図
、第5図はオプティカルブランク部に傷が在る場合の信
号の例を示す図、第6図は第5図示の坦合のクランプ誤
差を説明する図、第7図は本発明の撮像装置の構成の一
例を示す図、第8図は本発明のクランプ制御回路の構成
の一例を示す図、第9図は第8図示回路の動作説明図、
第10図(a)は本発明のクランプ回路及びクランプ制
御回路の構成の−fllを示す図、第10図(b)ハ同
図(a)の構成に於けるクランプパルスの説明図、第1
1図は本発明のクランプ回路及びクランプ制御回路の構
成の他の例を示す図、第12図は第11図示構成の動作
を説明する図である0100−・・・・撮像デノくイス 20・・・・・クランプ回路 13・・・・・クランプ制御回路 1ろ1・・・・・検出回路 躬2M 第(5図 462−
Fig. 1 is a diagram showing an example of an imaging device having a 2-butical black, Fig. 2 is a diagram showing -elJ of the relationship between the optical black and the clamp pulse, Fig. 6 is a diagram of the principle of the clamp circuit, and Fig. 4 is a diagram showing the relationship between the optical black and the clamp pulse. Figure 5 is a diagram showing the timing of clamping, Figure 5 is a diagram showing an example of a signal when there is a flaw in the optical blank section, Figure 6 is a diagram explaining the clamping error of alignment shown in Figure 5, Figure 7 is A diagram showing an example of the configuration of the imaging device of the present invention, FIG. 8 is a diagram showing an example of the configuration of the clamp control circuit of the present invention, FIG. 9 is an explanatory diagram of the operation of the circuit shown in the eighth diagram,
10(a) is a diagram showing -fll of the configuration of the clamp circuit and clamp control circuit of the present invention; FIG. 10(b) is an explanatory diagram of the clamp pulse in the configuration of FIG. 10(a);
1 is a diagram showing another example of the configuration of the clamp circuit and clamp control circuit of the present invention, and FIG. 12 is a diagram explaining the operation of the configuration shown in FIG. 11. ... Clamp circuit 13 ... Clamp control circuit 1 Ro 1 ... Detection circuit 2M No. 5 (Fig. 462-

Claims (1)

【特許請求の範囲】[Claims] 光学像を電気信号に変換する撮像手段と、該撮像手段の
出力の所定の部分を所定電位にクランプするクランプ手
段と、撮像手段の前記部分に於ける信号の欠陥を検出す
る検出手段と、該検出手段の出力に応じて前記クランプ
手段のクランプ動作を制御するクランプ制御手段とを有
する撮像装置。
an imaging means for converting an optical image into an electrical signal; a clamping means for clamping a predetermined portion of the output of the imaging means to a predetermined potential; a detection means for detecting a defect in the signal in the portion of the imaging means; An imaging device comprising: a clamp control means for controlling a clamping operation of the clamping means according to an output of the detection means.
JP58037727A 1983-03-08 1983-03-08 Image pickup device Pending JPS59163981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58037727A JPS59163981A (en) 1983-03-08 1983-03-08 Image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58037727A JPS59163981A (en) 1983-03-08 1983-03-08 Image pickup device

Publications (1)

Publication Number Publication Date
JPS59163981A true JPS59163981A (en) 1984-09-17

Family

ID=12505525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58037727A Pending JPS59163981A (en) 1983-03-08 1983-03-08 Image pickup device

Country Status (1)

Country Link
JP (1) JPS59163981A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177660A (en) * 1987-01-19 1988-07-21 Canon Inc Color image reader
JPH0620321U (en) * 1992-05-25 1994-03-15 車体工業株式会社 Container supply mechanism with tiltable container

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52132723A (en) * 1976-04-30 1977-11-07 Sony Corp Solid state pick up unit
JPS57208770A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Dc level automatic compensating circuit for analog signal repetitively including reference level signal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52132723A (en) * 1976-04-30 1977-11-07 Sony Corp Solid state pick up unit
JPS57208770A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Dc level automatic compensating circuit for analog signal repetitively including reference level signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177660A (en) * 1987-01-19 1988-07-21 Canon Inc Color image reader
JPH0620321U (en) * 1992-05-25 1994-03-15 車体工業株式会社 Container supply mechanism with tiltable container

Similar Documents

Publication Publication Date Title
KR100421330B1 (en) The defect detection device of the solid-
US4734774A (en) CCD imager video output defect compensation
JPS59163981A (en) Image pickup device
JPH09179532A (en) Driving device for matrix type display panel
JP2808814B2 (en) Defective pixel position detection device
EP0705028B1 (en) Method of driving solid-state image pickup apparatus
JPH0727728Y2 (en) Crystal defect compensation circuit
KR910003674Y1 (en) Auto-centering circuit
JPS59791A (en) Method and apparatus for pattern recognition
JP3387165B2 (en) Clamp potential correction circuit
JPH09149320A (en) Driving method in solid-state image pickup device
JP2876553B2 (en) Photoelectric conversion device and image reading device
JPS63232768A (en) Image pickup device
JPH05299987A (en) Automatic identification level controller
JPS6033783A (en) Image pickup device
JPH11346333A (en) Solid image pickup device
JP2965350B2 (en) Error correction device for image sensor
JPH0251981A (en) Image pickup device
JPH066643A (en) Defect detection method for solid-state image pickup element
JPH0583645A (en) Output signal processing circuit for charge coupled element
JPS6035881A (en) Clamping circuit of feedback
JPS63232765A (en) Image pickup device
JP3705326B2 (en) Defective pixel correction apparatus and method
JPS585085A (en) Dark current correcting circuit of solid-state image pickup device
JPH0324892A (en) Image pickup device