JPS59161718A - Control system for common bus jurisdiction - Google Patents

Abstract

PURPOSE:To perform optimum priority assignment selectively by providing a control procedure storage means which is stored with plural control procedures for deterining the priority of use among plural main buses and a selecting means which selects one of the stored conrol procedures. CONSTITUTION:An area specifying circuit 12 sends out an area selection signal (0,0), (0,1), (1,0), or (1,1) to an input terminal (A1,A0) of a priority deciding circuit 11 to specify one of four areas. Request signals RQ0-RQ3 for common bus jurisdiction are led to input terminals A2-A5, and the circuit 11 outputs permission signals GT0-GT3 from output terminals 00-03 on the basis of the decision result of priority. Those signals are led to a priority sotrage circuit 13, which supplies signals SA6-SA9 to input terminals A6-A9 selectively according to the signal which is outputted at the last among the signals GT0-GT3, thus performing priority switching in cyclic priority assignment.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a common path dominance control system.

[Prior art]

In a system (hereinafter referred to as a multi-mask system) in which multiple masks (path masks) having a path control function are connected to one common 7 bus, common path control requests are issued simultaneously from multiple bus masks. If so, it is necessary to determine its priority.

FIG. 1 shows an example of the configuration of a multi-mask system including four lotus masks (4Rh), where kA to 18 are bus masks, and each of them is a common path dominance request signal RQO.
~RQ3 is supplied to the path controller 2. The bus controller 2 responds to those signals RQO to R・Q3,
The permission signals GTO to GT3 are sent to the path master IA, respectively.
-10 as appropriate and guess the priority by 1 egg.

Conventionally, there are two examples as shown below as typical methods of assigning the 1111th position of the role.

(1) Fixed priority assignment method (2) Cyclic priority assignment method First, the fixed priority assignment method in section (1) is used when there are differences in the frequency and importance of requests for dominance for each path mask.
Priorities are uniquely set for Hess masters A to ID in advance, and according to the priorities, the highest priority among the multiple path masters outputting the control right request signal is given control of the common path. This is a control method that gives

FIG. 2 shows a block diagram of a circuit for processing common path dominance request signals RQO-RQ3 by fixed priority assignment. Here, 3 is a priority determination circuit, which determines the supplied dominance request signal RQi according to a preset priority 5, and selects a path mask that outputs the signal RQih with the highest priority. A permission signal GTih is supplied to the terminal. For example, for signals RQO to RQ3, the priority is RQO)RQI)RQ2)RQ3 (
1), if path master B and IC request control of the common path and output signals RQI and RQ2, respectively, the priority determination circuit 3 determines the priority order. In response to high signal RQI,
The signal GTI is supplied to the master IH to 7.

This method allows for easy circuit configuration, and is especially suitable for bus masters 1. It is preferable that there are differences in the frequency and importance of requests for control over A-10, and that their priorities are always constant, since this provides a high processing speed.

However, in this method, if there is no difference in the frequency or importance of dominance requests and all hasmasks must be equal, some path masters will have a short wait time before being able to use the common bus, while others will This path mask has the problem that the waiting time is long, and furthermore, when it is necessary to change the priority order by type, there is a problem that it cannot cope with the change.

On the other hand, the 1u priority cyclic allocation method in item (2) is a control method in which the Hasmask that has received a request for control is sequentially assigned the lowest priority, and the priorities are sequentially advanced. This method is suitable for use when there is no difference in the frequency or importance of dominance requests among path masters, and the respective lotus masks are equal.

Figure 3 shows 41-5 of the circuit related to the priority cyclic assignment method.
An example is shown. Here, 4 is an iQ priority order determination circuit, and 5 is a priority order storage circuit, and signals GTO to GT3 outputted from the priority order determination circuit 4 are guided to the priority order storage circuit 5. When the priority determination circuit 4 selects a certain path master and outputs a permission signal, the priority storage circuit 5 stores the priority of the path mask as the lowest in response to that signal.
Data corresponding to the stored contents is supplied to the priority order determination circuit 4 to switch the priority order.

An example of the operation of the circuit shown in FIG. 3 will be described using FIGS. 4(A) to 4(D). First, as an initial state, path masks IA to X
If the priority of I) is set as in equation (1), priority 1
111! The i-order storage circuit 5 stores the priority order as shown in FIG. 4(A), and supplies stem data to the priority order determination circuit 4. In this state, when only the path mask IC outputs the request signal RQ2, the priority determination circuit 4 outputs the permission signal GT,2, and the /<smaster IC gains control of the common path. At this point, the contents of the priority storage circuit 5 are rewritten as shown in FIG. 4(B), and the bus master IC becomes the lowest priority. Next, when the path master IA gains control, the priority becomes the lowest, as shown in FIG. 4(C).

Next, assume that bus masters IA and 1B output request signals RQO and RQI, respectively. In this case, the priority order is in the state shown in FIG. 4(C), so the priority order is higher for path mask IB than for path master IA. The priority order is determined using the data output from the storage circuit 5, and the permission signal GTI is output to the path mask IB. At the same time, the priority storage circuit 5
stores that the priority of path mask IB has become the lowest, as shown in FIG. 4(D).

In this way, the priority cyclic allocation method is suitable when all the path masks are equal.
, (0,1), (1,0), or (1,1) so that one of the four areas can be specified.

Here, the signals supplied to the input terminals (AI, AO) are (
0, 0), the area (area 0) stores the control force formula based on the fixed priority assignment; shall be specified.

Common bus mastership request signal RQO is input to input terminals A2 to A5.
~RQ3, and the priority determination circuit 11 outputs the permission signal GT from the output terminals 00 to 03 based on the priority determination result.
Output O~GT3. These signals GTO to GT3 are also guided to the priority order storage circuit 13.
Hikonely supplies signals SAe to SA9 to input terminals A6 to A8 according to any one of the last output signals GTO to GT3, and switches the priority order when performing priority cyclic assignment.

Table 1 shows the input/output relationship of the priority determination circuit 11 when the common bus mastership control method with fixed priority assignment is selected. This shows that.

(b) Finally, the permission signal GT3 was output.

(b) Signals RQ2 and RQ3 were manually operated at the same time.

(c) When comparing signals RQ2 and RQ3, in the control system based on priority [υ fixed assignment], signal RQ2 always has a higher priority, and the priority determination circuit 11
Outputs 2.

Table 2 shows the input/output relationship of the priority determination circuit 11 when the common bus mastership control method based on cyclic priority assignment is selected.
).

(d) Finally, the permission signal GT2 is output, and the signal RQ2
has the lowest priority.

(e) Signals RQO and RQI are simultaneously disabled.

(f) Under conditions (d) and (e), signal RQ
! The signal RQO has a higher priority, and the determination circuit 4 outputs the signal GTO.

Table 1 Table 2 Second Embodiment FIG. 6(A) shows a second example of the configuration of the priority processing circuit according to the present invention. In this example, the storage numbers for various priority assignment methods are stored in a large capacity R.
A CIM 21 is used and a high speed random access memory (RAM) 22 is used to determine the priority order.

That is, as shown in FIG. 6 (El), the ROM2
Among the areas expanded in 1, the data of the area storing the control method to be adopted is transferred to the RAM 22, and the RAM 22 determines the priority order according to the control method.

When transferring data, first R
This is done by specifying a region within OM 21 and then activating counter 23. The address signal ADR output from the counter 23 is guided to the ROM 21, and is also supplied to the multiplexer (MPX) 24 through L-(RAM22).
The address is input to the ROM 21 and RAM 22.

When the bus mastership request signal RQi is supplied, the RAM '
22 uses the signal RQi supplied via the MPX 24 and the output 4i of the latch circuit 25 to output a permission signal GTih for the request signal RQih having the highest priority. The latch circuit 25 stores the data of the permission signal to the bus master that was last permitted to control the bus, and the RAM 22 waits for the next bus control request signal RQi to be input.

Third Embodiment FIG. 7 shows a third example of the configuration of a priority processing circuit according to the common bus dominance control system of the present invention. In the second embodiment, if a 7-bit control request occurs during data transfer from the ROM 21 to the RAM 22, it is not possible to determine the priority and respond to the request. Therefore, in this example, in addition to the configuration shown in FIG. 6(A), R
RAM 32 for storing data transferred from OM 21;
A RAM 22 (1) and an MPX 35 (RAM 3217) which receives the output signal and outputs a permission signal GT'ih are added.

In other words, in this example, priority order judgment circuits are provided in parallel, so even if one judgment circuit is receiving transfer data, such processing can be interrupted by using the other judgment circuit for priority processing. It can be done without.

Fourth Embodiment FIG. 8 shows a fourth example of the configuration of the priority processing circuit related to the common path dominance control system of the present invention.
is replaced with RAM41. That is, R.O.
Compared to the processing circuit shown in FIG. 7 in which data is fixed in M21, the data can be freely rewritten.

Fifth Embodiment FIG. 9 shows a fifth example of a priority processing circuit according to the common bus dominance control system of the present invention. In this example, the ROM shown in FIG.
21 and counter 23, and a RAM 41 shown in FIG.
The data related to the desired priority assignment is supplied to the RAM 228 and RAM 32. This allows for more flexible processing.

〔effect〕

As explained above, according to the present invention, a means for storing a plurality of different priority processing procedures is provided, so that the upper fixed priority assignment method, the priority cyclic assignment method, and the priority Free priority assignment methods such as rank assignment can be stored, and therefore,
Since the optimal processing procedure can be appropriately selected depending on the degree of importance of the bus masks, it is possible to perform common path dominance control with high flexibility.

Note that the number of bus masters in the present invention is not limited to four, and the present invention can of course be applied to all multi-mask systems equipped with two or more bus masters, and the greater the number, the more effective the present invention is. . moreover,
RAM 41 described in the fourth embodiment and the fifth embodiment
can also be composed of a group of rewritable register files.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a general multi-mask system, and FIG. 2 is an example of the configuration of a circuit that performs common bus dominance control using a conventional fixed priority assignment method.
FIG. 3 is a block diagram showing an example of the configuration of a circuit that performs common path dominance control using the conventional priority cyclic assignment method, and FIGS. 4 (A) to CD) explain an example of the process. 5 (A) and (B)
) is a block diagram showing a first example of the configuration of the priority processing circuit according to the present invention, and FIGS. 6(A) and (B) are blocks showing a second example of the configuration of the usage priority processing circuit according to the present invention. figure,
7 to 9 are block diagrams showing third to fifth examples of the priority processing circuit according to the present invention, respectively. IA, 1B, IC, 10...Bath mask, 2...
Bus controller, 3.4.11...Priority determination circuit, 5.13...
Priority storage circuit, 12... Area designation circuit, 21... Read only memory (ROM), 22.32
．． 41... Random access memory (RAM), 24.34, 35.50...-y Multiplexer (M
PX), RQO, RQI, RQ2. RQ3...Dominance request signal, GT, 0. GTI, GT2. GT3...Permission signal. Patent applicant: Fuji Electric Manufacturing Co., Ltd.
Applicant: Fuji Facom Control Co., Ltd.-10

Claims (1)

[Claims] a common/hess, a mask of a number of screws connected to the common path to claim control over the common path, and selectively using the common hess for each of the plurality of masks. a path control means for permitting the use of the plurality of masks; selection means for selecting any one of a plurality of control procedures, and when two or more of the plurality of masks simultaneously request the use, the selection means selects one of the plurality of control procedures. A common path dominance control system, characterized in that, in accordance with the control procedure, a 1e first order of use of the two or more masks is determined.