JPS59160346U

JPS59160346U - Image processing terminal device with auxiliary frame buffer memory

Info

Publication number: JPS59160346U
Application number: JP5420283U
Authority: JP
Inventors: 内藤　昭; 今村　宗立; 鈴木　壮一
Original assignee: 三菱電機株式会社
Priority date: 1983-04-12
Filing date: 1983-04-12
Publication date: 1984-10-27

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の画像処理端末装置を示すブロック図、第
２図はこの考案の補助フレームバッファメモリを有する
画像処理端末装置の一実施例の構成を示すブロック図で
ある。ｌａ〜ｌｃ・・・・・・インタフェースバス、２．　３
゜１０・・・・・・インタフェイス回路、４−−−−−
−ＣＰＵ、　５、・・・・・・セグメントバッファメモ
リ、６・・・・・・線分発生器、７・・・・・・フレー
ムバッファメモリ、８・・・・・・ビデオ回路、９・・
・・、’、ＣＲＴ、１１・・・・・・補助フレームバッ
ファメモリ、１２・・・・・・切換用回路。なお、図中
同一符号は同一または相当部分を示す。FIG. 1 is a block diagram showing a conventional image processing terminal device, and FIG. 2 is a block diagram showing the configuration of an embodiment of the image processing terminal device having an auxiliary frame buffer memory according to the present invention. la to lc...interface bus, 2. 3
゜10...Interface circuit, 4------
- CPU, 5... Segment buffer memory, 6... Line segment generator, 7... Frame buffer memory, 8... Video circuit, 9...・
..., ', CRT, 11... Auxiliary frame buffer memory, 12... Switching circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A central processing unit within the image processing terminal device that analyzes data transferred from the host system, organizes and stores it in a segment buffer memory, and performs calculations necessary for displaying the contents of this segment buffer memory on one stage of the indicator; a line segment generator that converts the contents of the segment buffer memory into line segments necessary for display on the display means; a frame buffer memory that holds the output of this line segment generator as data for display on the display means; A video circuit that converts frame buffer memory into data for display on the display means; an auxiliary frame buffer memory that takes in data from the host system through an interface circuit when displaying data directly on the display means at high speed; An image processing terminal device having an auxiliary frame buffer memory comprising a switching circuit for determining whether or not to transfer the contents of the frame buffer memory to the video circuit.