JPH103446A - Integrated circuit for connection of graphic accelerator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the monopolization of a PCI(peripheral component interconnect) bus and also the generation of conversion loss of data by switching mutually the data form between a PCI bus form and a VL(video electronic standard association local) bus form. SOLUTION: The memory write data are inputted to a PCI control part 1 from a PCI bus 20 and temporarily sent to a FIFO part 2 after they are judged as the due data. Thus, the bus 20 is opened. Then the memory write data are sent to a data form conversion part 4 via the bus 20 and converted into a VL bus form from a PCI bus form. The data of the PCI bus form are sent to a graphic accelerator 30. The I/O write data which are judged at the part 1 are sent to an address conversion part 3. Then the address conversion is carried out for the data if needed, and the converted data are sent to the part 4. The part 4 converts the data into a VL bus form from a PCI bus form and sends the converted data to the accelerator 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic accelerator connection integrated circuit for connecting an information processing device connected to a PCI bus and a VL bus interface graphic accelerator used for the information processing device.

[0002]

2. Description of the Related Art A high-speed PCI bus (Peripheral
Component Interconnect bus: Address and data use the same line in time division. There is no dedicated signal line indicating the bus use state, and the lower bits of the address are substituted. )
Information processing device connected to the VL bus (Video Electronic Standard Associ
-ation (VESA) Local bus: Use separate line for address and data. There is a dedicated signal line that indicates the use state of the bus. A conventional means for connecting a graphic accelerator of an interface (an integrated circuit chip equipped with a circuit for displaying information such as characters and images on a screen of a display device) is a graphic accelerator of a VL bus interface. Integrated circuit (I
C), a general-purpose PCI bus-VL bus connection integrated circuit (PCI-VL bus bridge IC) is used. When the I / O address of the graphic accelerator is not in the memory map system (a system in which a control instruction is issued using a memory address on the memory map), the I / O address of the information processing device and the graphic An integrated circuit (IC) for performing I / O address conversion after performing mutual conversion between PCI bus format data and VL bus format data so that the I / O address of the accelerator does not overlap. doing.

[0003]

As described above, the means for connecting the conventional information processing apparatus with the graphic accelerator of the VL bus interface is a general-purpose PC.
Because I-VL bus bridge IC is used, PC
When the target graphic accelerator is accessed from the I bus, the PCI-VL bus
The bridge IC starts a cycle of the VL bus,
Transfer data while confirming the response from the graphic accelerator. At this time, since there is no FIFO circuit, the PCI-VL bus / bridge IC keeps occupying the PCI bus, so that there is a problem that a conversion loss occurs. Also, when the graphic accelerator is replaced to enhance the contents of the screen display, an IC for preventing the I / O address of the replaced graphic accelerator from overlapping with the I / O address of another integrated circuit (IC). Therefore, there is also a problem that a conversion loss occurs here. Furthermore,
Because a large number of ICs must be used,
There is also a disadvantage that the price increases and the mounting area increases.

[0004]

The integrated circuit for connecting a graphic accelerator according to the present invention is an integrated circuit for connecting a graphic accelerator for connecting an information processing device connected to a PCI bus and a graphic accelerator of a VL bus interface used for the same. A data format conversion function for converting a data format between data in a PCI bus format and data in a VL bus format, and an I / O address of the graphic accelerator and other I / O addresses.
It has an address conversion function of converting addresses so that the I / O address of C does not overlap, and a temporary storage function of temporarily storing memory write data.

That is, the integrated circuit for connecting a graphic accelerator according to the present invention is a P-type IC for controlling connection to a PCI bus connecting an information processing device connected to the PCI bus.
A CI control unit, a FIFO unit for temporarily storing memory write data from the PCI control unit, and an I / O address of the graphic accelerator and an I / O address of another IC for the I / O write data from the PCI control unit. An address conversion unit that performs address conversion so that the O address does not overlap with the address;
A data format conversion unit is connected to the graphic accelerator of the VL bus interface and converts the data in the PCI bus format and the data in the VL bus format into and out of each other.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, an integrated circuit (PCI bus bridge IC) 10 for connecting a graphic accelerator comprises:
A PC which is connected between a PCI bus 20 connecting an information processing device and a graphic accelerator 30 of a VL bus interface, and controls connection with the PCI bus 20;
An I control unit 1, a first-in first-out circuit (FIFO unit) 2 for temporarily storing memory write data from a PCI bus 20, an I / O address of an information processing device, an I / O address of a graphic accelerator 30, And a data format conversion unit 4 for converting addresses in the PCI bus format and data in the VL bus format between each other so that addresses do not overlap.

Next, the operation of the PCI bus bridge IC configured as described above will be described.

In the case of memory write data (32-bit data which is written in a memory in the graphic accelerator 30 and then processed and sent to a display device to be displayed on a screen), the data is , PCI
The PCI controller 20 enters the PCI controller 1 from the bus 20, where the data is determined to be memory write data and is sent to the FIFO unit 2. At the same time, the PCI bus 20 is notified that the data has been fetched. As a result, the PCI bus 20 shifts to the next operation, and the graphic accelerator 30
It does not hold the CI bus 20. This operation stores the data in FI
Since the operation is only to be taken into the FO unit 2, the PCI bus 2
0, and therefore, the PCI
The transfer capability of the bus 20 is not impaired. The data taken into the FIFO unit 2 is sent to the data format conversion unit 4 from there,
Then, the data format is converted from the PCI bus format to the VL bus format and transferred to the graphic accelerator 30.

In the case of I / O write data (16-bit data for operating the graphic accelerator 30), the data enters the PCI control unit 1 from the PCI bus 20, where the I / O write data And sent to the address conversion unit 3. The I / O write data sent to the address conversion unit 3 is determined whether or not address conversion is required. If it is determined that address conversion is required, the I / O write data is subjected to a conversion operation. Is sent to the data format converter 4. When it is determined that the address conversion is unnecessary, the conversion operation is not performed, and is sent to the data format conversion unit 4 as it is. The data format converter 4 converts the format of the transmitted data from the PCI bus format to the VL bus format and transfers the data to the graphic accelerator 30.

In the case of read data (data read from the graphic accelerator 30 to check the display state of the display device), in the case of memory read data,
In the case of / O read data, both operate along the same path. That is, the read data enters the data format converter 4 from the graphic accelerator 30, where the data format is converted from the VL bus format to the PCI bus format, and then sent to the PCI controller 1.
The data is transferred to the I bus 20.

[0013]

As described above, the integrated circuit for connecting a graphic accelerator according to the present invention includes a FIFO unit for storing memory write data therein, an I / O address of the graphic accelerator, and an IC of another IC. I
Since an address conversion unit for converting an address so that an / O address does not overlap and a data format conversion unit for mutually converting data in the PCI bus format and data in the VL bus format are provided, the PCI bus A large amount of sent memory write data can be immediately received regardless of the operation state of the graphic accelerator, and
There is an effect that monopoly of the I bus and occurrence of data conversion loss can be suppressed. Further, there is an effect that the overlap between the I / O address of the graphic accelerator and the I / O address of another IC can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 PCI control unit 2 First in first out circuit (FIFO
3) Address conversion unit 4 Data format conversion unit 10 Graphic accelerator connection integrated circuit (PCI bus bridge IC) 20 PCI bus 30 Graphic accelerator

Claims (2)

[Claims] 1. A graphic accelerator connection integrated circuit for connecting an information processing device connected to a PCI bus and a graphic accelerator of a VL bus interface used for the information processing device, wherein the data format is PCI bus format data and a VL bus. A data format conversion function for mutually converting between data of the same format, an address conversion function for converting addresses so that an I / O address of the graphic accelerator does not overlap with an I / O address of another IC, and a memory. An integrated circuit for PCI bus connection, having a temporary storage function of temporarily storing write data. 2. A PCI control unit for controlling connection with a PCI bus connecting an information processing device connected to the PCI bus, a FIFO unit for temporarily storing memory write data from the PCI control unit, I from the PCI control unit
/ O Write data to I / O of graphic accelerator
An address conversion unit for converting addresses so that the O address does not overlap with the I / O addresses of other ICs, and a P / L converter connected to a graphic accelerator of the VL bus interface.
An integrated circuit for PCI bus connection, comprising: a data format conversion / conversion unit for mutually converting between data in a CI bus format and data in a VL bus format.