JPS59160310U - control circuit - Google Patents
control circuitInfo
- Publication number
- JPS59160310U JPS59160310U JP5633783U JP5633783U JPS59160310U JP S59160310 U JPS59160310 U JP S59160310U JP 5633783 U JP5633783 U JP 5633783U JP 5633783 U JP5633783 U JP 5633783U JP S59160310 U JPS59160310 U JP S59160310U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- output
- control circuit
- detector
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Control Of Temperature (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の制御回路の回路図、第２図は本考案実施
例の制御回路の回路図である。
４・・・・・・直流電源、５・・・・・・検知素子、６
．６’。
６″・・・・・・分圧抵抗、７・・・・・・抵抗、８・
・・・・・トランジスタ、９・・・・・・検出器、１０
・・・・・・論理手段、１０′・・・・・・バッファト
ランジスタ、１０“・・・・・・ドライバ。FIG. 1 is a circuit diagram of a conventional control circuit, and FIG. 2 is a circuit diagram of a control circuit according to an embodiment of the present invention. 4...DC power supply, 5...Detection element, 6
．． 6'. 6″・・・Divider resistance, 7・・・Resistance, 8・
...Transistor, 9...Detector, 10
...Logic means, 10'...Buffer transistor, 10''...Driver.
Claims (3)
、該抵抗をペースエミッタ間に接続したトランジスタと
、前記検知素子の抵抗値の変化を検出する検出器と、前
記トランジスタの出力と検出器の出力とで制御信号を構
成する論理手段とを具備した事を特徴とする制御回路。(1) A sensing element and a resistor connected in series to a DC power source, a transistor connecting the resistor between pace emitters, a detector that detects a change in the resistance value of the sensing element, and an output of the transistor and detection. 1. A control circuit comprising logic means for configuring a control signal with the output of the device.
器の出力信号を制御信号とし、トランジスタがＯＦＦの
時検出器の出力にかかわらず特定の制・ 両信号を出力
するものである事を特徴とする前記実用新案登録請求の
範囲第１項記載の制御口−九 路。(2) The logic means is characterized in that when the transistor is ON, the output signal of the detector is used as the control signal, and when the transistor is OFF, it outputs a specific control signal regardless of the output of the detector. The control port-nine route according to claim 1 of the utility model registration claim.
するものである事を特徴とする前記実用新案登録請求の
範囲第１項記載の制御回路。(3) The control circuit according to claim 1, wherein the detection element has a resistance value that changes depending on temperature changes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633783U JPS59160310U (en) | 1983-04-14 | 1983-04-14 | control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5633783U JPS59160310U (en) | 1983-04-14 | 1983-04-14 | control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59160310U true JPS59160310U (en) | 1984-10-27 |
Family
ID=30186660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5633783U Pending JPS59160310U (en) | 1983-04-14 | 1983-04-14 | control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59160310U (en) |
-
1983
- 1983-04-14 JP JP5633783U patent/JPS59160310U/en active Pending
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