JPS59159549A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS59159549A
JPS59159549A JP58033064A JP3306483A JPS59159549A JP S59159549 A JPS59159549 A JP S59159549A JP 58033064 A JP58033064 A JP 58033064A JP 3306483 A JP3306483 A JP 3306483A JP S59159549 A JPS59159549 A JP S59159549A
Authority
JP
Japan
Prior art keywords
lead frame
pellet
wire
wires
wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58033064A
Other languages
Japanese (ja)
Inventor
Takeo Masuda
増田　猛雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58033064A priority Critical patent/JPS59159549A/en
Publication of JPS59159549A publication Critical patent/JPS59159549A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To prevent the short circuit due to wire sag and enable to utilize the size of a pellet which can be mounted by providing a wall at an island edge in a lead frame whereon an integrated circuit pellet is mounted. CONSTITUTION:In the lead frame, the wall 20 of an insulation substance provided with radial grooves 21 in the surface is pasted at the island edge 13, thus forming the support for the wires between leads 15 and the pellet 15. This wall 20 serves as the support for the wires 22 and thus prevents the sag of said wires 22. Besides, the radial grooves 21 prevent the slide of the wire 22 at the time of sealing resin. The size of the pellet which can be mounted on the lead frame of the same standard becomes in a wide range owing to the prevention of the sag of these wires.

Description

【発明の詳細な説明】 本発明は、集積回路（以後ＩＣ）ベレット全搭載するリ
ードフレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame on which an integrated circuit (hereinafter referred to as IC) pellet is fully mounted.

ＩＣの製造ＶＣ於いて、近年の技術革新は急激であり５
同時に品種展開、用途の多様化は極めて急激である。こ
れに関連して、ＩＣベレットヲ搭載するり−ド７レーム
の種類も増し、そのパターン設計工数及び期間が増大し
ている。この中には単にベレットサイズの変更によるリ
ードフレームの設計しなおしが増えている。In IC manufacturing VC, technological innovation has been rapid in recent years5.
At the same time, the development of varieties and the diversification of uses are extremely rapid. In connection with this, the number of types of cards mounted with IC pellets has increased, and the number of man-hours and period for designing patterns has increased. This includes an increasing number of lead frame redesigns simply due to changes in pellet size.

第１図が１４ビンの場合のリードフレーム図で、１１は
リード、１２はアイランド、工３はアイランド縁全示す
・ 第２図がＩＣＴ％１５はベレット、１６は金または銀線
（以後ワイヤ）％　１７は樹脂全示す。Figure 1 is a lead frame diagram for 14 bins, 11 is the lead, 12 is the island, and work 3 shows the entire edge of the island. Figure 2 is ICT% 15 is the bullet, 16 is the gold or silver wire (hereinafter referred to as wire) % 17 indicates total resin.

従来のＩＣの製造工程お概要は、アイランド中央ＶＣペ
レット全の９句でし、ペレ、ットの出力ビンとリード間
全ワイヤで接続しこれを樹脂で固める。The outline of the conventional IC manufacturing process is to make a total of nine VC pellets in the center of the island, connect the output bins of the pellets and the leads with all wires, and harden them with resin.

ペレット’ｌリードフレームに搭載する場合、アイラン
ド縁、ベレット縁間隔は、Ｑ、２ｍｍ〜Ｑ、４ｍｍ程度
であること、ワイヤの長さは２ｍｍ程度であること、リ
ード縁、アイランド縁は２ｍｍ〜３ｍｒ４度であること
、などの制限がある。When mounting the pellet on a lead frame, the spacing between the island edge and the pellet edge should be about Q, 2mm to Q, 4mm, the wire length should be about 2mm, and the lead edge and island edge should be about 2mm to 3mmr4. There are restrictions such as being at a certain degree.

第３図はこれら制限全違反して、ワイヤが長丁ぎた場合
のリードフレームの断面図である。１８はたるんだワイ
ヤ金示す。FIG. 3 is a sectional view of a lead frame in which all of these restrictions are violated and the wire is too long. 18 indicates slack wire metal.

また、ベレットサイズが変更となった場合、同一規格の
リードフレームでは許容できな′くなることがアリ、ア
イランドサイズおよびリード、アイランド間隔を変更し
たリードフレームを作成しなおさなければならない欠点
があった。Additionally, if the pellet size is changed, lead frames of the same standard may no longer be acceptable, and a lead frame with different island sizes, leads, and island spacing must be recreated. .

本発明の目的は、ワイヤのたるみによるン、−１−ｆ防
ぐと同時に、搭載でき６ベレツトザイズが広範囲に使用
できることである。An object of the present invention is to prevent the loss of -1-f due to wire slack, and at the same time, to enable a 6-barret size to be mounted and used over a wide range of areas.

次に実施例で説明′ｖ″′る７ｏ第４図一本発明実施］
タリのリードフレームである。２０は絶縁環、２１は溝
ゲ示す。第５図ｒｉ　’）−ドクし／−ムの１雪面図で
ある。２２は塀に支えらノ’Ｌ７こワイヤを示１゛。Next, it will be explained in the examples.
This is a Tali lead frame. 20 is an insulating ring, and 21 is a groove. Figure 5 is a snow map of ri')-Dokushi/-mu. 22 shows the wire L7 supported on the wall.

表面に放射状の溝紫設けた絶縁物質の塀紮アイランド縁
ＶＣのり付けし、リード、ベレット間ワイヤの支え全作
る。この塀がワイヤの支えとなりワイヤのたるみ全防止
する効果がある。ま／こ放射状の溝は、樹脂名二封入す
る際にワイヤがすれること全防止する。これらワイヤの
たるみが防止できることにより、同一規格のリードフし
・−ムＶＣ搭ｆｉｇできるベレ、　ｌ−の大きさが広範
囲ＶＣなることで、ある。Glue the island edge VC to the insulating material fence with radial grooves on the surface, and create a complete support for the wire between the lead and pellet. This wall supports the wire and has the effect of completely preventing the wire from sagging. The radial grooves completely prevent the wire from slipping during resin filling. By preventing these wires from sagging, the size of the lead frame VC of the same standard can be mounted over a wide range of VCs.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図け、１４ビンの」揚台のリードフレーム図、第２
図は、ＩＣの外観、葡示す図、第３図ｔよ、ペレットに
適合し方いり一部フレームの断面全示す図第４図（址、
本発明のリードフＬ／−ム外観葡示−ｊ゛図、第５図は
、本発明のリードフレーム断面金示す図、である。 なおは）ＶＣおいで、 １１　・　リード％　１２　・・・・アイランド、１３
・”アイランド縁、１５−　Ｉ　Ｃペレット、１６ワイ
ーヤ、」７　・　・オ封月旨、１８　・　・／ヒるんだ
ワイヤ、２０・・・絶縁環、２１・　・溝、２２　・・
塀に支えられたワイヤ、である。 ６ 第２［ｇｌ ８ 第３１図 り４図 第Ｓ［１Figure 1, lead frame diagram of a 14-bin lifting platform, Figure 2.
The figures show the external appearance of the IC, Fig. 3 shows how it fits into the pellet, and Fig. 4 shows the entire cross section of a part of the frame that fits the pellet.
FIG. 5 is a cross-sectional view of the lead frame of the present invention. Naoha) Come on VC, 11 ・ Lead% 12 ... Island, 13
・"Island edge, 15-IC pellet, 16 wire," 7 ・ ・Osealed moon effect, 18 ・ ・・/hanging wire, 20 ・・insulation ring, 21 ・・groove, 22 ・・
It's a wire supported by a fence. 6 2nd [gl 8 31st figure 4 S [1

Claims (1)

【特許請求の範囲】[Claims] アイランド縁ｖｃ塀を有することを特徴とするリードフ
レーム。A lead frame characterized by having an island edge VC wall.
JP58033064A 1983-03-01 1983-03-01 Lead frame Pending JPS59159549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58033064A JPS59159549A (en) 1983-03-01 1983-03-01 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58033064A JPS59159549A (en) 1983-03-01 1983-03-01 Lead frame

Publications (1)

Publication Number Publication Date
JPS59159549A true JPS59159549A (en) 1984-09-10

Family

ID=12376301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58033064A Pending JPS59159549A (en) 1983-03-01 1983-03-01 Lead frame

Country Status (1)

Country Link
JP (1) JPS59159549A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376756A (en) * 1991-12-20 1994-12-27 Vlsi Technology, Inc. Wire support and guide
US5408127A (en) * 1994-03-21 1995-04-18 National Semiconductor Corporation Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376756A (en) * 1991-12-20 1994-12-27 Vlsi Technology, Inc. Wire support and guide
US5430250A (en) * 1991-12-20 1995-07-04 Vlsi Technology, Inc. Wire support and guide
US5408127A (en) * 1994-03-21 1995-04-18 National Semiconductor Corporation Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components

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