JPS59158552A - Semiconductor photodetector - Google Patents

Abstract

PURPOSE:To inhibit the variation of potential of a shielding gate region effectively, and to improve the controllability of output characteristics by forming a means inhibiting the storage of carriers generated by incident rays to the shielding gate region. CONSTITUTION:Source electrodes 22 are connected and formed among adjacent cells in exposed sections in source regions 16. Transparent control gate electrodes 24 are formed to the exposed sections of control gate regions 14 through insulating layers 26. The insulating layers 26 consist of films such as oxide films, and are shaped extended onto the source electrodes 22. The control gate electrodes 24 are formed along the upper sections of the insulating layers 26. Informations stored in either cells can be read because the direction of connection of the control gate electrodes 24 and the direction of connection of the source electrodes 22 cross. Shielding gate electrodes 18E can apply fixed voltage to the whole shielding gate regions 18.

Description

[Detailed Description of the Invention] Technical Part] The Pf misfire is based on a semiconductor photodetector using a static induction transistor, especially when the gate is the first readout device. This invention relates to an improvement in a semiconductor photodetector device using an SIT"7 which is divided into a gate and a second dart providing a potential reference.

Background Techniques (-11) For semiconductor photodetection devices using SIT, such as solid-state imaging devices, patent applications were first published in 1980 as a starting technology.
．． The most basic device was disclosed in Publication No. 5229, and a further improved version of this device 4 was patented).
Various proposals have been made, including No. 204656.

By the way, in case of a solid-state imaging device using a case-divided type SIT, the voltage applied to the shielding dart (or floating case 1) is 1h1.
It has the excellent feature that by controlling it, the output characteristics at the time of signal readout can be changed. In order to fully utilize this feature, it is preferable that the electric potential of the shielding dart does not change even when light enters each cell.

FIG. 1(A) shows l] a channel region 2 consisting of a single layer;
A source region 3A consisting of an n-layer is formed, and a shielding region 3A and a control gate region 3B consisting of a p'' layer are formed across the entirety of the source region 1.
The main part of the solid-state imaging device that is formed is shown in fragments as a concept necessary for understanding the band structure. As shown in Figure 1 (B), the structure of the valence band in such a configuration has the lowest potential near the source region, which is called the bottom of the page. has been done.

When light is applied from the outside to a solid-state imaging device with such a band structure, electron-hole pairs are generated and the holes are accumulated in the control gate region 3BK, as shown in FIG. C
) as shown in sea urchin 4, control gate region 3
B No potential or lower is 9, shielding ka-
A difference of ΔE1 occurs with respect to the potential of the target region 3A.

On the other hand, when holes are accumulated in the shielding gate region 3A, as shown in FIG. A difference of ΔE2 occurs with respect to the potential of the gate region 3B. If the potential of the sealing gate region 3A is taken as a reference, the potential of the control gate region 3B will be relatively increased by ΔE2.

On the other hand, the readout current of the signal is as shown in FIG. 1 (C) or (D
) This corresponds to the change in the band due to hole accumulation shown in . Therefore, in the case as shown in FIG. 1 (]), even if no holes due to incident light are accumulated in the control gate region 3B, a signal is output as if light had been incident. There is a possibility that

FIG. 1(E) shows the band structure including the control gate region 3C of the adjacent cell.

In this figure, most of the holes generated when light is incident on the sensor L on the left are in the control case 1.
・Although some holes are accumulated in region 3C, some holes are
It will also be accumulated in the ink target area 3A.

Therefore, the potential of the control gate region 3C decreases as indicated by the arrow F1, and the potential of the /-ruding gate region 3A also decreases by ΔE as indicated by the arrow F2.

In this way, when the potential of the 8-digit area 3A changes, as mentioned above, the output during signal readout! This causes a problem in that the characteristics change and, as a result, the control of the output characteristics by applying a predetermined voltage to the shielding part 8-1 and region 3A is disturbed. Furthermore, in reality, signals are read out even from cells with no incident light, resulting in a smearing phenomenon on the reproduced image.

Also, the carriers generated by the incident light (in the above example?
If holes (or holes) are also accumulated in the shielding gate region, the output signal for very weak incident light becomes small, resulting in a decrease in sensitivity.

Purpose The present invention improves the drawbacks of the prior art, completely reduces the accumulation of carriers in the shielding gate region, and improves the efficiency of carrier accumulation in the control gate region. The purpose is to provide a semiconductor photodetection device that can improve detection sensitivity and suppress fluctuations in the potential of the 7-ruding gate region caused by incident light to better control output characteristics. That is.

DISCLOSURE OF THE INVENTION In accordance with the present invention, means are formed in the rolling gate area for suppressing any buildup of gear produced by incident light.

According to one embodiment according to the invention, the inhibition N? The l1 means is a potential barrier formed at the boundary between the rolling gate region and the channel region by providing an insulating layer at the boundary.

According to another embodiment of the invention, the suppressing means includes a potential barrier formed by applying an i+5 pressure 2L to the gel navigating region -1 to the potential barrier formed by the insulating layer. Alternatively, there is the addition of a potential barrier formed by one of the source and drain regions located in close proximity to the shielding gate region.

According to a further embodiment of the invention, the suppression means include a potential barrier formed by the insulating layer with a note for the shielding gate region of the same conductivity type as the channel region. A potential barrier formed by applying a voltage in a loop shape is added.

According to a further embodiment according to the invention, the suppression means include a shielding cage in the above-mentioned potential barrier.
In this case, the incidence of light to the target area is blocked, and the light of 1·Δ is added.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the semiconductor device and detection device 1t according to the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 2, reference numeral 1 shows an embodiment of a semiconductor photodetection device using an SIT according to the present invention, and an image pickup device. Of these figures, (A) is a partially cutaway plan view, and (B) is an end surface (2) seen from the direction of arrow H in the plan view of (A). In this (B), in order to avoid complicating the diagram, components that connect each cell are omitted. 1, - Figure 2 of the cell corresponding to the pixel (BJ
The corresponding end face is shown as a miner in FIG.

2(A), (B) and FIG. 3, on the substrate 10, which is made of a material such as silicon (S) and has a high impurity density, there is a channel made of a single layer of n with a low impurity density. A region 12 is formed.

A control gate region 14 made of a p-layer with an impurity density is provided on the upper surface of the n-layer where the channel region 12 is formed. This control group
A source region 16 made of an n+ layer with high impurity density is provided around the region 14. These control region 14 and source region 16 are arranged in a regular two-dimensional matrix at appropriate intervals, as shown in FIG. 2(A). A cell corresponding to a single-stroke tree is formed by a set of control gate electrodes 14 and source regions 16.

A shielding gate region 18 made of a p-layer having a high impurity density is formed between adjacent source regions 16. An insulating layer 18I is formed at the boundary between the seeding gate region 18 and the channel region 12. Furthermore, a shielding gate region 18E is connected to the seeding gate region 18 so that a suitable full voltage can be applied from the outside.

Next, on the upper surface of the n-layer where the channel region 12 is formed, a silicon oxide (5102) film (hereinafter referred to as Simply “oxide film”
) 20 is formed for surface protection. A source electrode 22 is formed in an exposed portion of the source region 16 to connect adjacent cells. The direction of this connection, as shown in FIG. 2(A), is the direction that intersects the connection direction of the control gate L-electrode, which will be described later.

Next, the M output WtV of control group 1/area 14
A transparent control gate electrode 24 is formed at the portion r with an insulating layer 26 interposed therebetween. The insulating layer 26 is made of, for example, an oxide film, and is provided extending over the saw compensation electrode 22 . A control gate electrode 24 is formed along this insulating layer 26. That is, the insulating layer 26
A capacitor is formed between the control gate region 14 and the control gate electrode 24, and the source electrode 22 and the shielding gate region 18
E and the control gate electrode 24 are insulated from each other. The connection direction of the control gate electrode 24 and the connection direction of the source electrode 22 intersect with each other, thereby making it possible to read out information stored in any cell. That is, any one of the plurality of source electrodes 22 is selected, and the plurality of control gate electrodes 2
If any one of 4 is selected, a cell at a position where both electrodes intersect will be selected. Channel region 1 of substrate 10
A drain electrode 28 is formed on the side opposite to the n'''' layer where the 2 is formed.

The cooling cage 8-1 and the electrode 18EU are connected at a portion not shown so that a predetermined voltage can be applied to the entire shielding cage region 18.

Next, the electrical equivalent circuit of the imaging device having the above-described structure, the connection between each electrode, and the connection with the driving means will be explained.

FIG. 4(A) shows connections between the electrical circuit and external devices. Some of these connections are also shown in FIG.

First, the symbols representing the cells shown in FIG. 4(A) will be explained with reference to FIG. 4(B)'f. In this figure, SA represents a channel, and the source electrode 2
2 and a drain electrode 28 are connected.

SB c represents the control gate electrode 14, sci
9 represents a capacitor formed by an insulating layer 26 to which a control electrode 24 is connected.

Furthermore, SD represents the shielding gate region 18, to which the shielding gate region 18E is connected. SC2 represents the capacitor formed by the insulating layer 18I.

Next, in FIG. 4(A) or FIG. 3, the cell pc corresponding to the pixel unit is as shown in FIG. 2(A),
Two-dimensional matrix) A plurality of IJs are arranged in a square shape. A readout address circuit 30 is connected to each of the plurality of control cables 71 and electrodes 24, so that a readout signal voltage is sequentially applied to each desired parallelism. On the other hand, the plurality of source electrodes 22 are each connected to the drain of a transistor 40 that performs a switching operation, and the sources are each connected to an output terminal 38. The 400 transistors are connected to the video line selection circuit 32.
are connected to each. This video line selection circuit 32
From then on, selection pulse voltages are sequentially output to the transistors 40, and the transistors 40 are thereby sequentially driven.

The transistor 40 is formed by, for example, an SIT which is normally in the rOFFJ state, and the read address circuit 30 and the video line selection circuit 32 are formed by, for example, a shift line selection circuit.

In addition, the output terminal 38 and the ground, that is, the drain electrode 28
An output resistor 34 and a power supply 36 are connected between the two. Sealing case electrode 1 of each cell PC
8IK is connected to another variable power supply of 36V. This variable power supply 36V includes, for example, a variable resistor VR, a voltage variable power supply VE, and a variable capacitance capacitor VC.

Next, the overall operation of the above embodiment will be explained with reference to FIGS. 5 and 6 in addition to FIGS. 2 to 4. Note that FIG. 5 shows an outline of the band structure from the nI''L of the substrate 10 to the control gate region 14, and FIG. 6 shows the band structure from the control gate region 14 to the shielding case. The band structure up to region 18 is schematically shown.

First, when light is incident on each cell PC, electron-hole pairs are generated in the potential gradient portion formed from the channel region 12 to the control gate region 14, as shown in FIG. In detail, the incident light hν
mainly passes through the control gate region 14 and reaches the channel region 12, electrons E are excited to the conduction band CB, and holes H are generated in the valence band VB.

Electrons E move in the direction of the drain electrode 28, and holes H move in the direction of the control gate region 14 and are accumulated.

On the other hand, since the band structure extending from the channel region 12 to the shielding gate region 18 is also approximately the same as that shown in FIG.
It also moves in the direction of the sliding gate area 18.

On the other hand, considering the band structure centered on the source region 16, as shown in FIG.
The structure is such that the potential increases as the gate region 18 is reached, and a potential barrier is formed at the boundary between the shielding gate region 18 and the channel region 12 by an insulating layer 18I. has been done. A positive voltage is applied to the 7-ruding gate region 18 by a variable power source 36 (see FIG. 4(A)). Therefore, the shielding gate region 18
and the band in its vicinity descends in the direction of arrow F3 in FIG.

Therefore, the holes H moving in the direction of the shielding gate region 18 move in the direction of the control gate region 14 along the valence band VB and are accumulated in the shielding gate region 18. will not be stored.

Indeed, even when no voltage is applied from the variable power source 36V, the accumulation of holes H in the shielding gate region 18 is greatly reduced by the potential wall formed by the insulating layer 18I. .

Due to the above-mentioned effects, the accumulation of holes H in the shielding gate region 18 is suppressed, that is, with almost no fluctuation in the potential of the shielding gate region 18, carriers are transferred to each control gate region 14. Holes H are accumulated, and image information is accumulated for each cell pc. Next, a selection pulse voltage is sequentially applied by the video line selection circuit 32 to the (1) run raster 40 connected to the plurality of source electrodes 22. As a result, the corresponding L transistor 40 is driven, and the source electrode 22 and the drain electrode 28 of the plurality of cells PC arranged in the corresponding column direction among the cells PC shown in the fourth figure) are driven. It is connected to a power source 36 through all resistors 34.

This completes the preparation for the flow of source-drain current. In this state, for example, the voltage of the power supply 36 is adjusted so that each cell PC maintains a non-conductive state.

By the above-described operation, the image line from which the image information is to be read is selected. Next (・r, z”?lE output address circuit 30 causes multiple cases 1・electrode 24
Pulse heavy pressure is applied to the two in sequence.

This positions the selected video line.

The cells pc are driven one after another, and the control gate, ie, the north drain current corresponding to the amount of incident light, flows through the resistor 34.
The current flows to the output terminal 38, which is then converted into a voltage and output to the output terminal 38.

The above operation is performed for each video line, and image information corresponding to the incident light is outputted as a voltage change at the output terminal 38. Also, since the potential of the rolling cage region 18 does not change drastically, its output characteristics are maintained at well-set characteristics.

As described above, according to this embodiment, the separation between each cell PC is extremely good, and the carriers generated by the incident light are accumulated effectively, and the space where the channel is formed is effectively However, in order to further improve such an effect, it is preferable to take the following consideration into the formation of the line layer 181.

The material used for the insulating layer 18I is, for example, silicon oxide (S102) or tantalum oxide (Ta205).
Alternatively, silicon oxide (SiN, SiQN4) is used. If the thickness of this insulating layer 18I is too thin, it will lose its meaning as an insulating layer due to the tunnel effect, and if it is too thick, the influence on the channel region 12 by the voltage applied to the shielding gate electrode j8E will be weak. It's too crunchy and I like it.

The thickness of the insulating layer 181 is set in consideration of such points, and in the case of using acidic acid, it is set to, for example, 300X to 100OX.

Since TERRA silicon has a higher dielectric constant than silicon oxide, it is set to, for example, 40"H to several 1.00X.

Next, it is preferable to consider the entire Debye length when determining the distance between the insulating layer 18I and the source region 16. In other words, by setting the distance within the Debye length determined by the impurity density of the channel region 12, the influence of potential changes in the shielding gate region 18 can be favorably exerted on the potential of the channel region 12. , the output code can be easily controlled.

Next, FIGS. 7 and 8 show modified examples of the above-mentioned embodiment.
This will be explained with reference to the figures. In the above embodiment, the accumulation of holes H in the control gate region 14 is extremely effective and the sensitivity to weak incident light is greatly improved, but a large amount of carriers are removed by strong incident light. It has a relatively weak property against the occurrence of so-called pluming, which is caused by the occurrence of pluming. The following modification example takes such blooming into consideration.

FIG. 7 shows a portion of the semiconductor layer of a modified example, and FIG. 8 shows a cross section taken along the line f--Mll of this figure. Note that the same reference numerals will be used for the same components as in the above-described embodiment, and the explanation thereof will be omitted.

In this modification, shielding case area 1
A buried layer 18A made of a mesh-like p+ layer is provided below the substrate 10 at the boundary between the n-layer of the substrate 10 and the n-layer where the channel region 12 is formed.

FIG. 9 shows shielding case 1 in this configuration.
- An outline of the band structure from the p+ layer (region 18) to the n-layer (substrate 10) is shown. Variable power supply 36■ (4th figure) in the rolling cage area 18
When a positive voltage is applied (see FIG. 6), the band near the turning dart region 18 will be bent in the direction of arrow F4 in FIG. 9 as explained in FIG. 6. As is clear from this band structure, +5
Tennyar is partially elevated, so that hole 1 is absorbed. Basically, one hole H generated by the incident light has a control gate region 14.
However, when it becomes saturated, the holes H are accumulated in the buried layer 1.
8 A, K will be absorbed. Therefore, the occurrence of pluming is effectively suppressed. Buried layer 18A
Since the holes 1 are formed in a mesh shape, the area of the potential gradient portion formed at the boundary with the channel region 12 is enlarged, and holes 1] are well absorbed.

Note that if the buried layer 18A is provided over a wide range, holes Hf will be absorbed by the necessary plate, which will cause a decrease in sensitivity. Therefore, when forming the buried layer 18A, it is preferable to give sufficient consideration to these points, especially the degree of expansion of the depletion layer formed in the channel region 12 by the buried layer 18A.

FIG. 10 shows an embodiment in which the present invention is applied to an all-line sensor. Note that the same reference numerals are used for the same components as in the above-mentioned embodiment, and the explanation thereof will be omitted. .

In this embodiment, the source region 1'6L is formed continuously and commonly for each cell, and the source electrode 22
The same applies to L. Shielding''-1・Area 18L
is deleted from a part of the periphery of the control area 14.

The line sensor does not require video line selection unlike the imaging device, so it can have the simple configuration described above. Therefore, the video line selection circuit 32
Although the L and the transistor 4 OL are not necessarily necessary, they are shown for comparison with the embodiments described above.

Next, another embodiment will be described in which prevention of carrier accumulation in the pooling gate region is further improved.

This embodiment is shown in FIGS. 11(A) and 11(B), with FIG. 11(A) being a top view corresponding to FIG. 2(A), and FIG. 11(B) being 11 is an end view corresponding to FIG. 2(B), as seen from arrow X in FIG. 11(A). Incidentally, in this embodiment, the same reference numerals are used for the same components as in the above-described embodiment, and a complete explanation thereof will be omitted.

In the embodiment shown in FIGS. 11A and 11B, the source region 46 is located close to the shielding skate region 18. That is, the distance between the source region 46 and the Shield/Gugut region *f k
WAz source area 46 and control gate area 1
4, the relationship is WA, (WB. In this way, in the band structure shown in FIG. 6, the lowest potential band in the source region 46 As a result, the position of the true gate moves to the left in the figure, and the holes () become more effectively stored and bonded in the control gate region 14.Furthermore, in this embodiment, the source Insulating films 4 and 2'ff are formed on the region 46 and the shielding case region 18.
An aluminum film 4475 is formed therebetween. For this reason, no light enters the channel region 12 from the norting gate region 18, and carriers (holes H in this embodiment) are accumulated in the shielding gate region 18. There's no comparison. Note that in this embodiment, the shimmering film 44 passes through the through-hole portion 20 Hif of the oxide film 20 . Reading market area 18
The electrode is connected to the electrode and serves as a shielding gate electrode. This shimmering film 44 does not need to be provided below the controller 1 to the electrode 24, and may be provided above.

As described above, according to this embodiment, the isolation between the cell PCs is further improved. Shielding can also be achieved by forming the shielding goo deep into the channel region 12.
・Control the impurity density of the region Case-1・Region 14
This can also be achieved by making it higher than .

By using any one of the above configurations or a combination of a plurality of configurations, it is possible to improve the isolation between the cells PC, and it is possible to significantly improve the degree of integration of the cells PC arranged per unit area.

Still another embodiment of the invention is shown in FIGS. 12 and 13. In this example, the shielding case
The gate region 18B is formed of an n-layer with high impurity density and is not directly connected to the shielding gate region 18E.

A negative voltage is applied to the shielding gate region by a power source of 36W. As a result, the electrons existing in the shielding key-1 region 18B are discharged,
As a result, the shielding gate region 18B becomes positively charged and its potential changes as indicated by arrow F3 in FIG. Therefore, like the embodiments described above, the accumulation of carriers in the shielding gate region JI 8 B is reduced.

Insulating layer 1 in this shielding gate region 18B
The thickness of the insulating layer 1 in the above-mentioned embodiment is
There is no fundamental difference from 81. That is, as shown in FIG. 13, the thicknesses Δt1 and Δt2
Each of these is set to, for example, about 300 holes to 100 OX.

In all of the above embodiments, the channel is formed by a single n layer, but the channel may also be formed by a single intrinsic or p layer, and the conductivity types of the other components may be changed accordingly. Please make changes as appropriate. The source and drain may be made to correspond inversely to those in the above embodiment, and the same effect will be achieved.

In addition, 1. The transistor 40 for Todo may be an ordinary transistor gold piece, and it is also optional to integrate this transistor 40, the read address circuit 30, and the video line selection circuit 32 with the imaging device to form an integrated circuit. .

Although phosphor is mainly used as the material, other materials such as kermanium, m-v group 9 compound semiconductor, etc. can also be used.

In addition, the characteristics of SIT are normal I where the channel is non-conductive in a state of thermal equilibrium with no external voltage applied.
In addition to the J OFF type, there are normal channels that are conductive in thermal equilibrium! J, ON type may be used.

Furthermore, the shape of each part in the above embodiments may be arbitrary within the range of having similar functions. For example, in the tenth embodiment, the control electrode 24 is connected to the insulating layer 26.
It may also be covered. In this way, the controllability of the voltage applied to the control gate electrode 24 is improved, and the margin for mask alignment in the manufacturing process is improved.

In addition, in order to obtain color image information, the 7 trixes of the cell are configured to correspond to, for example, red (R), green (3), and blue (B), and the incident light is filtered through the R, G, and G colors. , B
What is necessary is to separate the lights and make them incident on each corresponding cell.

Effects As described above, according to the present invention, a means for suppressing the accumulation of carriers generated by incident light is formed in the shielding gate region. This not only effectively suppresses potential fluctuations and improves the controllability of output and characteristics, but also improves the separation between cells, which in turn has the excellent effect of improving photodetection sensitivity.

[Brief explanation of the drawing]

FIGS. 1(A) to E) are explanatory diagrams showing variations in the potential of the shielding gate region due to incident light, and FIG. 2(A) is a partial illustration of an embodiment of the imaging device according to the present invention. A broken plan view, FIG. 2 (8) is an end view seen from the arrow ■ in FIG. 2 (A), and FIG. Figure 1 (A) is a circuit diagram showing an electrical equivalent circuit as a two-dimensional imaging device, Figure 4 (] 3) is an explanatory diagram for explaining the symbol of one imaging cell, and Figure 5 is a board. Figure 6 is an explanatory diagram showing the band structure from the n layer of the control gate region to the first layer of the control gate region. FIG. 7 is a partially broken perspective view showing a modification of the present invention; FIG. 8 is a perspective view showing a cross section taken along line 1-M1l in FIG. 7; An explanatory diagram showing the band structure in the example of FIG. 8,
! FIG. 10 is a partially cutaway plan view showing an embodiment of the line sensor according to the present invention, and FIG. 11(A) is a plan view showing still another embodiment of the present invention.
Figure 11 (B) is an end view seen from arrow X in Figure 11 (A),
FIG. 12 is a sectional view showing still another embodiment of the present invention, and FIG. 13 is an explanatory view showing an enlarged portion of the shield die/finger 8 in FIG. 12. Signature plate of main part J 12...Channel area 14...Control gate area 16.16L...Source area 18.18B, 18L...Shielding gate area 18A...Embedded Layers 18I, 18BI...Insulating layer 44...Light blocking film ■(...Hole hν...Incoming light PC...Cell patent applicant Fuji Photo Film Co., Ltd. Measure 5 Figure Kai 6 Concave L7 Figure Procedure correction Rock - May 6, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1 Display of the case 1982 <[Patent Application" 1I3o929 No. 2 Title of the invention Semiconductor photodetector device 3, Relationship to the amended person's case Patent applicant 4 Agent Address: 1-13-47 Toramon, Minato-ku, Tokyo 105 Column 8 of “Claims” of the specification to be amended Contents of the amendment The scope of claims will be amended as shown in the attached sheet. Patent Claim 1: A first gate region in which carriers generated by incident light are accumulated and set at a predetermined potential at the time of signal readout, and a second gate region that provides a reference potential of the first gate region at the time of signal readout. The first and second key regions have a channel region and a SIT region bounded by a channel region.
A semiconductor photodetection device comprising: a semiconductor photodetection device comprising: a semiconductor photodetection device comprising: a semiconductor photodetection device comprising: a means for suppressing accumulation of carriers generated by incident light; a means for suppressing accumulation of carriers generated by incident light; In the device according to item 1, the suppressing means falls within the range of item 20+.
-1. A semiconductor photodetection device characterized by being a potential barrier formed at the boundary between a region and a channel region. 3. The device according to claim 2, wherein the barrier of the bottom/bar is formed by an insulating layer. 1. A semiconductor device hanging device, characterized in that the device is formed by: 4!1', 'J' In the device according to claim 3, the barrier of the poten/...
1. A semiconductor photodetecting device characterized in that a poden/yal barrier formed by one of the source and drain regions disposed close to the region is added (□J). A semiconductor photodetecting device according to item 3, wherein the potential barrier is added with a potential of a 20th-category region formed by applying a low voltage. 6!l ``t'ii'l'' DI!S required range In the device described in item 5, 1) the voltage indicated by il is in the form of a morsel, and the second gate region (the channel region has a similar conductivity as the chain channel region). 7. In the device 6 according to any one of claims 13 to 5, the 20th case region has no incident light. A semiconductor photodetecting device, characterized in that it is coated with a cutting-resistant optical layer. 8. The device according to any one of claims 1 to 7, wherein the SIT is one-dimensional. 9. In the device according to any one of claims 1 to 7, the SIT is arranged two-dimensionally. A semiconductor photodetecting device characterized in that a plurality of semiconductor photodetecting devices are arranged. 10. The device according to claim 8 or 9.
In the second case 8-1, the area is adjacent to the SI
A semiconductor photodetection device characterized in that it is provided in common to T. 11. The device according to any one of claims 1 to 10, characterized in that an excess carrier absorbing means is added in the channel region opposite to the 20th gate region. Semiconductor, - external light detection device. 12. The device according to claim 11, wherein the absorbing means has a 5y! ,
A semiconductor photodetection device characterized by comprising a % type. 13. A semiconductor photodetection device according to claim 12, wherein the absorption means is formed in a mesh shape. Procedural amendment dated 612/1980 Kazuo Wakasugi, Commissioner of the Patent Office] Case No. 1982 Patent Application No. 30929 2 Title of the invention Semiconductor photodetector device 3 Relationship with the amended beach case A'1 Patent applicant 4 Agent 105 Address 1-13-47 Toranomon, Minato-ku, Tokyo Gradient of correction Claim 1 Carriers generated by incident light are accumulated and the force
a first gate region that is set to a predetermined potential when reading a signal; and a second gate region that sets the reference potential of the first gate region when reading a signal; The 1st- and 20th-category regions are SI having a boundary with the channel region.
What is claimed is: 1. A semiconductor light detecting device comprising: a semiconductor light emitting device comprising T, wherein means for suppressing accumulation of carriers generated by the incident light is formed in the 20th gate region; 2. The device according to claim 1, wherein the suppressing means &j is a potential barrier formed at the boundary between the second channel region and the channel region. Detection device. 3 In the device according to claim 2: 1) 1
4. The device according to claim 3, wherein the potential barrier is formed of an insulating layer. 1. A semiconductor photodetection device characterized in that a potential barrier is defined by one of the source and drain regions disposed in close proximity to the source and drain regions. 5. The semiconductor photodetector according to claim 3, wherein the potential barrier is added with a potential in the 20th digit region formed by applying a voltage. Device. 6. The semiconductor photodetector according to claim 5, wherein the voltage is in the form of a current, and the 20th gate region has the same conductivity type as the channel region. Device. 7. In the device according to any one of claims 3 to 5, the region 20-1- is coated with a light-blocking layer that blocks incident light. A semiconductor photodetection device characterized by: 8. A semiconductor photodetecting device according to any one of claims 1 to 7, characterized in that a plurality of SITs are arranged one-dimensionally. 9. A semiconductor photodetection device according to any one of claims 1 to 7, wherein a plurality of the SITs are two-dimensionally arranged. 10. In the device according to claim 8 or 9, the second case-1 region is
1. A semiconductor photodetection device characterized in that it is provided commonly to both. 11. In the device according to any one of claims 8 to 10), an excess gear absorbing means is provided in the channel region opposite to the region 20, 8-1. A semiconductor photodetector device @ characterized by comprising: 12. The device according to claim 11, wherein the absorbing means has a conductivity type 2 similar to that of the first case-1 region.
- A semiconductor photodetection device characterized by comprising the following. 13. The device according to claim 12,
A semiconductor photodetecting device characterized in that the absorption means is formed in a mesh shape. 1t1 In the device according to claim 1,
A semiconductor photodetection device characterized in that the SIT is provided as an instant cell.

Claims (1)

[Claims] 1゜ A first dirt region where carriers generated by incident light are accumulated and set to a predetermined potential at the time of signal readout, and a reference potential of the first dirt region at the time of signal readout. a second dart area;
In the semiconductor photodetector device, the gate region is formed of an SIT having a boundary with a channel region, and in the second gate region, means for suppressing accumulation of carriers generated by incident light is formed. A semiconductor photodetection device characterized by: 2. A semiconductor photodetecting device according to claim 1, wherein the suppressing means is a potential barrier formed at the boundary between the second dart region and the channel region. 3. The semiconductor photodetecting device according to claim 2, wherein the potential barrier is formed of an insulating layer. 4. Permissible range of claim 3 In the apparatus according to claim 3, said 2.
A semiconductor photodetector device characterized in that a potential barrier formed by one of the source and drain regions disposed in close proximity to the second gate region is added to the Tennyar barrier. 5. The semiconductor device according to claim 3, wherein the potential barrier is added with a potential of a 20th-category region formed by applying a voltage. Photodetection device. 6. The device according to claim 5, wherein the voltage is pulsed and the 20th gate region has the same conductivity type as the channel region. Photodetection device. 7. In the device according to any one of claims 3 to 5, the second gate region is coated with a light shielding layer that blocks incident light to a certain extent. 8. The device according to any one of claims 1 to 7 (in I, a plurality of SITs are arranged in one dimension). A semiconductor photodetection device characterized in that: 9. The device according to any one of claims 1 to 7, wherein: ii. a plurality of SITs are arranged two-dimensionally; A semiconductor photodetecting device characterized in that the semiconductor photodetecting device is arranged in an array. 10. In the device according to claim 8 or 9, the 20-1 area
1. A semiconductor photodetection device characterized in that it is provided commonly to both. 11. In the device according to any one of claims 1 to 10, means for absorbing excess moyaria is added in the channel region opposite to the region 20-8-1. A semiconductor photodetection device characterized by: 12. A semiconductor photodetecting device according to claim 11, wherein the absorption means is of the 51-electrode type similar to the first dirt region. 13 In the device according to claim 12,
1. A semiconductor photodetection device, wherein the absorption means is formed in a mesh shape.