JPS59158108A - Variable phase difference oscillator - Google Patents

Variable phase difference oscillator

Info

Publication number
JPS59158108A
JPS59158108A JP3148383A JP3148383A JPS59158108A JP S59158108 A JPS59158108 A JP S59158108A JP 3148383 A JP3148383 A JP 3148383A JP 3148383 A JP3148383 A JP 3148383A JP S59158108 A JPS59158108 A JP S59158108A
Authority
JP
Japan
Prior art keywords
oscillator
circuit
output
signal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3148383A
Other languages
Japanese (ja)
Inventor
Kojiro Tajima
田島 浩二郎
Shozo Komaki
小牧 省三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3148383A priority Critical patent/JPS59158108A/en
Publication of JPS59158108A publication Critical patent/JPS59158108A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter

Abstract

PURPOSE:To widen the variable range of the phase difference between a voltage- controlled oscillator and a reference oscillator and to facilitate the size reduction and integration of a circuit by detecting the phase difference through a multiplying circuit and comparing it with a reference voltage. CONSTITUTION:When the output signal of the 1st oscillator 1 is v1=k1cosomegat and the output signal of the 2nd oscillator 12 is v2=k2cos(omegat+theta), they are applied to a multiplying circuit 8 through branching circuits 2 and 7 and the multiplying circuit 8 outputs a signal v0=kv1.v2kk1k2cosomegat.cos(omegat+theta)=V2kk1k2(cos (2omegat+theta)+costheta), where (k), k1, and k2 are proportional constants. A lowpass A lowpass filter 9 extracts a signal with an amplitude proportional to costheta from said output signal. This output is compared with the set voltage at a terminal 11 by a comparing circuit 10 and the result is applied to the control input of the voltage-controlled oscillator 12 to control the pahse difference theta corresponding to the set voltage.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、あらかじめ設定した位相差を有する二つの正
弦波信号を発生させる回路に関するものである。本発明
の回路は、例えばスペースダイパーシティ無線通信装置
の合成位相調整用の発掘器として適している。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a circuit that generates two sine wave signals having a preset phase difference. The circuit of the invention is suitable, for example, as an excavator for composite phase adjustment in a space-diaperity radio communication device.

〔従来技術の説明〕[Description of prior art]

従来のこの種の回路では、第1図のように構成されてい
る。図中1は発振器、2は分岐回路、3および4は出力
端子、5a、5bはコンデンサ、6はインダクタである
。この回路は発振器1の信号が分岐回路2により2分岐
され、一方の分岐された信号は出力端子3に供給される
。一方、分岐回路2の他方の出力信号は、コンデンサ5
a、5bおよびインダクタ6により構成される遅延回路
に加えられる。ここでコンデンサ5a、5bおよびイン
ダクタ6の定数を変化させることにより、出力端子4と
出力端子3と位相差を制御することができる。
A conventional circuit of this type is constructed as shown in FIG. In the figure, 1 is an oscillator, 2 is a branch circuit, 3 and 4 are output terminals, 5a and 5b are capacitors, and 6 is an inductor. In this circuit, a signal from an oscillator 1 is branched into two by a branch circuit 2, and one branched signal is supplied to an output terminal 3. On the other hand, the other output signal of branch circuit 2 is connected to capacitor 5.
a, 5b and an inductor 6. By changing the constants of the capacitors 5a, 5b and the inductor 6, the phase difference between the output terminals 4 and 3 can be controlled.

しかし、この回路は、コンデンサおよびインダクタの可
変範囲が有限であるため、出力端子3および4の間の位
相差の可変範囲が狭い欠点があった。またコンデンサお
よびインダクタを回路要素に含むため、回路の小型化、
集積化が難しい欠点があった。
However, this circuit has a drawback that the variable range of the phase difference between the output terminals 3 and 4 is narrow because the variable range of the capacitor and inductor is limited. In addition, since capacitors and inductors are included in the circuit elements, the circuit can be made smaller and
The drawback was that it was difficult to integrate.

〔発明の目的〕[Purpose of the invention]

本発明は、これらの欠点を除去し、二つの出力信号間の
位相差を広い範囲で可変するとともに、モノリシックI
C化に適した回路構成の位相差可変発振器を提供するこ
とを目的とする。
The present invention eliminates these drawbacks, allows the phase difference between two output signals to be varied over a wide range, and enables monolithic I
It is an object of the present invention to provide a variable phase difference oscillator with a circuit configuration suitable for C conversion.

〔発明の特徴〕[Features of the invention]

本発明は、基準信号を発生する第一の発振器と、この発
振器に等しい周波数の信号を発生しその出力信号位相が
電圧制御形の第二の発振器を備え、第一の発振器の出力
信号と第二の発振器の出力信号とを混合し、この混合出
力から低周波成分を抽出し、この低周波成分を設定電圧
と比較し、この比較出力により上記第二の発振器の信号
位相を制御するように構成されたことを特徴とする。
The present invention includes a first oscillator that generates a reference signal, and a second oscillator that generates a signal of the same frequency as that of the oscillator and whose output signal phase is voltage controlled. The output signal of the second oscillator is mixed with the output signal of the second oscillator, a low frequency component is extracted from this mixed output, this low frequency component is compared with a set voltage, and the signal phase of the second oscillator is controlled by this comparison output. It is characterized by being configured.

〔実施例による説明〕[Explanation based on examples]

第2図は本発明第一実施例回路の構成図である。 FIG. 2 is a block diagram of a circuit according to a first embodiment of the present invention.

第一の発振器1は基準周波数roの正弦波を発生する。A first oscillator 1 generates a sine wave with a reference frequency ro.

その出力は第一の分岐回路2により2分岐される第二の
発振器12は川波数foの信号を発生する電圧制御形の
発振器であって、その出力は第二の分岐回路7により2
分岐される。第一の分岐回路2および第二の分岐回路7
の各−力の出力は、それぞれ掛算回路8の二つの入力に
与えられ、その掛算回路8の出力は、低域濾波器9を介
して比較回路10の一方の入力に導かれる。この比較回
路10の一方の入力に導かれる。この比較回路10の他
方の入力端子11には、出力信号位相差を定めるための
設定電圧が与えられる。比較回路10の出力は第二の発
振器12の制御入力に加えられる。
The second oscillator 12, whose output is branched into two by the first branch circuit 2, is a voltage-controlled oscillator that generates a signal with a river wave number fo, and whose output is branched into two by the second branch circuit 7.
Branched out. First branch circuit 2 and second branch circuit 7
The outputs of each of the -powers are respectively applied to two inputs of a multiplier circuit 8, and the output of the multiplier circuit 8 is led via a low-pass filter 9 to one input of a comparator circuit 10. It is guided to one input of this comparator circuit 10. The other input terminal 11 of this comparison circuit 10 is given a set voltage for determining the output signal phase difference. The output of the comparison circuit 10 is applied to the control input of the second oscillator 12.

このような回路の動作を説明すると、第一の発振器1の
出力信号を VL =ks cos ωを 第二の発振器12の出力信号を V2 =に2cos  (ωt+θ) とすると、掛算回路8の出力には、 VO==kvl  −v2 =kklk2cosωt−cos(ωt+θ)なる信号
が得られる。ただし、k、に1、k2は比例定数である
。この信号から低域濾波器9により、cosθに比例す
る振幅の信号を抽出することができる。この出力を比較
回路IOで端子11の設定電圧として比較して、電圧制
御形の発振器12の制御入力に印加すると、この設定電
圧に応じて位相差θを制御することができる。
To explain the operation of such a circuit, if the output signal of the first oscillator 1 is VL = ks cos ω and the output signal of the second oscillator 12 is V2 = 2 cos (ωt + θ), then the output of the multiplier circuit 8 is The following signal is obtained: VO==kvl-v2=kklk2cosωt-cos(ωt+θ). However, 1 and k2 are constants of proportionality. From this signal, a low-pass filter 9 can extract a signal with an amplitude proportional to cos θ. When this output is compared with the set voltage of the terminal 11 by the comparison circuit IO and applied to the control input of the voltage-controlled oscillator 12, the phase difference θ can be controlled according to this set voltage.

第3図は第一の発振器1と第二の発振器12との位相差
θに対して低域濾波器9の出力電圧を示す。
FIG. 3 shows the output voltage of the low-pass filter 9 with respect to the phase difference θ between the first oscillator 1 and the second oscillator 12.

すなわち、例えば初期状態が図中す点であり、基準電圧
より高い直流成分が生じている場合に、電圧制御形の発
振器12にはさらに高い制御電圧が印加される。ここで
電圧制御形の発振器12の制御電圧と発振周波数が正の
関係にあるときには、発振周波数は上昇して位相差θは
拡大され、a点の平衡点まで位相差θは変化する。同様
に初期状態が0点にある場合には、電圧制御形の発振器
12は発振周波数が降下し、位相差θは平衡点aまで減
少する。このように基準電圧により位相差θを0゜〜1
80°まで制御することができる。
That is, for example, when the initial state is the point shown in the figure and a DC component higher than the reference voltage is generated, an even higher control voltage is applied to the voltage-controlled oscillator 12. Here, when there is a positive relationship between the control voltage of the voltage-controlled oscillator 12 and the oscillation frequency, the oscillation frequency increases and the phase difference θ is expanded, and the phase difference θ changes to the equilibrium point at point a. Similarly, when the initial state is at the 0 point, the oscillation frequency of the voltage-controlled oscillator 12 decreases, and the phase difference θ decreases to the equilibrium point a. In this way, the phase difference θ can be adjusted from 0° to 1 using the reference voltage.
It can be controlled up to 80°.

第4図は本発明第二実施例構成図である。図中13は両
極性比較器である。14は両極性比較器13の極性制御
端子である。他は第2図の実施例と同様である。
FIG. 4 is a configuration diagram of a second embodiment of the present invention. In the figure, 13 is a bipolar comparator. 14 is a polarity control terminal of the bipolar comparator 13. The rest is the same as the embodiment shown in FIG.

本実施例においては、極性制御端子14に加えられる電
圧が両極性比較器13を正にする場合は、第2図の実施
例と同様の動作を行う。さらに極性制御端子14により
両極性比較器を負とした場合には、第2図の実施例と逆
の制御を電圧制御形の発振器12に対して行い、第3図
中のd点に位相差θを制御する。ずなわち、基準電圧端
子11、および極性制御端子14に加える電圧により、
0°〜360°の任意の位相差θを得ることができる。
In this embodiment, when the voltage applied to the polarity control terminal 14 makes the bipolar comparator 13 positive, the same operation as in the embodiment of FIG. 2 is performed. Further, when the bipolar comparator is made negative by the polarity control terminal 14, the voltage-controlled oscillator 12 is controlled in the opposite manner to the embodiment shown in FIG. Control θ. That is, by the voltage applied to the reference voltage terminal 11 and the polarity control terminal 14,
Any phase difference θ between 0° and 360° can be obtained.

−1−記例では、低域濾波器9を比較器13の入力側に
おいたが、濾波器9を比較器13の出力側においても同
等の9Jノ果を得ることができる。
-1- In the example, the low-pass filter 9 is placed on the input side of the comparator 13, but the same result of 9J can be obtained even if the filter 9 is placed on the output side of the comparator 13.

次に、上記例に示した関係をモノリシックICに構成す
る場合の各要素について説明する。
Next, each element when configuring the relationship shown in the above example into a monolithic IC will be explained.

第5図は掛算回路8の構成の一例を示す図である。トラ
ンジスタQ1はエミッタ接地形の増幅器として作用し、
その出力負荷RにトランジスタQ2のコレクタ回路が並
列に接続される。この構成により入力11から出力OU
Tに至る信号の利得は、人力I2の信号により変化する
ことになり、出力OUTには、両人力11およびI2の
積の信号が得られる。
FIG. 5 is a diagram showing an example of the configuration of the multiplication circuit 8. Transistor Q1 acts as a grounded emitter amplifier;
The collector circuit of transistor Q2 is connected in parallel to the output load R. With this configuration, from input 11 to output OU
The gain of the signal leading to T will change depending on the signal of the human force I2, and a signal of the product of the two human forces 11 and I2 is obtained at the output OUT.

このほか、掛算回路8は簡単には適当なバイアス電圧が
与えられたダイオードによっても作ることができる。
In addition, the multiplier circuit 8 can be easily formed by a diode to which an appropriate bias voltage is applied.

第6図は低域濾波器9の構成の一例を示す図である。モ
ノリシックIC形の演算増幅器A1に、コンデンサC1
により負帰還を施して積分回路を構成する。また、この
演算増幅器A1の入力回路にも、抵抗R2およびコンデ
ンサC2によるCR低域濾波器を形成する。この回路の
入力INから出力OUTまでの伝送特性は低域濾波器の
特性となる。
FIG. 6 is a diagram showing an example of the configuration of the low-pass filter 9. A monolithic IC type operational amplifier A1 and a capacitor C1
Negative feedback is applied to form an integrating circuit. Also, a CR low-pass filter is formed in the input circuit of this operational amplifier A1 by a resistor R2 and a capacitor C2. The transmission characteristics from the input IN to the output OUT of this circuit are those of a low-pass filter.

さらに、分岐回路2および7については、抵抗分岐また
は直接分岐とすることができる。
Furthermore, branch circuits 2 and 7 can be resistive branches or direct branches.

このような要素を用いることにより、本発明の回路はモ
ノリシックICにより構成することができる。
By using such elements, the circuit of the present invention can be constructed using a monolithic IC.

上述の掛算回路8、低域濾波器9および分岐回路2.7
の構成はあくまでも例を示すものであって、ここに例示
する回路以外あさまざまな回路を用いて本発明を実施す
ることができる。
Multiplier circuit 8, low-pass filter 9 and branch circuit 2.7 described above
This configuration is merely an example, and the present invention can be implemented using various circuits other than those illustrated here.

〔効果の説明〕[Explanation of effects]

以上説明したように、本発明によれば電圧制御形の発振
器と基準発振器との位相差を掛算回路により検出し、こ
れを基準電圧と比較する構成をとるので、広い範囲に位
相差を制御できる利点がある。また回路にはインダクタ
や大形のコンデンサを含まないため、回路の小形化およ
び集積化が容易である利点がある。本発明の回路はスペ
ースダイバーシティ無線通信装置の合成位相調整用の発
振器に実施して有用であった。
As explained above, according to the present invention, the phase difference between the voltage-controlled oscillator and the reference oscillator is detected by a multiplication circuit, and this is compared with the reference voltage, so that the phase difference can be controlled over a wide range. There are advantages. Further, since the circuit does not include an inductor or a large capacitor, there is an advantage that the circuit can be easily miniaturized and integrated. The circuit of the present invention was useful when implemented in an oscillator for adjusting the composite phase of a space diversity wireless communication device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の信号発生回路の構成図。 第2図は本発明第一実施例の回路構成図。 第3図はその動作説明図。横軸に両全振器の出力位相差
をとり縦軸に低域濾波器の出力電圧を示す。 第4図は本発明第二実施例の回路構成図。 第5図は掛算回路の構成例を示す図。 第6図は低域濾波器の構成例を示す図。 1・・・基準信号を発生する第一の発振器、2・・・分
岐回路、3.4・・・出力端子、5a、5b・・・コン
デンサ、6・・・インダクタ、7・・・分岐回路、8・
・・掛算回路、9・・・低域濾波器、10・・・比較回
路、11・・・設定電圧を与える入力端子、12・・・
電圧制御形の第二の発振器、13・・・両極性比較器、
14・・・極性制御端子。 特許出願人   日本電信電話公社 代理人 弁理士 井 出 直 孝 ′M2  ロ 萬 3 図 z 萬 4I121
FIG. 1 is a configuration diagram of a conventional signal generation circuit. FIG. 2 is a circuit diagram of the first embodiment of the present invention. FIG. 3 is an explanatory diagram of the operation. The horizontal axis shows the output phase difference of both total oscillators, and the vertical axis shows the output voltage of the low-pass filter. FIG. 4 is a circuit diagram of a second embodiment of the present invention. FIG. 5 is a diagram showing an example of the configuration of a multiplication circuit. FIG. 6 is a diagram showing an example of the configuration of a low-pass filter. DESCRIPTION OF SYMBOLS 1... First oscillator that generates a reference signal, 2... Branch circuit, 3.4... Output terminal, 5a, 5b... Capacitor, 6... Inductor, 7... Branch circuit , 8・
...Multiplier circuit, 9...Low-pass filter, 10...Comparison circuit, 11...Input terminal for giving set voltage, 12...
Voltage-controlled second oscillator, 13... bipolar comparator,
14...Polarity control terminal. Patent Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney Nao Takashi Ide'M2 Roman 3 Figure z Roman 4I121

Claims (1)

【特許請求の範囲】 (11基準となる信号を発生する第一の発振器と、この
第一の発振器の出力を2分岐する第一の分岐回路と、 上記第一の発振器と等しい周波数の信号を発生しその出
力信号位相が入力電圧により変化するように構成された
第二の発振器と、 この第二の発振器の出力を2分岐する第二の分岐回路と
、 上記第一の分岐回路の一方の出力と上記第二の分岐回路
の一方の出力を二つの入力とするit)算回路と、 この掛算回路の出力から低周波信号成分を抽出する低域
濾波器と、 この低域濾波器の出力を一方の入力とし他方の入力に設
定電圧が与えられた比較回路とを備え、 上記比較回路の出力信号により上記第二の発振器の出力
信号位相が制御されるように構成され、上記第一の分岐
回路および上記第二の分岐回路の各他方の出力がそれぞ
れ二つの出力端子に導かれたことを特徴とする 位相差可変発振器。
[Claims] (11) A first oscillator that generates a reference signal, a first branch circuit that branches the output of the first oscillator into two, and a second oscillator configured to generate a signal whose output signal phase changes depending on the input voltage; a second branch circuit that branches the output of the second oscillator into two; and one of the first branch circuits. an it) multiplication circuit that receives the output and one output of the second branch circuit as two inputs; a low-pass filter that extracts a low-frequency signal component from the output of this multiplication circuit; and an output of this low-pass filter. a comparator circuit having one input of the oscillator and a set voltage given to the other input, the output signal of the second oscillator is controlled by the output signal of the comparator circuit, and the first oscillator A variable phase difference oscillator characterized in that the outputs of the other of the branch circuit and the second branch circuit are respectively guided to two output terminals.
JP3148383A 1983-02-25 1983-02-25 Variable phase difference oscillator Pending JPS59158108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3148383A JPS59158108A (en) 1983-02-25 1983-02-25 Variable phase difference oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3148383A JPS59158108A (en) 1983-02-25 1983-02-25 Variable phase difference oscillator

Publications (1)

Publication Number Publication Date
JPS59158108A true JPS59158108A (en) 1984-09-07

Family

ID=12332512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3148383A Pending JPS59158108A (en) 1983-02-25 1983-02-25 Variable phase difference oscillator

Country Status (1)

Country Link
JP (1) JPS59158108A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007121695A (en) * 2005-10-28 2007-05-17 Seiko Instruments Inc Lens drive device and electronic equipment
WO2007102300A1 (en) * 2006-03-07 2007-09-13 Nec Corporation Frequency synthesizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007121695A (en) * 2005-10-28 2007-05-17 Seiko Instruments Inc Lens drive device and electronic equipment
WO2007102300A1 (en) * 2006-03-07 2007-09-13 Nec Corporation Frequency synthesizer

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