JPH0563506A - Balanced/unbalanced conversion circuit - Google Patents

Abstract

PURPOSE:To correct a phase and a level difference of an output signal by employing a transistor(TR) for a constant current bias so as to form a differential amplifier circuit thereby connecting a correction capacitor between a base and an emitter of a signal input side TR. CONSTITUTION:A couple of output signals So<+>, So<-> resulting from balancing an input signal So are extracted from collectors of 1st and 2nd TRs Q41, Q42. Then a capacitor C41 whose capacitance corresponds to a stray capacitance Ccs between a substrate and a collector of a 3rd TRQ43 is connected between the base and the emitter of the TRQ41. The capacitor C41 is used to correct a phase difference and a level error of a couple of the output signals So<+>, So<-> due to the stray capacitance Ccs. As a result, the inputted unbalanced signal is converted into balanced signals in opposite phase having an equal level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting an unbalanced signal into a balanced signal.

[0002]

2. Description of the Related Art When a radio receiver is integrated into a one-chip IC, if the intermediate frequency filter is composed of a ceramic filter or the like, the intermediate frequency filter cannot be integrated into an IC.

Therefore, the intermediate frequency filter is
It may be considered to be configured by an active filter using a capacitor and an operational amplifier. However, at this time, if the intermediate frequency fi is set to standard 450 kHz, the area occupied by the active filter in the semiconductor pellet of the IC becomes large, which is not preferable.

Therefore, it is considered to further lower the intermediate frequency fi to 55 kHz, which is sufficiently lower than the reception band.

FIG. 5 shows an example of such an IC or radio receiver. In FIG. 5, a portion 10 surrounded by a chain line in FIG.
T1 to T8 are external terminal pins, T3 is a power supply terminal pin, and T4 is a ground terminal pin.

Further, a part or a circuit externally attached to the chain line is attached, 1 is an antenna tuning circuit, and 2 is a resonance circuit for local oscillation. The tuning circuit 1 is composed of a bar antenna (antenna tuning coil) L1 and a variable capacitor (variable capacitor) VC1.
Is composed of a local oscillation coil L2 and a variable capacitor VC2 which is interlocked with the variable capacitor VC1.

Further, SW is a power switch, BATT is a power source battery of, for example, 3 V, VR is a variable resistor for volume adjustment, SP
Is a speaker.

Then, the antenna tuning circuit 1 selects and extracts a broadcast wave signal Sr Sr = Er.sin ωr t ωr = 2πfr having a frequency fr. Note that in the subsequent signal processing, only the relative amplitude and phase of each signal are relevant, so the initial phase of each signal is omitted in the above equation and the following description.

The signal Sr is supplied to the high frequency amplifier 11 through the pin T1 of the IC 10, and the signal Sr from the amplifier 11 is supplied to the first and second mixer circuits 12 and 12.
It is supplied to A and 12B.

Further, the terminal pin T is connected to the local oscillation circuit 13.
The resonance circuit 2 is connected through 2 to form the local oscillation signal So. In this case, the oscillating frequency of the oscillating signal So is set to a value of 2fo, 2fo = (fr + fi) × 2 fi is an intermediate frequency, and fi = 55 kHz.

The oscillation signal So is supplied to a frequency dividing circuit (counter) 14 and divided into local oscillation signals Soa and Sob having a frequency of ½ and phases different from each other by 90 °.
That is, the signal is divided into signals Soa and Sob of Soa = Eo.cos .omega.o t Sob = Eo .sin .omega.o t .omega. = 2.pi.fo.

The signals Soa and Sob are supplied to the mixer circuits 12A and 12B and multiplied by the signal Sr, respectively, and the following signals Sia and Sib are extracted from the mixer circuits 12A and 12B. That is, Sia = Sr.Soa = Er.sin .omega.rt t.Eo .cos .omega.o t = .alpha. [omega] ot = [alpha] {-cos ([omega] r + [omega] o) t + cos ([omega] r- [omega] o) t} [alpha] = Er.multidot.Eo / 2 signals Sia and Sib are taken out.

Then, as will be described later, these signals Si
Of a and Sib, the signal component of the angular frequency (ωr −ωo) is used as the intermediate frequency signal, and the angular frequency (ωr + ωo)
Since the signal component of is removed, for simplicity, ignoring the signal component of the angular frequency (ωr + ωo) in the above equation, Sia = α · sin (ωr − ωo) t Sib = α · cos (ωr − ωo) t.

At this time, since the image signal Sm is Sm = Emsin ωm t ωm = ωo + ωi ωi = 2πfi, the broadcast wave signal Sr from the tuning circuit 1 contains the image signal Sm. Then, the signals Sia and Sib at this time are Sia = α · sin (ωr −ωo) t + β · sin (ωm −ωo) t Sib = α · cos (ωr −ωo) t + β · cos (ωm −ωo) t β = Em · Eo / 2. Further, further, since ωr <ωo <ωm, the above equation is Sia = α · sin (ωr−ωo) t + β · sin (ωm−ωo) t = −α · sin (ωo−ωr) t + β · sin ( ωm −ωo) t Sib = α · cos (ωr −ωo) t + β · cos (ωm −ωo) t = α · cos (ωo −ωr) t + β · cos (ωm −ωo) t.

Then, these signals Sia and Sib are supplied to the phase shift circuits 15A and 15B. This phase shift circuit 15A,
15B is composed of, for example, an active filter using a capacitor, a resistor, and an operational amplifier, and shifts the signal Sia by a value φ in the phase shift circuit 15A, and the signal Sib in a value (φ + 90 °) in the phase shift circuit 15B. )
By shifting the phase only, the phase difference between the two input signals Sia and Sib is 90 ° ± 1 ° in the 55 kHz ± 10 kHz band.
It is a phase shift to the relationship.

In this way, the signal Sib is advanced by 90 ° with respect to the signal Sia by the phase shift circuits 15A and 15B, and Sia = -α.sin (ωo-ωr) t + β ・ sin (ωm-ωo) t Sib = α ・ cos {(ωo −ωr) t + 90 °} + β ・ cos {(ωm −ωo) t + 90 °} = −α ・ sin (ωo −ωr) t−β ・ sin (ωm −ωo) t Sia and Sib are supplied to the addition circuit 16 to be added, and from the addition circuit 16, Si = Sia + Sib = −α · sin (ωo−ωr) t + β · sin (ωm−ωo) t + {{α · sin (ωo A signal Si represented by −ωr) t−β · sin (ωm−ωo) t} = − 2α · sin (ωo−ωr) t is extracted.

Here, since ωo-ωr = 2π (fo-fr) = 2πfi, the signal Si is the intended intermediate frequency signal. Further, even if the broadcast wave signal Sr from the tuning circuit 1 includes the image signal Sm, the signal component of the image signal Sm is canceled and not included in the intermediate frequency signal Si.

In this way, the intermediate frequency signal Si (and the signal component of the angular frequency (ωr + ωo)) converted from the broadcast wave signal Sr is extracted from the adder circuit 16.

Then, the intermediate frequency signal Si is supplied to the band pass filter 17 for the intermediate frequency filter.
The bandpass filter 17 is, for example, a capacitor,
It is composed of a biquad active filter that uses resistors and operational amplifiers, and its pass band is 55k.
Hz ± 3 kHz. Thus, the bandpass filter 1
At 7, the unnecessary signal components are removed and only the intermediate frequency signal Si is extracted.

Then, the extracted intermediate frequency signal S
i is supplied to the AM detection circuit 22 through the amplifier 21 to take out the audio signal Ss (and the DC component V22 of the level corresponding to the level of the intermediate frequency signal Si), and the audio signal Ss is supplied to the differential input audio amplifier. 23
Signal Ss from the amplifier 23 is supplied to the pin T
It is supplied to the speaker SP through 8 and the capacitor C5.

Further, the signal Sib from the mixer circuit 12B
Is supplied to the AGC voltage forming circuit 18 to form an AGC voltage, and this AGC voltage is supplied to the amplifier 11 as a control signal for the gain thereof and the AGC voltage is supplied to the signals Sia and Sib.
Is done. In this case, the capacitor C3 for smoothing the AGC voltage is connected to the forming circuit 18 through the pin T5. Further, this AGC voltage is applied to the phase shift circuit 15A,
15B and each operational amplifier forming the bandpass filter 17 are supplied as a reference voltage.

The detection output of the detection circuit 22 is AGC.
The AGC voltage is formed by being supplied to the voltage forming circuit 24.
This AGC voltage is supplied to the amplifiers 11 and 21 as a control signal of its gain, and AGC is performed on the intermediate frequency signals Sia, Sib, Si.

In this case, the capacitor C4 is connected to the forming circuit 24 through the pin T6, a low pass filter is constituted by the capacitor C4, and the DC voltage V22 is taken out from the detection output. A voltage is created. Also, this DC voltage V22 is
The DC component V22 supplied to the differential input of the amplifier 23 and supplied from the detection circuit 22 to the amplifier 23 together with the audio signal Ss is equivalently canceled.

Further, the variable resistor VR is connected to the amplifier 23 through the pin T7, and the gain of the amplifier 23 is controlled according to the resistance value of the variable resistor VR.
The volume is adjusted by the variable resistor VR.

The capacitor C6 is for bypassing signal components other than the audio signal Ss.

Then, in this example, the intermediate frequency f
Since i is a frequency sufficiently lower than the general intermediate frequency and the reception band, the area occupied by one stage of the bandpass filter (intermediate frequency filter) 17 becomes large when integrated into an IC, but the required selectivity characteristics are required. It is possible to reduce the number of stages for obtaining, so that in the IC 10, the area occupied by the entire bandpass filter 17 can be reduced, and the IC can be formed.

In general, when the intermediate frequency fi is low,
Although the image characteristics are deteriorated, the image characteristics are not deteriorated because the image signals Sm are removed by the circuits 12A to 16A.

Further, since the phase shift circuits 15A, 15B and the bandpass filter 17 are constituted by active filters, the circuits 15A, 15B, 17 have a limited signal level that can be handled, but the amplifier 12
Since AGC is applied to the phase shift circuits 15A, 1A,
5B and the bandpass filter 17 do not generate an excessive input.

By the way, in the above description, the local oscillator signal Soa,
If the phase difference of Sob is not 90 ° and the levels are not equal, the addition circuit 16 does not sufficiently cancel the components of the image signal Sm, and the components of the image signal Sm remain in the intermediate frequency signal Si. The characteristics deteriorate.

Therefore, in general, as shown in FIG.
The unbalanced oscillation signal So (Fig. A) from the oscillation circuit 13 is converted into balanced signals So + and So- (Figs. B and C), and these signals So + and So- are divided and the rising edge of the signal So + is obtained. The inverted signal Soa (FIG. D) is obtained, and the inverted signal Sob (FIG. E) is obtained at each rising edge of the signal So-.

That is, in this way, the signals Soa,
Sob has a frequency fo and a phase difference of 90 °, and the levels are equal to each other.
If frequency conversion is performed using these signals Soa and Sob,
The required image characteristics can be obtained.

In that case, in order to convert the oscillation signal So from the unbalanced signal to the balanced signals So + and So-,
Alternatively, as shown in FIG. 8, a differential amplifier 41 can be used.

That is, in the example shown in FIG. 7, the differential amplifier 41 is composed of transistors Q41 and Q42 and a constant current bias transistor Q43, and the oscillation signal So from the local oscillator circuit 13 is transmitted to the transistor Q41. 6A to 6C, the unbalanced signals are converted into balanced signals So + and So-. And these signals So
+ And So- are supplied to the frequency dividing circuit 14 and divided into signals Soa and Sob as shown in FIGS.
Sob is supplied to the mixing circuits 12A and 12B.

In the example shown in FIG. 8, the differential amplifier 41 is composed of transistors Q41 and Q42 and a constant current bias resistor R40. , Sob is taken out.

[0035]

However, as shown in FIG. 7, when the transistor Q43 is used for the constant current bias of the differential amplifier 41, this transistor Q43 is used.
The stray capacitance Ccs between the collector and substrate of 43 causes a problem.

That is, in FIG. 7, i41 is an alternating current component of the collector current of the transistor Q41, i42 is an alternating current component of the collector current of the transistor Q42, and ics is an alternating current component flowing through the capacitance Ccs. Since no alternating current flows, i41 + i42 = ics.

If Ccs = 0 (there is no stray capacitance Ccs), then ics = 0, so the above equation becomes i41 = -i42. That is, the currents i41 and i42 have a phase of 18
They are 0 ° different and the levels are equal to each other.
That is, the signals So + and So- obtained at the collectors of the transistors Q41 and Q42 have opposite phases and equal levels, and the duty ratio is 1: 1.

However, in reality, since Ccs> 0 (the stray capacitance Ccs exists), ics ≠ 0 and i41 ≠ i42.

Therefore, the phase difference between the signals So + and So- obtained at the collectors of the transistors Q41 and Q42 does not become 180 °, and a level difference also occurs.

When an error occurs in the phase and level between the signals So + and So-, this gives an error in the phase and level between the local oscillation signal Soa and the signal Sob, and thus the image signal Sm. Are not removed sufficiently, and the image characteristics are deteriorated.

As shown in FIG. 7, the differential amplifier 41
When the resistor R40 is used for the constant current bias, the phase error or the level error is not generated in the signals Soa and Sob, and therefore the image characteristic is not deteriorated.

However, in this case, the transistor Q4
1, it is necessary to make the base of Q42 a constant voltage in direct current,
Therefore, the constant voltage circuit 40 is required.

The present invention is intended to solve the above problems.

[0044]

For this reason, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the whole is made into an IC, and the first and second transistors Q are formed.
The emitters of 41 and Q42 are commonly connected to the collector of a third transistor Q43 for constant current bias, and the collectors of the first and second transistors Q41 and Q42 are connected to loads R41 and R42, respectively. The input signal So is supplied to the base of the transistor Q41 of the second transistor Q41.
The base of 42 is AC-grounded, and a pair of output signals So + and So− obtained by balancing the input signal So is taken out from the collectors of the first and second transistors Q41 and Q42, and at the same time, the first transistor Q41 Between the base and emitter of
A capacitor C41 having a value corresponding to the stray capacitance Ccs between the collector and substrate of the third transistor Q43 is connected, and the phase difference and the level difference between the pair of output signals So +, So- produced by the stray capacitance Ccs by the capacitor C41. Is to be corrected.

[0045]

The phase error and level error generated in the output signals So +, So- by the stray capacitance Ccs between the collector and substrate of the transistor Q43 are corrected by the capacitor C41, and the output signals So +, So- become balanced signals.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, the emitters of transistors Q41 and Q42 are commonly connected to the collector of a transistor Q43 for constant current bias, and this transistor Q43 is used.
Is connected to the ground terminal pin T4, and the collectors of the transistors Q41 and Q42 are connected to the power supply terminal pin T3 through the resistors R41 and R42 to form the differential amplifier 41.

The transistor Q43, together with the transistor Q44, constitutes the current mirror circuit 42 with the terminal pin T4 as a reference potential point. The transistor Q44 serves as the input side and the collector thereof has a constant current source Q45. Are connected.

Then, the terminal pin T3 and the transistor Q41
The oscillation signal So of frequency 2fo is supplied from the local oscillator circuit 13 to the base of the transistor Q42, and the base of the transistor Q42 is connected to the terminal pin T3. In addition, transistor Q41,
The frequency dividing circuit 14 is connected to the collector of Q42, and the oscillation signal S
oa and Sob are taken out.

Further, a correcting capacitor C41 is connected between the base and emitter of the transistor Q41 to which the oscillation signal So is supplied. The value of the capacitor C41 is optimized corresponding to the value of the stray capacitance Ccs, but as an example, C
41 = 0.4 pF.

According to such a configuration, the current ics flowing through the stray capacitance Ccs flows through the capacitor C41, so that i41 = -i42. That is, the currents i41 and i42 have a phase of 18
They are 0 ° different and the levels are equal to each other.
That is, the signals So + and So- obtained at the collectors of the transistors Q41 and Q42 have opposite phases and equal levels, and the duty ratio is 1: 1.

Therefore, the local oscillation signals Soa and Sob from the frequency dividing circuit 14 have a phase difference of 90 ° and have the same level, so that the image characteristics are not deteriorated.

FIG. 2 shows an example of measurement of the phase error (deviation from 90 °) between the signals Soa and Sob with and without the capacitor C41 connected. The horizontal axis represents the signal So. Frequency. Further, according to the measurement result, when the capacitor C41 is connected, the phase error is improved in the high frequency band as compared to when the capacitor C41 is not connected.

Further, FIGS. 3 and 4 show the signal So + when the capacitor C41 is connected and when it is not connected.
FIG. 3 shows an example of observation of the So− waveform. FIG. 3 shows the case of connection and FIG. 4 shows the case of no connection. From these figures, it can be seen that by adding the capacitor C41, the level difference between the signals So + and So- is improved, and the deviation of the duty ratio from 1: 1 is also improved.

[0054]

As described above, according to the present invention, the transistor Q43 is used for the constant current bias to configure the differential amplifier 41, and the correction capacitor is provided between the base and emitter of the transistor Q41 on the signal input side. C41
Are connected, it is possible to convert the input unbalanced signals into balanced signals having opposite phases and equal levels.

Moreover, it is only necessary to connect the capacitor C41, and the capacity of the capacitor C41 can be sufficiently small, so that the IC can be sufficiently formed.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an example of the present invention.

FIG. 2 is a diagram showing a measurement example of characteristics.

FIG. 3 is a diagram showing an example of observation of signal waveforms.

FIG. 4 is a diagram showing an example of observation of signal waveforms.

FIG. 5 is a system diagram showing an example of a one-chip IC.

FIG. 6 is a waveform diagram for explaining the present invention.

FIG. 7 is a connection diagram for explaining a conventional example.

FIG. 8 is a connection diagram for explaining a conventional example.

[Explanation of symbols]

 1 Antenna Tuning Circuit 2 Resonance Circuit for Local Oscillation 10 1 Chip IC 11 High Frequency Amplifier 12A, 12B Mixer Circuit 13 Local Oscillation Circuit 14 Dividing Circuit 15A, 15B Phase Shifting Circuit 16 Adder Circuit 17 Bandpass Filter 18 AGC Voltage Forming Circuit 21 Amplifier 22 AM detection circuit 23 Audio amplifier 24 AGC voltage forming circuit 41 Differential amplifier 42 Current mirror circuit T1 to T8 External terminal pin VR Variable resistor SP Speaker

Claims (1)

[Claims] 1. The whole is integrated into an IC, the emitters of the first and second transistors are commonly connected to the collector of a third transistor for constant current bias, and the collectors of the first and second transistors are , Each of which is connected to a load, an input signal is supplied to the base of the first transistor, the base of the second transistor is AC grounded, and the input signal is supplied from the collectors of the first and second transistors. A pair of output signals balanced is extracted, and a capacitor having a value corresponding to the stray capacitance between the collector and substrate of the third transistor is connected between the base and emitter of the first transistor, This capacitor causes the above-mentioned 1 caused by the stray capacitance.
An unbalanced / balanced conversion circuit in which a phase difference and a level difference between paired output signals are corrected.