JPS59153322A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To obtain a D/A converter with high accuracy without being much affected with the matching accuracy of a cpacitor by providing two capacitors connected at one end, plural voltage holding means and a switch means. CONSTITUTION:One end of a switch S21 is connected to a reference input terminal 21. One end of a capacitor C21 is connected to the other end of the S21 and the other end is connected to a common terminal. One end of the S22 is connected to one end of the C21 and the other end is connected to the common terminal. One end of an S24 is connected to a reference input terminal 21, one end of a C22 is connected to the other end of the S24 and the other end of the C22 is connected to the common terminal. One end of an S25 is connected to one end of the C22 and the other end of the S25 is connected to the common terminal. One end of an S23 is connected to the one end of the C21 and the other end of the S23 is connected to the one end of the C22. Each one end of the said C21, C22 is connected to the input terminal of sample hold circuits 22, 23, each one end of S26, S27 is connected to an output terminal of the circuits 22, 23, and the other ends of the S26, S27 are connected to the one end of the C21, C22. Then, the D/A converter with high accuracy without being much affected with the matching accuracy of the capacitors is obtained in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an improvement of a charge redistribution type D/A converter.

[Prior art]

FIG. 1 is an explanatory diagram showing the principle of an example of a conventional charge redistribution type D/A converter, which was prototyped by California Inu. Two canopy trees CN with equal valley lines,
C12 is initially discharged. Open all switches and start conversion from LSB. When the LSH is in the state d1-1, the switch S12 is momentarily closed and the capacitor C11 is charged to the reference voltage ■R. When d, = 0, switch Si3 is not closed. Next, only switch S11 is momentarily closed to redistribute the charge.

At this time, the terminal voltage v+ of C1+, C10
+ (+).

■12(1) becomes d, v, , /2. Then, switch S12 or 31 is activated depending on the state of the bit d2 one above LSH.
Close 3 momentarily. After that, if only the switch sr+ is closed and the charge is redistributed, it becomes ganokushita (:N, C
12 terminal voltage vt+ (2) 1, V12 (2)
is as follows3°Vil (2)=V12 (2
) = + (dz + + d+ ) VR (41 When the above operation is repeated, after the completion of the k-th charge redistribution, the terminal voltage of capacitor C11, (j2) VN (k
), Vi2 (k) becomes, and k-bit D/
A conversion is completed.

As mentioned above, the A converter is composed of two capacitors and an analog switch, and has a simple configuration and is suitable for IC implementation, but the conversion accuracy is determined by the accuracy of the matching of the two capacitors. Therefore, high accuracy cannot be expected when integrated into an IC.

〔the purpose〕

The present invention was made in order to solve the above problems, and therefore, it is an object of the present invention to realize a highly accurate charge redistribution type D/A converter in which the capacitor munching accuracy does not have much influence.

〔overview〕

In order to achieve the above object, the first gist of the present invention is to provide two capacitors connected to each other at one end,
The circuit includes 41 voltage holding means and a switch means for switching the connection state of the circuit using a switch, and the switch means has a first voltage holding means for holding a constant voltage for one moment corresponding to binary input data for each bit. and a second capacitor that holds the previous output voltage are connected in parallel with each other to generate a first voltage that redistributes the charge, and a second capacitor that holds the previous output voltage. and a second capacitor holding a constant voltage corresponding to the binary input data are connected in parallel to each other, thereby redistributing charges and applying a second voltage to the two capacitors. and a fifth voltage generated by redistributing the charge by connecting the two capacitors in parallel with each other is set as an output voltage.
The circuit is connected to obtain a D/A conversion output corresponding to the binary input data from the output voltage generated after repeating the above operation a number of times corresponding to the number of bits of the value input data. The D/A converter has the following characteristics:

The second gist of the present invention is to convert the output voltage of the previous stage into the next stage by using a 1-pin D/A conversion circuit configured as shown in (a) below using a number corresponding to the number of bits of human data. The D/A converter is characterized in that the D/A converter is connected in cascade as an input voltage, and a D/^ conversion output corresponding to the input data is obtained from the output voltage of the final stage.

(a) Two capacitors to be connected at one end, a number of voltage holding means, and a switch means for switching the connection state of the circuit using a switch, and the switch means is connected to the corresponding pit. A first capacitor that holds a constant voltage corresponding to binary input data and a second capacitor that holds a common voltage or an output voltage from a previous stage are connected in parallel to each other to redistribute charges. a first capacitor holding the generated first voltage, a common voltage or an output voltage from the previous stage; and M Me 2
(1) and a second capacitor that holds a constant voltage corresponding to the human power data are connected in direct relation to each other to generate a second voltage that is generated by redistributing the charge. 1-bit D/A conversion, in which the two capacitors are connected in parallel with each other to form a circuit configuration in which a sixth voltage generated by distributing the charge is obtained as an output voltage. circuit.

[Explanation of Examples]

The present invention will be explained below using the drawings.

FIG. 2 is a principle circuit diagram showing a circular charge redistribution type D/A converter, which is an embodiment of the D/A converter according to the present invention. In the main circuit 20, 21 is a reference input terminal to which a reference voltage v1 is applied, B21 is a switch whose one end is connected to this reference input terminal 21, and C21 is this switch S2.
324 is a switch whose one end is connected to the one end of the first capacitor C21 and the other end is connected to common; A switch whose one end is connected to the reference input terminal 21, C22 is a second capacitor whose one end is connected to the other end of the switch 24 and the other end is connected to the common, and S25 is a second capacitor whose one end is connected to the second capacitor C22. 323 is a switch whose one end is connected to the one end of the first capacitor and whose other end is connected to the one end of the second capacitor; 22.23; S26 is a sample/hold circuit (voltage holding means) whose input terminal is connected to one end of each of the capacitors C21 and C22;
A switch 827 has one end connected to the output terminal of the sample/hold circuit 22 and the other end connected to the one end of the capacitor C21, and 827 has one end connected to the output terminal of the sample/hold circuit 11523 and the other end. a switch connected to the one end of the capacitor C22;
24 is an output terminal connected to the one end of the capacitor C21. 25 is a sample/hold circuit (voltage holding means) which receives the output from the output terminal 24; 26;
is a control circuit that receives an external clock and binary input data and generates control signals to be sent to each switch of this D/A converter. Switches 821 to 327 constitute switching means.

@Figure 5 is an operation explanatory diagram showing the operation pattern of the D/A converter configured as described above. The third part shows the operation steps below.
The operation will be explained based on FIGS. (A) to (F).

(4) First, when the first bit of input data d is 1 and switch S21.0, only switch S22 is turned on and capacitor C21 is set at constant voltage dl''R (vR' reference voltage).
(pressure). When the LSB is other than (i21), the capacitor C22 stores the previous conversion result V. l-1 is retained. When LSB (1=1), switch S25 is ON
Therefore, it becomes V22”OV.

(B) Only the switch 823 is turned on to redistribute the charges to the capacitors C21° and C22VC. Terminal voltage of the capacitor after redistribution (first voltage) v2. becomes (when LSH is V.1-1mi0 and -).

This voltage V21 is held in the sample and hold circuit 26.

FC) Again dI blood 9- this time cabaret 7ri C22
(Switch S24 or 825 is ON), LS
If it is not B, the previous conversion result V held in the sample/hold circuit 22 is used. , the capacitor Cal
(switch 826 is turned on). The LSB signal switch S22 is turned on and becomes v21-OV.

(D) When only switch S23 is turned ON again and the charges are redistributed, the terminal voltage of the capacitor after redistribution (second
The voltage) v22 is (at the time of LSH, it is V., - is set as 0).

(E) Hold the second voltage 22 in the capacitor C21 [7], turn on the switch S27, and apply the 10' voltage V21 output from the sample-and-hold circuit 23.
The capacitor C22 is photoelectrically charged.

(+=')I]) and switch 823 is turned ON to perform charge redistribution tJ for the 31st bit, the voltage at the GABA/R terminal after redistribution, that is, the D/A conversion for the 1st bit. Output■. 1 becomes. This is held in the sample/hold circuit 22 for conversion of the next bit. (The output V.1 bolded in capacitor C22 is also used in the next bit conversion.) The above operation is performed from LSB (i21) to MSB (
1: n: input; I] Number of bits of data) - By repeating the process, D/A conversion for n bits of manual data is completed, and the result ■A (=■on) is sent to the sample and hold circuit 25. ■ Holds and outputs. The output will be closed.

In a D/A converter having such a configuration, the influence of the matching accuracy of the two capacitors on the 1)/A conversion output accuracy is shown as follows. In equation (5), C21 and C22 are almost equal, so CAN:C, C22:C+Δ
If we set it as C, it becomes. The second term in equation (6) represents the error term, and this
is the error in the case of the conventional method as shown in Fig. 1, IJt(
9 in total, omitted) takes a much smaller value. For example, when the capacitor matching accuracy is 1%, Δc/c=o, o+, so the error term ΔC2//2 (
4CQ+4CΔC+Δc2) is 0.00+2
% (Tsukuda V of ΔC/2 (2C + ΔC) of the error term according to the formula
i0.25%.

In this way, in the D/A converter configured as above,
The matching accuracy of the two capacitors has a very small effect on the output accuracy. In other words, even if the matching Q accuracy of capacitor/unit ratio is not very good, it is possible to obtain higher accuracy relatively easily.

Since this is a method using a stale GABA/R, neither V'' nor electric current Mt flows in an equilibrium state, so there is no error caused by the on-resistance of the switch. .

FIG. 4 is an electric circuit diagram showing a second embodiment of the present invention, which is a further embodiment of the circuit shown in FIG. 2.

In the main recovery 40, switches 841 to 847 correspond to switches S21 to S27 in the embodiment shown in FIG.
Capacitors C41 and C42 correspond to C21 and C22. 42, the input terminals are connected to the input terminals of the
42 is an inverting amplifier connected to a simple one such as an inverter, 848 is an inverting amplifier 4 whose one end is At]
2, the other end of which is connected to the input terminal, switch 349, capacitor C43, 43 (a simple η1 device such as a source follower is sufficient), switch SSO, capacitor C44, 4
4 (a simple one such as a north follower may be sufficient) constitutes a known sample-and-hold circuit that samples and holds the output from the inverting amplifier 42, and 8
46 is a switch whose one end is connected to the output terminal of the previous buffer 45 and the other end is connected to one end of the gear/coil C1, and S47 is a switch whose one end is connected to the output terminal of the AIJ buffer 44. 46 is an output terminal of the main circuit to which the output from the inverting amplifier 42 is connected, and 45 is a feedback input terminal connected to one end of the capacitor C41. Switch S52. C45 and the buffer 47 form a known sample-and-hold circuit that inputs the output V from the main circuit 40, and S51 and the buffer 47 (
It is a switch whose one end is connected to the output terminal of a source follower (which may be a simple device such as a source follower) and whose other end is connected to the feedback terminal 45. 48 is an output terminal for sending the output of the buffer 4 to the outside. Note that the control circuit is the same as that in FIG. 2, so it is omitted. The switches 841 to S52 constitute a switch means.

FIG. 5 is an explanatory diagram showing the operation of the D/A converter configured as described above. Each operation step will be explained below based on FIGS. 5(h) to (F).

(A) When the first bit of input data d1 is 1, the switches S41 and 848. When O, switches 842 and 8
48 is turned on and the capacitor C41 is set to V4, -” d
I VRVT (VT: offset or threshold voltage of the inverting amplifier 42). LSB(
l = +), capacitor C42 has fC'#kL pressure v42 = "ol-7"T corresponding to the previous conversion result.
is retained.

The switch S45 of LSB (l21) is turned on and becomes v42-Ov.

(B) Switch 843, S47, S5
0 is turned on to redistribute the charges to the capacitors C1 and C42. The terminal voltage of the capacitor after the redistribution is transferred to the inverting amplifier 42.
is held in capacitor C44 via. At this time, the output (first voltage) of the buffer 44 becomes 41 (L
In the case of SH, ■ in equation (8). l-1”O)
.

(C) Charge dlvR again, this time using gear grasshopper C4.
2 (switch 844 or S45 is ON), and the previous conversion result V is held in capacitor C45. 1
-1 is charged to the capacitor C41 via the buffer 43 (switch S46 is ON). Sui when it's LSB.

The switch 842 is turned on and becomes v41-0■. During this time, the switch 848 is always ON.

(D) Turn on switches S43 and 848 again,
When the charges are redistributed, the terminal voltage (second voltage) v42 of GABA/R after redistribution becomes as follows (when LSH is ■.L- is set to 0).

(g) The second voltage v42 is held in the capacitor C41, and the switches S47, S48, and S5
0 is turned on and the first
The voltage ■4° is applied to the capacitor C4 through the buffer 44 at 1-.
Charge to 2.

(Fl switch again S43, S46.84
9' When the charge is redistributed for the third time as an iON, the terminal voltage of the capacitor/l after redistribution, that is, the terminal voltage of l bit D/
A conversion output V-to 17). This is connected to the capacitor C for the next pinto conversion.
43 (the output V.l held in the capacitor C42 is also used in the next (1011th bit) bit conversion).

The above operation is performed from LSB (1'-1) to MSB (i
By repeating up to 202 bits of human-powered data), the D/A conversion for n-bit human-powered data is completed, and the result is V. The voltage corresponding to n is the capacitance C4
5 and output V from terminal 48.

(When the signal is MSB, the switches 851 and 852 are turned ON instead of the switches S46 and 849 in step (F) described above).

D/A converter with the above configuration ld first ability 1
In addition to the advantages of the above example, it has the following advantages:

That is, since the offset (-1, threshold voltage) of the inverting amplifier does not affect the accuracy of the output in principle, something as simple as an inverter can be used. Furthermore, since each sample bold circuit is included in a loop, its buffers (43, 44, 47) may be simple ones such as source 7 rowers. 'Also, since high-precision parts are not required, it is suitable for IC implementation.

FIG. 6 is an electric circuit diagram showing a fifth embodiment of the present invention, in which the buffers 43, 44i of the circuit of FIG. 4 are omitted so that parts of the inverting amplifier 42 are provided with a hold function.

In the main circuit 60, switches 861 to S65 correspond to switches S4j to S45 in FIG. 4, and capacitors C61 and C62 correspond to capacitors C41 and C42. 62 is an inverting amplifier whose input terminal is connected to the connection point of the capacitors C61 and C62, and is a simple device such as an inverter; 868, one end of which is connected to the inverting amplifier 62;
C63 and C64 are capacitors whose one ends are connected to the input terminal of the inverting amplifier 62 to constitute voltage holding means, and S66 and 867 are capacitors whose one ends are connected to the input terminal of the inverting amplifier 62. are connected to the other ends of the capacitors C65 and C64, respectively, and the other ends are connected to the common, and S69 and S70 are switches whose one ends are connected to the capacitors C66 and C64, respectively, and whose ends are connected to the inverting amplifier 1liJ. 62, a switch S71 has one end connected to the output terminal of the first inverting amplifier, and the other end connects to one end of the first six capacitor C61 and the feedback input terminal 65; 64 is a switch connected to the inverting amplifier 62; This is the output terminal of the main circuit to which the output from the amplifier 62 is applied.

872, 873, C65, 65, and 66 are S51 and S52 in FIG.

Corresponds to C45, 47, and 48, respectively. Similar to FIG. 4, the control circuit is omitted.

Switches 861 to S75 constitute switching means.

FIG. 7 is an explanatory diagram showing the operation of the D/A converter having the configuration as shown in the figure. Each operation step will be explained below based on FIGS. 7(A) to 7(H).

(A) -1 When the first bit of input data d is 1, switches S61, 866, S68, dl
is 0, switch S62. Turn on S66 and 86B to charge the capacitor C61 to V6 and divR"T. When the LSB is other than (1-1), the capacitor C6
2 is the voltage v62 ” corresponding to the previous conversion result
f-1''T is held.

When it is LSB (1=1), switch S65 is turned on and becomes v62-Ov.

(B) Switches S63, 868, S66
is turned on to redistribute the charge to the capacitors C61 and C62. Capacitor terminal voltage after redistribution (first voltage)■
61 becomes (In the case of LSH, V.1-1=Q in formula 011).

(C) Switches S62 and S69 are turned on and the charges held in the capacitor C61 in (B) are removed.
Transfer to Nokushita C63. At this time, the voltage at one end of the canister is as follows.

(D) Charge d+VR again, this time using Cano (Sita C).
62 (switch S64 or S65 and S62
, S6B is ON).

(E) Switches 863, 867, 871
is turned on, and the charge corresponding to the previous conversion result held in C64 is transferred to the capacitor CIN,
1. Transfer to C62 and redistribute it together with the charge held in capacitor C62 at (D). After redistribution, the component double voltage (second voltage) ■62 becomes (For LSB, V in the +13 formula. + +
"" is set to 0).

(F) Switches S62 and 868 are turned on to reset the charge on the capacitor C61. Capacitor C6
2 holds the voltage after redistribution in (E).

(G) When not MSB, switch S6A, S
6+S, S71 turns ON, and in (C) redistribution is performed between the charge corresponding to the first voltage V61 held in the capacitor C63 and the charge corresponding to the second voltage V62 held in the capacitor C62. The terminal voltage of the capacitor after redistribution, that is, the 1st bit D/Ai conversion output ■. 1
becomes .

For MSH, switch 87 is used instead of switch S71.
2, 875 is turned on, and the D/Af conversion output V. The voltage corresponding to n is held in the capacitor C65 and output from the output terminal 66 via the buffer 65. The output will be closed.

(If not MSH, switch 862, S70
is turned ON, and the charge corresponding to Vol held in the capacitor C61 (CG) is transferred to the capacitor C64 in preparation for conversion of the next bit.

MS) 3, turn on 867 and 868.

The above operation is changed from LSB (i=l) to MSB (1=
By repeating this process until n (number of bits of input data), it is possible to perform D/A conversion on n-bit input data.

The D/A converter configured as described above has the advantage of the second embodiment as well as the advantage that the configuration is simpler because the buffers 43 and 44 of FIG. 4 are not required.

FIGS. 8 and 9 are a partial circuit diagram and a block diagram showing a fourth embodiment of the present invention. Figure 8 (A) is the second
While the embodiments shown in Figures 44 and 6 are of the 11-circulation type, these are used as a cascade-type D/A transformer V (when used, the modification to be made to the main circuit of each of the above figures is shown). 80 is a partial circuit diagram of the main circuit 20, 40° 60 of FIG. 2, FIG. 4, and FIG.
By adding S82, a 1-pin D/A converter is configured such that the conversion result of the previous stage is held in the next stage.

81 is a conversion input terminal for inputting the conversion result of the previous stage.

A broken connection as shown in Figure 8 (B) works in the same way.

FIG. 9 is a block diagram showing connections in a cascaded configuration. Reference numeral 91 is a reference input terminal to which a reference voltage is applied, and 90 is a main circuit obtained by adding the modification shown in Fig. 8 to the above-mentioned Figs. (8th
It has been added to 81) in the figure.

Switch S90. The capacitor C90 and the buffer 92 constitute a sample/hold circuit that holds the output vA from the final stage (the nth stage when the data input is n bits).
3 is the D/A output V from the buffer 92.

This is an output terminal that sends out the signal to the outside. 94 is data human power d
A delay circuit 95 generates a delay corresponding to each of 1 to dn, and 95 inputs an external clock and data inputs d, to dn through the delay circuit 94, and connects each switch of the main circuit and sample and hold circuit. This is a control circuit that generates a Mili control signal.

When the data inputs d1 to do are applied, each main circuit 90 sequentially receives the data inputs d1 to d by the four control signals from the control circuit 95.
Conversion corresponding to each bit of 1 to dn is performed.

That is, the main circuit 90 in the first stage performs conversion on the data power d1, and after adding the conversion output vA to the next stage, the second stage performs conversion on the data power d2, and this is repeated at the nth stage. d from output terminal 93 by
It is possible to obtain the same D/A conversion output as in the case of the circulation type.

Although the D/A converter with the above configuration is somewhat complex, it has the advantage that the D/A conversion speed is about 0 times faster than the (kM type).

The vgoo diagram is the D/A transformation cycle th! of FIG. 6 showing the third embodiment. FIG. 12 is an electrical circuit diagram showing a fifth embodiment of the present invention which also operates as an A/D switcher using 2I. 120 is a multiplexer for selecting channels for external analog input signals and residual output (when operating as an A/D converter); 1100 is a D/D converter;
A main circuit that performs A/D conversion based on the signal from the A/D converter multiplexer 120; The output multiplexer 140 that outputs the D/A converted output to a predetermined channel is an output hold node that holds the output from the output multiplexer 130. The main circuit 100 has a configuration in which capacitances C611C62 and 103 and 104 are inserted in the main circuit 60 of the circuit shown in FIG. ing),.

S11 to S1n are switches forming the input multiplexer 120, 5) 11 to SH□ are the output multiplexers 13
Switches constituting 0, output hold / (sofa 14
0, the capacitors C61 to Com are connected to the respective switches 5l-11 to S1 of the output multiplexer +30 (a holding canister holding the 113 horns from □, Bo1 to
B. m is this holding capacitor C6, ~ComVcson
These are output buffers that are connected to each other.

An A/D dual-purpose D/A converter configured as above (
When operating as a D/A converter 2 in the ADA converter (hereinafter referred to as an ADA converter), the sixth embodiment (FIG. 6) is used.

The operation is similar to that shown in Fig. 7). That is, in the main circuit 100, D/A is repeatedly performed in response to each bit of human data based on a control signal from a control circuit (not shown).
After conversion, the final bit () & conversion output is output to the output hold buffer of the channel l specified (by the address signal). Output as 1.

A, l) When operating the A converter as an A/D converter, the analog human power selected by the human multiplexer 120. A 1-bit comparison output ■c is outputted from the comparison output terminal 104, and a remainder output vA is outputted from the analog output terminal 105. The residual output vA is converted to the output V of the output hold buffer 140 by turning on the switch SH1 in the output multiplexer 160, for example. It becomes 1.

This output■. 1 is fed back to the input camarnaplexer 12oVC and becomes, for example, the input VH, which becomes the input for the next Pino I conversion. Set the number of bits of the output data to 2 for the above 11111 work.
If the comparison is repeated a corresponding number of times φ, the combination of the comparison outputs for each (bit conversion) cycle becomes the A/I) conversion output.

Figure 11 shows the main circuit 100 in A/D conversion mode.
FIG. Figure 11 below (
The operation will be briefly explained along each step of A) to (J). (However, in order to simplify the explanation, the buffer is excluded from tjQ.) (A First, switch S1n
, with only 5106 and 5108 turned on, the input signal V
T, and the offset (or threshold voltage) VT of the inverting amplifier are sampled onto the capacitor clo1°ClO2.

(B) Next, turn on only switches 5i05.5i09
Let the charge of capacitor ClO2 be the charge of capacitor ClO3
Transfer to.

(C) Turn on only switch SIo, 8108, and sample the s3r input to capacitor ClO2.

(T)) Only switches 5106 and 5111 are turned on to return the charge of capacitor ClO3 to capacitor ClO2.

(E) Turn on only switch 5104 and compare inputs N and V, /2.

(F) When VIN< VR/2, switch 5
Only 111 is turned ON to obtain a residual output = 2vN.

(G) Below step (J) V4N22 VR/
In case 2, only switch 5105 and 5109 is O.
The charge on the capacitor/ClO2 as N is the capacitor ClO2.
Transfer to 3.

(I(1) Only switch 5j04.8+09 is turned on to transfer the charge of capacitor ClO3 to capacitor ClO2K.

(I) Turn ON only the switches 5j05 and 8108, and sample λnoceno)v,, fz using the capacitor ClO2.

(J) Only switches 5106 and 5111 are turned on to return the discharge of the capacitor ClO3 to the capacitor ClO2. As a result, a residual output VA '' 2 Vl:N VR is obtained when the VTN is 22 V,, / 2 t/).

Note that when using the above-mentioned working oil, ClO3 with a light gap, it can also be used in parallel with the capacitor ClO4.

The A/D converter using an ADA converter like the above T41-+ has no effect on the output accuracy due to the offset (also threshold voltage) of the inverting amplifier, and does not use any resistors. C can perform A/D conversion, and the values of capacitors ClO2 and ClO3 do not affect accuracy in principle.
It has the advantage that the ON resistance of the switch does not become an error and is suitable for IC implementation.

Although the above-mentioned ADA conversion circuit is shown as having a square shape, it is also possible to use a cascade type as shown in FIG. 9, which improves the response.

-Also, by using the buffers 403 and 104 in FIG. 10, the time required for the capacitors to be connected to the external signal source can be reduced.

With the configuration shown in Figure 10, A/D conversion and D/A conversion can be performed in the same circuit, which greatly simplifies the input/output interface of, for example, a process computer system. can be converted into

Although the ADA converter shown in FIG. 10 is a modification of the circuit shown in FIG. 6, it is also possible to modify the circuit shown in FIG. 4 in the same manner to form an ADA converter.

FIG. 12 is a block diagram showing a sixth embodiment of the present invention, in which the above-mentioned AI) A converter is converted into an RC. In the figure, 200 is an IC-based A/DA converter, and 2 old is the main circuit 100 in FIG. Input multiplexer 120
゜Output multiplexer 130. An At)A conversion section consisting of an output hold buffer 14 [], etc., 202 is a reference voltage generation section that supplies a reference voltage R to this conversion section 201, and 2G3 generates a clock that drives this ADA conversion IC 200. A clock generation unit 204 generates a clock from the clock generation circuit and the M ADA conversion unit 201.
This is a control/interface unit that generates control signals based on the comparison output from the controller and has a human output interface function. The operation and timing of this IC are the same as in the fifth embodiment.

〔Effect of the invention〕

As described above, according to the present invention, a charge redistribution type D with high accuracy that does not significantly affect the mapping accuracy of the capacitor can be obtained.
/A converter can be realized. Also, it is suitable for IC conversion.9,A
-1) It can also have a conversion function.

[Brief explanation of drawings]

Figure 1 shows the conventional charge redistribution type 1) / A-variable 4-chi device 1
An electric circuit diagram showing an example, FIG. 2 is a principle circuit diagram showing an embodiment of the present invention, FIG. 5 is an operation explanatory diagram for explaining the operation of the circuit in FIG. 2, and FIG. FIG. 5 is an operation explanatory diagram for explaining the operation of the circuit in FIG. 4; FIG. 6 is an electric circuit diagram showing the fifth embodiment of the invention; 7 is an explanatory diagram created by IJ to explain the operation of the circuit in FIG. 6, FIG. 8 is a partial circuit diagram for showing the fourth embodiment of the present invention, and FIG. FIG. 10 is a block diagram showing the fifth embodiment of the present invention.
FIG. 11 is an operation explanatory diagram for explaining the A/D conversion operation of the circuit in FIG. 10, and FIG. 12 is a block diagram showing a sixth embodiment of the present invention. be. 80...1 Hinode A/D transformation device, C21, C22
, C1, C42, C61, C62, (joj, ClO2
...Capacitor/Li, SHL, Sn2, 8143, C43, C4
4, C45, C63, C64. C65, C90, ClO3, ClO4...voltage holding means, 821-327, 841-852. 86
1-S75, 890, 8101-5111...Switch, d1-do...Binary human data, Vol-1r "ol"' Output voltage, v211v4
11v61'°゛First voltage\V22, ■421 V
62 ”・Second voltage, vol...Third voltage, ■...D/person conversion output. 3 times (B) (D) 'I/zz guIl・1 rθノ -t17) (H )

Claims (2)

[Claims] (1) The first . A second capacitor, voltage holding means for inputting and holding the terminal voltage of this capacitor and charging the capacitor with the holding voltage, and switching means for switching the connection state of the circuit using a switch. and the switch means comprises: 1
By connecting the first capacitor that holds a constant voltage corresponding to the binary input data for each pin and the second capacitor that holds the common voltage switch or the previous output voltage in parallel with each other, A first voltage generated by redistributing charges, a first capacitor that holds the common voltage i or the previous output voltage, and a second capacitor that holds a constant voltage corresponding to the binary input data. A second voltage generated by redistributing the charge by connecting the two capacitors in parallel with each other is held in the two capacitors, respectively, and the two capacitors are connected in parallel with each other. The above operation is repeated a number of times corresponding to the number of bits of the binary input data described in 1.
1. A D/A converter, characterized in that the D/A converter is connected in a circuit configuration in which all D/A conversion outputs corresponding to the binary input data are performed from the output 'voltage'. (2) 1-bit D/configured as shown in (a) below.
The output voltage of the previous stage is connected in cascade to the input voltage of the next stage using the number corresponding to the number of bits of the input data, and the output voltage of the final stage is converted to a D/A conversion output corresponding to 111 Me data. A D/A converter characterized in that it obtains. (a) The first strands are connected to each other at one end. A second gap 7, a voltage holding means for inputting and holding the terminal voltage of this capacitor and charging the first gap capacitor with the holding voltage, and a switch for changing the connection state of the circuit 6. a first capacitor that holds a constant voltage corresponding to binary input data of a corresponding bit; and a second capacitor that holds a common voltage or an output voltage from a previous stage. a first voltage generated by redistributing charges by connecting the capacitors in parallel with each other, a first capacitor holding a common voltage or an output voltage from the previous stage, and the binary input data; A second capacitor holding a corresponding constant voltage is connected in parallel with each other, thereby causing the two capacitors to hold a second voltage generated by redistributing the charges, respectively. A 1-bit D/A conversion circuit that connects capacitors in parallel to each other in such a way that a third voltage generated by redistributing charges is used as an output voltage.