JPS59151217A - Microcomputer - Google Patents

Abstract

PURPOSE:To increase an effective memory capacity to reduce the power consumption in the CPU waiting state, by dividing the frequency of a reference frequency signal to supply it as a low-frequency operation clock signa to the CPU only when a specific instruction is inputted. CONSTITUTION:When the CPU executes instructions successively in accordance with the command of a program to meet with a non-operation instruction, an FF9 is set by a code Ox indicating the non-operation instruction, and a clocked inverter 8a is closed, and a high-frequency signal phia from an oscillating circuit 7 is cut. Simultaneously, a clocked inverter 8b is opened, and the oscillation signal phia is supplied from the circuit 7 to a frequency dividing circuit 10 and is subjected to a proper frequency division and is supplied to the CPU. Thus, the operation speed of the CPU for execution of the non-operation instruction is lower than the normal instruction execution time, and the number of steps of non-operation instructions required for elapse of a certain time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microconverter in which the frequency of an operating clock signal inside a CPU can be switched.

FIG. 1 shows the schematic configuration of the microcomputer system. A CPU (microprocessor) 1 is connected to a RoM (read only memory) 4 and a RAM (random access memory) via an address bus 2 and a data bus 3.
It is connected to a storage device such as 5 and an input/output device 6. Then, 0PU1 is operated by the clock signal OLK supplied from the oscillation circuit 7, and the memory IJ (2, 3)
It executes instructions sequentially according to the instructions of the program stored in the computer.

However, in programming, when a predetermined time or more than a certain amount of time is required between one instruction and the next, a number of instructions called non-operation instructions are inserted between those instructions. ,OP
U1 is made to wait only for the elapse of time without exchanging any data with the external device via the input/output device 6.

Therefore, the longer the non-operation is required between certain instructions, the greater the number of steps of the non-operation instruction, and the larger the area in the ROM 4 or RAM 5 for storing this non-operation instruction. As a result, the effective storage capacity of the memory is reduced, and extra current is generated due to the OPU executing a non-operation instruction even though 0P(J is not executing any valid instruction to the outside). The problem was that it was consumed.

Therefore, the present invention lowers the frequency of the internal operating clock signal in the OPU's time waiting state by making it possible to switch the frequency of the internal operating clock signal of the CPU using the code of the non-operation instruction. It is an object of the present invention to reduce the number of steps of non-operation instructions, increase effective memory capacity, and reduce power consumption.

The present invention will be explained below with reference to the drawings - Fig. 6. Fig. 2 shows an embodiment of the present invention.

In the figure, 7 is a reference frequency signal generation circuit (oscillation circuit) including an oscillator such as a crystal oscillator.

The reference frequency signal (original oscillation signal) φ3 output from this oscillation circuit 7 or a signal obtained by appropriately dividing this original oscillation signal is supplied to the inside of the CPU via the clock 8a.・Ru.

Reference numeral 9 denotes a flip-flop, and this 7-linopfronop 9 is set by a code Ox indicating a non-operation instruction inserted in the middle of the program. When the flip-flop 9 is set, the output of the flip-flop 9 is changed to zero, the clock 8a is closed via the impark 10, and the original oscillation signal φ3 is transmitted from the oscillation circuit 7 to the CPU. Supply is being cut off.

Further, in parallel with the clocked inverter 8a, there is provided a first clocked inverter 8b which is also opened and closed in a complementary manner to the clocked inverter 8a by the output signal of the flip-flop 9.

This second clocked inverter 8b is opened when the flip-flop 9 is set by a non-operation instruction and the output signal is turned to invert, and the output signal φ from the oscillation circuit 7 is output.

is supplied to the frequency dividing circuit 10. The signal frequency-divided to an appropriate frequency by the frequency divider circuit 10 is the operating clock signal φ. be supplied to the CPU as

In the above circuit, the normal instructions of the program are OP
When U is executed, the flip-flop 9 is reset and the clocked inverter 8a is opened and 8b is closed. Therefore, the high-frequency original oscillation signal φ output from the oscillation circuit 7 remains unchanged. Internal operation clock signal φ. Should be supplied to OI'U.

Suppose that the OPU encounters a non-operation instruction while executing instructions one after another according to the instructions of the program. Then, the flip-flop 9 is turned on by the code Ox indicating this non-operation instruction, the clocked inverter 8a is closed, and the high frequency signal φ3 from the oscillation circuit 7 is cut off. At the same time, the clocked inverter 8b is opened, and the oscillation signal φ8 from the oscillation circuit 7 is supplied to the frequency division (b) path 10, and after being divided to an appropriate frequency, it is supplied to the VC. Become.

Then, when there are no non-operation instructions, the flip-flop 9 is reset again, the clocked inverter 8b is closed, and the clocked inverter 8a is opened. Therefore, OP
The original oscillation signal φ3 is again directly supplied to U from the oscillation circuit 7.

Therefore, while a non-operation instruction is being executed, a clock signal having a frequency lower than that during execution of other instructions is supplied inside the CPU, as shown in FIG. 3(C). This allows the C
The operating speed of the PU is made much slower than during normal instruction execution, and the number of non-operation instruction steps required to get through a certain amount of time is reduced.

Therefore, less memory area is required to store non-operation instructions that are intermediated between one instruction and the next in order to create a predetermined waiting time between those instructions.

As a result, the area for storing instructions that have an effect on other external devices becomes larger, and the effective storage capacity of the memory increases. Alternatively, the amount of memory required to store a certain amount of programs can be reduced.

Furthermore, in a so-called CMOS microcomputer configured with complementary MOSFETs, current flows only when a signal changes, so the higher the frequency of the operating clock signal, the greater the current consumption. However, in the circuit of the above embodiment, since the frequency of the internal operating clock signal supplied to the OPU is lowered when a non-operation instruction is executed, the power consumption in the OPU time waiting state is reduced.

Although a clocked inverter is used as a gate circuit for switching the frequency in the embodiment described in -, it is also possible to use other gate circuits such as a NAND circuit.

Furthermore, in the embodiment, the original oscillation signal from the oscillation circuit is supplied to the inside of the CPU as an operating clock signal during normal instruction execution. A frequency dividing circuit may be provided to supply the original oscillation signal from the oscillation circuit or a signal obtained by dividing the original oscillation signal by the frequency dividing circuit 10 as the operating clock signal inside the CPU.

As explained above, in the present invention, only when a specific command such as a non-operation command is input, the reference frequency hz signal is supplied to the frequency divider circuit and the frequency is divided. Since the instructions are supplied to the OPU, the number of steps such as non-operation instructions is reduced, and the memory area for storing these instructions is reduced.

As a result, the amount of available memory (l) W will be increased. It also has the effect of reducing the power consumption of the CPU in the time waiting state.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a microcomputer system, FIG. 2 is a block diagram showing an embodiment of the main part of a microcomputer according to the present invention, and FIG. 3 is a timing chart of signals in this embodiment. be. 1...OP U (microprocessor), 7...
Oscillation circuit, 9...flip-flop, 10...frequency dividing circuit, Ox...instruction code, φ. ...Operating clock signal. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] - A flip-flop whose setting and reset are controlled by a 1% fixed instruction code, and a pair of gate circuits that are opened and closed in a complementary manner by the output signal of this flip-flop to pass and cut off the reference frequency signal; A frequency dividing circuit is provided on the output side of the gate circuit of 10,000, and only when the above-mentioned specific machine enters, the reference frequency signal is supplied to the frequency dividing circuit and divided, and the OPU outputs it as a low frequency operation clock signal. A micro combinator characterized in that it is supplied to a micro combinator.