JPS59150419A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS59150419A JPS59150419A JP1397283A JP1397283A JPS59150419A JP S59150419 A JPS59150419 A JP S59150419A JP 1397283 A JP1397283 A JP 1397283A JP 1397283 A JP1397283 A JP 1397283A JP S59150419 A JPS59150419 A JP S59150419A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- compound semiconductor
- resist
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、化合物半導体装置の製造方法に係わり、特に
化合物半導体基板へのイオン注入プロセスの改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a compound semiconductor device, and particularly to an improvement in an ion implantation process into a compound semiconductor substrate.
近時、化合物半導体を用いた化合物半導体装置が研究開
発されているが、この装置では各種のイオン注入プロセ
スが必要である。従来、半導体基板に選択イオン注入を
行うには、第1図に示すレジスト1或いは第2図に示す
酸化膜2をマスクとして、半導体基板3に不純物イオン
を注入するようにしている。なお、第2図に示す構造は
酸化膜2上のレジスト(図示せず)をマスクとして酸化
膜2をパターニングしたのち、上記し・シストを剥離し
て形成されたものである。。Recently, compound semiconductor devices using compound semiconductors have been researched and developed, but these devices require various ion implantation processes. Conventionally, when performing selective ion implantation into a semiconductor substrate, impurity ions are implanted into the semiconductor substrate 3 using a resist 1 shown in FIG. 1 or an oxide film 2 shown in FIG. 2 as a mask. The structure shown in FIG. 2 is formed by patterning the oxide film 2 using a resist (not shown) on the oxide film 2 as a mask, and then peeling off the cysts as described above. .
しかしながら、半導体基板3としてInSb等の化合物
半導体を用いた場合、上記の方法では次のような問題が
あり九。すなわち、前記第1図に示す方法では、イオン
注入のダメージによシ基板30表面が非常に跪くなシ、
レジスト剥離液による基板3の浸蝕が激しい。さらに、
イオン注入のドーズ量を多くするとレジスト1が固化し
てしまい、基板30表面からレジスト1を剥離できなく
なる虞れがある。また、前記第2図に示す方法では、レ
ジスト剥離後も酸化膜2のパターンエツジにレジストが
残り、酸化膜2を弗酸系のエッチャントで除去する際、
レジストの薄膜が基板30表面に付着残存すると云う問
題がある。そして、このようなレジスト残りや基板の浸
蝕等は、後続する工程により作成した化合物半導体装置
の素子特性を劣化させる大きな要因と々る。However, when a compound semiconductor such as InSb is used as the semiconductor substrate 3, the above method has the following problems. That is, in the method shown in FIG.
The substrate 3 is severely eroded by the resist stripping solution. moreover,
If the dose of ion implantation is increased, the resist 1 will solidify, and there is a possibility that the resist 1 will not be able to be peeled off from the surface of the substrate 30. Furthermore, in the method shown in FIG. 2, the resist remains on the pattern edge of the oxide film 2 even after the resist is removed, and when the oxide film 2 is removed with a hydrofluoric acid-based etchant,
There is a problem that a thin resist film remains attached to the surface of the substrate 30. Such resist residue, substrate corrosion, etc. are major causes of deterioration of the element characteristics of the compound semiconductor device fabricated in subsequent steps.
本発明の目的は、化合物半導体基板へのイオン注入に起
因するレジスト残存や基板の浸蝕等を防止することがで
き、素子特性向上に寄与し得る化合物半導体装置の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a compound semiconductor device that can prevent resist residue and substrate erosion caused by ion implantation into a compound semiconductor substrate, and can contribute to improving device characteristics.
本発明の骨子は、レジスト及びレジスト剥離液を化合物
半導体基板表面に直接接触させるととなく、イオン注入
プロセスを行うことにある。The gist of the present invention is to perform the ion implantation process without bringing the resist and resist stripping solution into direct contact with the surface of the compound semiconductor substrate.
前述した如(InSb等の化合物半導体では、イオン注
入のダメージによシ基板表面が脆くなり、レジスト剥離
液による浸蝕が激しい。また、ドーズ量が多い場合には
レジストを剥離しきれないことがある。したがって、レ
ジスト及びレジスト剥離液を基板表面に接触させるイオ
ン注入プロセスは好ましくない。一方、前記第2図に示
したように、選択イオン注入用マスクをレジストで)e
ターニングした酸化膜に代えた場合にも、パターンエツ
ジに付着したレジストの影響がでることがある。そこで
本発明者等が鋭意研究を重ねた結果、化合物半導体基板
上の全面に絶縁膜を形成し1、この絶縁膜上でレジスト
を使用したフォトリングラフィによシ選択イオン注入用
マスクを形成することによシ、レジスト及びレジスト剥
離液による基板表面の悪影響が防止されることが見出さ
れた。また、イオン注入後の絶縁膜剥離時に絶縁膜上の
レジスト等のゴミが基板表面に接触しないよう、超音波
でゴミを落としながら絶縁膜を膜厚の半分程度までウェ
ットエツチングし、その後超音波をかけずに弗酸で絶縁
膜を完全にウェットエツチングすることによシ、基板表
面の浸蝕及びレジスト残存が確実に防止されるのが判明
した。As mentioned above (for compound semiconductors such as InSb, the substrate surface becomes brittle due to damage from ion implantation, and is severely eroded by the resist stripping solution. Also, if the dose is large, the resist may not be completely stripped). Therefore, an ion implantation process in which a resist and a resist stripping solution come into contact with the substrate surface is not preferred.On the other hand, as shown in FIG.
Even when a turned oxide film is used instead, the resist attached to the pattern edge may be affected. As a result of extensive research, the present inventors formed an insulating film over the entire surface of a compound semiconductor substrate 1, and formed a mask for selective ion implantation by photolithography using a resist on this insulating film. It has been found that, in particular, the adverse effects of the resist and resist stripping solution on the substrate surface can be prevented. In addition, to prevent dust such as resist on the insulation film from coming into contact with the substrate surface when peeling off the insulation film after ion implantation, the insulation film is wet-etched to about half its thickness while being removed using ultrasound, and then It has been found that by completely wet-etching the insulating film with hydrofluoric acid without etching, corrosion of the substrate surface and residual resist can be reliably prevented.
本発明はこのような点に着目し、化合物半導体装置を製
造する方法において、化合物半導体基板上に絶縁膜から
なる@1の被膜を形成したのち、この被膜上に該被膜と
エツチング選択比のある第2の被膜を形成し、次いでフ
ォトレジストをマスクにして上記第2の被膜をパターン
エツジしたのち該レジストを除去し、次いで上記第2の
被膜をマスク圧して上記基板に不純物をイオン注入し7
、しかるのち上記第1の被膜をウェットエツチングし、
かつ第1の被膜のエツチング途中まで該被膜に超音波を
投射するようにした方法である。The present invention has focused on such points, and in a method for manufacturing a compound semiconductor device, after forming a @1 coating made of an insulating film on a compound semiconductor substrate, an etching layer having an etching selectivity with that of the coating is formed on the coating. A second film is formed, and then the second film is pattern-edged using a photoresist as a mask, the resist is removed, and impurity ions are implanted into the substrate by pressing the second film with a mask.
, and then wet-etching the first film,
In this method, ultrasonic waves are projected onto the first film until part way through the etching of the first film.
本発明によれば、化合物半導体基板への選択イオン注入
ゾロセスにおける基板表面の浸蝕及びレジスト残存を確
実に防止することができる。According to the present invention, it is possible to reliably prevent corrosion of the substrate surface and residual resist during selective ion implantation into a compound semiconductor substrate.
このため、化合物半導体基板上に作成する半導体素子の
素子特性向上をはかり得る。また、基板へのイオン注入
が絶縁膜を介して行われるので、イオン注入による基板
表面のダメージを極めて小さくすることができる。Therefore, it is possible to improve the device characteristics of a semiconductor device formed on a compound semiconductor substrate. Furthermore, since ion implantation into the substrate is performed through the insulating film, damage to the substrate surface due to ion implantation can be extremely minimized.
第3図(、)〜(−)は本発明の一実施例を示す工程断
面図である。まず、第3図(、)に示す如く乳酸系エッ
チャント(体積比で乳酸:硝酸=6 : 1)で前処理
したN型InSb基板(化合物半導体基板)11上にス
ノ臂ツタ法により厚さ1ooo(^〕の5IO2膜(第
1の被膜)12を堆積し、この8102膜12上に第2
の被膜としてのTI膜13及びAt膜14を電子ビーム
蒸着法によシそれぞれ厚さ100〔久)、so’ooC
X)K蒸着した。FIGS. 3(-) to 3(-) are process cross-sectional views showing one embodiment of the present invention. First, as shown in FIG. 3(,), a 100 mm thick film was deposited on an N-type InSb substrate (compound semiconductor substrate) 11 pretreated with a lactic acid-based etchant (volume ratio: lactic acid: nitric acid = 6:1) using the snob vine method. A 5IO2 film (first film) 12 of (^) is deposited, and a second film 12 is deposited on this 8102 film 12.
The TI film 13 and the At film 14 as coatings were deposited by electron beam evaporation to a thickness of 100 mm, respectively, and a so'ooC film.
X) K was deposited.
次いで、At膜14上にネガ型フォトレジスト(図示せ
ず)を所望ノ4ターンに形成し、とのレジストをマスク
としてAt膜14及びTI膜13を第3図(b) K示
す如く選択エツチングした。このトキ、100〔x〕T
i膜13はAtのエッチャントが5IO2膜12のピン
ホールをったってInSb基板11を浸蝕することを防
ぐストッパとなっている。Next, a negative photoresist (not shown) is formed in four desired turns on the At film 14, and using the resist as a mask, the At film 14 and the TI film 13 are selectively etched as shown in FIG. 3(b). did. This Toki, 100[x]T
The i film 13 serves as a stopper to prevent the At etchant from penetrating the InSb substrate 11 through the pinholes in the 5IO2 film 12.
次に、前記At膜14及びTI膜13をマスクとして用
い、InSb基板11に加速電圧20 Q(k@V玉ド
ーズ量5×1014〔crn−2〕でMgのイオン注入
を行った。このとき、InSb基板11には5IO2膜
12を介してイオン注入がなされることになシ、イオン
注入によるダメージは極めて小さい。Next, using the At film 14 and the TI film 13 as masks, Mg ions were implanted into the InSb substrate 11 at an acceleration voltage of 20 Q (k@V ball dose of 5×10 14 [crn-2]). Since ions are implanted into the InSb substrate 11 through the 5IO2 film 12, damage caused by the ion implantation is extremely small.
次いで、第3図(C)に示す如く適当々エッチャントを
用い、At膜14及びT1膜13を除去した。Next, as shown in FIG. 3(C), the At film 14 and the T1 film 13 were removed using an appropriate etchant.
その後、弗酸系のエッチャントを用い、超音波(出力8
0W)を当てながら5I02膜12を膜厚の半分程度ま
でウェットエツチングした。続いて、超音波を当てると
となく 5io2膜12を、第3図(d)に示す如く完
全に弗酸でウェットエツチングした。After that, using a hydrofluoric acid-based etchant, ultrasonic waves (output 8
0W), the 5I02 film 12 was wet-etched to about half its thickness. Subsequently, by applying ultrasonic waves, the 5io2 film 12 was completely wet-etched with hydrofluoric acid as shown in FIG. 3(d).
かくして得られたInSb基板11の表面はイオン注入
によるダメージも殆んどなく、レジストの残存も全く見
られず良好なものであった。したがって、本実施例方法
による効果は明らかであシ、後続する工程で作成される
各種半導体素子の素子特性の大幅な向上をはかシ得る。The surface of the InSb substrate 11 thus obtained was in good condition with almost no damage caused by ion implantation and no residual resist at all. Therefore, the effects of the method of this embodiment are obvious, and the device characteristics of various semiconductor devices fabricated in subsequent steps can be significantly improved.
なお、本発明は上述した実施例に限定されるものではな
く、その要旨を逸脱しない範囲で、種々変形して実施す
ることができる。例えば、なければ設ける必要はない。Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, there is no need to provide it if it does not exist.
また、前記第1の被膜はスパッタ法による5102膜に
限るものではなく、CVD法、熱酸化法若しくは陽極酸
化法によるSiO2膜、その他の絶縁膜であってもよい
。Further, the first film is not limited to the 5102 film formed by sputtering, but may be an SiO2 film formed by CVD, thermal oxidation, or anodic oxidation, or other insulating films.
壕だ、前記第2の被膜はAA等の金属膜に限るものでは
なく、窒化膜であってもよく、要は第1の被膜とエツチ
ング選釈比のあるものであればよい。さらに、前記半導
体基板としてはInSbに限るものではなく、InP
r GaAs 、その他各種の化合物半導体に適用する
ことが可能である。The second film is not limited to a metal film such as AA, but may be a nitride film, as long as it has an etching selection ratio with respect to the first film. Furthermore, the semiconductor substrate is not limited to InSb, but is InP.
It is possible to apply to r GaAs and various other compound semiconductors.
第1図及び第2図はそれぞれ従来のイオン注入プロセス
を説明するための断面図、第3図(a)〜(d)は本発
明の一実施例〉示す工程断面図である。
11・・・In8b基板(化合物半導体基板)、12・
・・Sin、膜、13・・・T+膜、14・・・AI!
膜出11:i[’i人代理人弁j”ij 1 鈴江武
彦第1図
第2図1 and 2 are cross-sectional views for explaining a conventional ion implantation process, respectively, and FIGS. 3(a) to 3(d) are process cross-sectional views showing one embodiment of the present invention. 11... In8b substrate (compound semiconductor substrate), 12.
...Sin, membrane, 13...T+ membrane, 14...AI!
Membrane 11: i ['i person's proxy dialect j''ij 1 Takehiko Suzue Figure 1 Figure 2
Claims (2)
を形成する工程と、上記第1の被膜上に該被膜とエツチ
ング選択比のある第2の被膜を形成する工程と、フォト
レジストをマスクにして上記第2の被膜を・々ターニン
グしたのち該レジストを除去する工程と、次いで上記第
2の被膜をマスクにして前記基板に不純物をイオン注入
する工程と、次いで上記第2の被膜を除去する工程と、
j〜かるのち前記第1の被膜をウェットエツチングし、
かつ上記第1の被膜のエツチング途中まで該被膜に超音
波を投射する工程とを具備したことを特徴とする化合物
半導体装置の製造方法。(1) A step of forming a first film made of an insulating film on a compound semiconductor substrate, a step of forming a second film having an etching selectivity with that of the first film, and a step of forming a photoresist. a step of turning the second film as a mask and then removing the resist; a step of ion-implanting impurities into the substrate using the second film as a mask; a step of removing;
j~ After a while, wet etching the first film,
A method for manufacturing a compound semiconductor device, further comprising the step of projecting ultrasonic waves onto the first film halfway through etching the first film.
して窒化膜若しくはアルミニウム膜を用いることを特徴
とする特許請求の範囲第1項記載の化合物半導体装置の
製造方法。(2) The method for manufacturing a compound semiconductor device according to claim 1, wherein an oxide film is used as the first film, and a nitride film or an aluminum film is used as the second film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1397283A JPS59150419A (en) | 1983-01-31 | 1983-01-31 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1397283A JPS59150419A (en) | 1983-01-31 | 1983-01-31 | Manufacture of compound semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59150419A true JPS59150419A (en) | 1984-08-28 |
Family
ID=11848132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1397283A Pending JPS59150419A (en) | 1983-01-31 | 1983-01-31 | Manufacture of compound semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59150419A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4816421A (en) * | 1986-11-24 | 1989-03-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making a heteroepitaxial structure by mesotaxy induced by buried implantation |
-
1983
- 1983-01-31 JP JP1397283A patent/JPS59150419A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4816421A (en) * | 1986-11-24 | 1989-03-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making a heteroepitaxial structure by mesotaxy induced by buried implantation |
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