JPS59149521A - Power supply circuit - Google Patents

Power supply circuit

Info

Publication number
JPS59149521A
JPS59149521A JP59022147A JP2214784A JPS59149521A JP S59149521 A JPS59149521 A JP S59149521A JP 59022147 A JP59022147 A JP 59022147A JP 2214784 A JP2214784 A JP 2214784A JP S59149521 A JPS59149521 A JP S59149521A
Authority
JP
Japan
Prior art keywords
power supply
terminal
power
constant voltage
zener diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59022147A
Other languages
Japanese (ja)
Inventor
Masaaki Fumoto
麓正昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59022147A priority Critical patent/JPS59149521A/en
Publication of JPS59149521A publication Critical patent/JPS59149521A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/577—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices for plural loads

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE:To facilitate a selection of a Zener diode and to ensure the overall stability of a power supply circuit by providing a common Zener diode to two constant voltage circuit. CONSTITUTION:When the power is supplied to an LSI1 containing a memory circuit, two constant voltage circuits are prepared. Then the power is supplied to a power supply terminal 4 for protection of memory via either one of two constant voltage circuits. While the power is supplied to a power supply terminal 3 via the other constant voltage circuit as well as a power supply switch S. The bases of transistors Q1 and Q2 of both constant voltage circuits are connected directly to each other and then connected to the minus side of a power supply B via a common Zener diode D1.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、一対の動作用電源端子の他にメモリー保護用
電源端子を有するたとえば０ＭＯ８）ランジスタを使用
したメモリー回路骨ＬＳＩの電源供給回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a power supply circuit for a memory circuit LSI using, for example, a 0MO8) transistor, which has a power supply terminal for memory protection in addition to a pair of power supply terminals for operation. be.

従来例の構成とその問題点 一般にメモリー回路骨のＬＳＩ等は、通常動作時のだめ
の一対の電源端子の他に非動作時にメモリーを保持して
おくだめのメモリー保護用の電源端子を有している。し
たかつ呑、この種のＬＳＩに電源を供給する場合、通常
動作時のだめの一対の電源端子に所定の電源電圧を印加
すると共に上記保護用の電源端子にも同様に所定の電源
電圧を印加する必要かある。この場合、保護用の電源端
子に供給する電力は通常動作時のだめの一対の電源端子
に供給する電力より著しく少なくても良いが、上記端子
に印加される電圧は共にはゾ同一であることが要求され
る。したかって、この種のＬＳＩの電源供給回路は上記
条件を考慮に入れて第１図に示すように構成されるこ七
が多い。Conventional configurations and their problems In general, LSIs with memory circuits have a pair of power supply terminals that are used for normal operation, and a memory protection power supply terminal that holds the memory during non-operation. There is. However, when supplying power to this type of LSI, a predetermined power supply voltage is applied to the pair of power supply terminals used during normal operation, and a predetermined power supply voltage is similarly applied to the above-mentioned protection power supply terminal. Is it necessary? In this case, the power supplied to the protective power terminal may be significantly less than the power supplied to the pair of spare power terminals during normal operation, but the voltages applied to the terminals must be the same. required. Therefore, the power supply circuit of this type of LSI is often constructed as shown in FIG. 1, taking the above conditions into consideration.

第１図において、Ｂけ電源電池、Ｓは電源スィッチ２、
　Ｑ１＋　　Ｑ２１’Ｒ１１Ｒ２＋　　ｎ、、　　Ｄ２
　はそれぞれ定電圧回路を構成するトランジスタ、抵抗
、ツェナーダイオード、１けメモリー回路性のＬＳＩで
あり、２．　３ｉｄ通常動作時のだめの一対の電源端子
、４はメモリー保護用の電源端子、５１寸他の回路に接
続される出力端子を示している。In Figure 1, B is the power supply battery, S is the power switch 2,
Q1+ Q21'R11R2+ n,, D2
2. are transistors, resistors, Zener diodes, and 1-digit memory circuit LSIs that constitute a constant voltage circuit, respectively; 2. 3id indicates a pair of power supply terminals used during normal operation, 4 indicates a power supply terminal for memory protection, and 51 indicates an output terminal connected to other circuits.

このようにメモリー回路性のＬＳＩに電源を共給する場
合にはそれぞれ別個に定電圧回路を用意し、メモリー保
護用の電源端子４に対しては一方の定電圧回路を介して
直接に電源電圧を印加し、通常動作時のだめの電源元子
３に対しては電源スィッチＳと他方の定電圧回路を介し
て電源電圧を印加するように構成している。しかしなが
ら、この種のものでは定電圧回路が完全に分離して別々
に形成されているため、その出力電圧を完全に一致させ
ることがきわめて困難であるという欠点を有する。特に
、第１図に示すように構成した場合、抵抗Ｒ１の値を抵
抗Ｒ２の値より充分太きくしてメモリー保護用電源端子
４に流入する電流を通常動作時のだめの電源端子３に流
入する電流より充分小さくする必要があるため、ツェナ
ーダイオードＤ１．Ｄ２に流れる電流もそれぞれ大きく
異なることになり、画定電圧回路の出力電圧を一致させ
るだめにはそれぞれある条件下で選別しだツェナーダイ
オードを対にして使用する必要があり、これらの設計が
非常に困難であるという欠点を有する。In this way, when supplying power to LSIs with memory circuits, separate constant voltage circuits are prepared for each, and the power supply voltage is directly supplied to the power supply terminal 4 for memory protection through one of the constant voltage circuits. The configuration is such that the power supply voltage is applied to the power supply element 3 which is not used during normal operation through the power supply switch S and the other constant voltage circuit. However, in this type of device, the constant voltage circuits are completely separated and formed separately, so that it is extremely difficult to match the output voltages completely. In particular, when configured as shown in FIG. 1, the value of resistor R1 is made sufficiently larger than the value of resistor R2 so that the current flowing into the memory protection power supply terminal 4 is changed from the current flowing into the other power supply terminal 3 during normal operation. Since it is necessary to make the Zener diode D1. The current flowing through D2 also differs greatly, and in order to match the output voltages of the voltage regulating circuits, it is necessary to use pairs of Zener diodes that are selected under certain conditions, which makes these designs extremely difficult. It has the disadvantage of being difficult.

発明の目的 本発明は以上のような従来の欠点を除去−ｉるものであ
り、簡単な構成で製作の容易な優れた電源供給回路を提
供することを目的とする。OBJECTS OF THE INVENTION The present invention is intended to eliminate the above-mentioned conventional drawbacks, and it is an object of the present invention to provide an excellent power supply circuit that has a simple configuration and is easy to manufacture.

発明の構成 上記の目的を達成するだめ、本発明の電源供給回路は、
コレクタが直接電源の一方の端子に接続さ力１、エミッ
タがＬ’ＳＩのメモリー保護用電源端子に接続された第
１のトランジスタのベースと、コレクタが電源スィッチ
を介して上記電源の一方の端子に接続され、エミッタか
上記ＬＳＩの動作用電源端子に接続された第２のトラン
ジスタのベースとをそれぞれ共通のツェナーダイオード
を介して上記電源の他方の端子に接続すると共に、上記
第１のトランジスタのベース、コレクタ間に上記第２の
トランジスタのベース、コレクタ間に接続された抵抗よ
り大きな抵抗を接続し７たことを特徴とするものである
。Structure of the Invention In order to achieve the above object, the power supply circuit of the present invention has the following features:
The base of a first transistor whose collector is directly connected to one terminal of the power supply 1, whose emitter is connected to the memory protection power supply terminal of L'SI, and whose collector is connected to one terminal of the said power supply through a power switch. The emitter of the second transistor connected to the operating power supply terminal of the LSI is connected to the other terminal of the power supply through a common Zener diode, and the emitter of the first transistor is connected to the other terminal of the power supply through a common Zener diode. The transistor is characterized in that a resistor greater than the resistor connected between the base and collector of the second transistor is connected between the base and collector.

実施例の説明 以下、本発明の電源供給回路について一実施例の図面上
ともに説明する。第２図は本発明の電源供給回路におけ
る一実施例の電気的結線図であり、図中第１図と同一の
符号を付したものは第１図と同一のものを示している。DESCRIPTION OF EMBODIMENTS The power supply circuit of the present invention will be described below with reference to the drawings of one embodiment. FIG. 2 is an electrical connection diagram of one embodiment of the power supply circuit of the present invention, and the same reference numerals as in FIG. 1 indicate the same components as in FIG. 1.

そして、第２図に示す°実施例では定電圧回路を構成す
るそれぞれのトランジスタＱ１．Ｑ２のベースが互に直
結され、共通のツェナーダイオードＤ１を介して電源Ｂ
のマイナス側に接続されている。In the embodiment shown in FIG. 2, each transistor Q1. The bases of Q2 are directly connected to each other and connected to the power supply B through a common Zener diode D1.
connected to the negative side of the

上記実施例において、電源スィッチＳかオフであるとす
ると、ツェナーダイオードＤ１に流れる電流は非常に小
さくなる。今、第３図において、ツェナーダイオードＤ
１に流れる電流を１１とすると、その端子電圧はｖｌ　
となり、ＬＳｌｌのメモリー保護用電源端子４に印加さ
れる電圧はトランジスタＱ１のベース、エミッタ間電圧
をＶＢＲＱＩとすると（Ｖ＋　＋ｖＢＸＱｊ　）となる
。In the above embodiment, if the power switch S is off, the current flowing through the Zener diode D1 becomes very small. Now, in Figure 3, the Zener diode D
If the current flowing through 1 is 11, its terminal voltage is vl
The voltage applied to the memory protection power supply terminal 4 of LSll is (V+ +vBXQj), where the voltage between the base and emitter of the transistor Q1 is VBRQI.

一方、電源スィッチＳをオンした場合にはダイオードＤ
１　　に流ｔしる電流はほとんど抵抗Ｒ２によって決定
されることになり、電源スィッチＳがオフのときに比べ
て著しく大きな電流が流れることになる。第３図におい
て、電源スィッチＳをオンしたときにツェナーダイオー
ドＤ１に流れる電流を工１とすると、ツェナーダイオー
ドＤ１の端子電圧はｖ２となり、ＬＳＩの各端子４，３
に印加される電圧はトランジスタＱ２のベース、エミッ
タ間電圧をＶＢＫＱ２とすると、それぞれ（ｖ２十Ｖｇ
ｚｑ１）＋　　（Ｖ２　＋ＶＢＩＩＱ２）と＆ル。ココ
テ、それぞれのトランジスタＱｌ、Ｑ２のベース、エミ
ッタ間電圧ｖＢＥＱ１．ｖＢＥｑ２はそわ、ぞれはＶ同
一とみ々すことができるので、ＬＳｌｌの各端子４゜３
に印加される電圧ははソ同一であるということができる
。On the other hand, when the power switch S is turned on, the diode D
Most of the current flowing through the power supply switch S is determined by the resistor R2, and a significantly larger current flows than when the power switch S is off. In FIG. 3, if the current flowing through the Zener diode D1 when the power switch S is turned on is 1, the terminal voltage of the Zener diode D1 is v2, and each terminal 4, 3 of the LSI
Assuming that the voltage between the base and emitter of transistor Q2 is VBKQ2, the voltage applied to
zz1) + (V2 +VBIIQ2) and &l. The voltage between the base and emitter of each transistor Ql and Q2 is vBEQ1. Since vBEq2 can be assumed to be the same V, each terminal 4゜3 of LSll
It can be said that the voltages applied to and are the same.

発明の効果 このように本発明によれば、２つの定電圧回路に共通に
１つのツェナーダイオードを用いているだめ、ツェナー
ダイオードの選択がきわめて容易であり、全体として安
定し２だ電源供給回路を安価にかつ容易に製作すること
ができるという優れた特長を有する。Effects of the Invention As described above, according to the present invention, since one Zener diode is commonly used in the two constant voltage circuits, it is extremely easy to select the Zener diode, and the two power supply circuits are stabilized as a whole. It has the excellent feature of being inexpensive and easy to manufacture.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の電源供給回路の電気的結線図、第２図は
本発明の電源供給回路における一実施例の電気的結線図
、第３図は同実施例の動作説明図である。 １・・・・・・メモリー回路骨ＬＳＩ、２，３・・・・
・・電源端子、４・・・・・・メモリー保護用電源端子
、Ｑｌ、Ｑ２・・・−・・トランジスタ、Ｄｌ・・・・
・・ツェナーダイオード、Ｒ，、Ｒ２・・・・・・抵抗
、Ｂ・・・・・・電源電池。FIG. 1 is an electrical connection diagram of a conventional power supply circuit, FIG. 2 is an electrical connection diagram of an embodiment of the power supply circuit of the present invention, and FIG. 3 is an explanatory diagram of the operation of the same embodiment. 1...Memory circuit bone LSI, 2,3...
...Power supply terminal, 4...Memory protection power supply terminal, Ql, Q2...--Transistor, Dl...
...Zener diode, R,, R2...Resistor, B...Power battery.

Claims (1)

【特許請求の範囲】[Claims] コレクタが直接電源の一方の端子に接続され、エミッタ
がＬＳＩのメモリー保護用電源端子に接続された第１の
トランジスタのベースと、コレクタが電源スィッチを介
して上記電源の一方の端子に接続され、エミッタか上記
ＬＳＩの動作用電源端子に接続された第２のトランジス
タのベース七をそれぞれ共通のツェナーダイオードを介
して上記電源の他方の端子に接続すると共に、上記第１
のトラン７スタのベース、コレクタ間に上記第２のトラ
ンジスタのベース、コレクタ間に接続された抵抗より大
きな抵抗を接続するように構成したことを特徴とする電
源供給回路。a base of a first transistor whose collector is directly connected to one terminal of the power supply and whose emitter is connected to a memory protection power supply terminal of the LSI, and whose collector is connected to one terminal of the power supply via a power switch; The bases of the second transistors whose emitters are connected to the operating power supply terminals of the LSI are connected to the other terminal of the power supply through common Zener diodes, and
A power supply circuit characterized in that a resistor larger than the resistor connected between the base and collector of the second transistor is connected between the base and collector of the transistor 7.
JP59022147A 1984-02-08 1984-02-08 Power supply circuit Pending JPS59149521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59022147A JPS59149521A (en) 1984-02-08 1984-02-08 Power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59022147A JPS59149521A (en) 1984-02-08 1984-02-08 Power supply circuit

Publications (1)

Publication Number Publication Date
JPS59149521A true JPS59149521A (en) 1984-08-27

Family

ID=12074746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59022147A Pending JPS59149521A (en) 1984-02-08 1984-02-08 Power supply circuit

Country Status (1)

Country Link
JP (1) JPS59149521A (en)

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