JPS59146324A - Power saving microcomputer device - Google Patents

Abstract

PURPOSE:To realize a low-power consumption computer device by determining whether the initializing processing should be executed or not in accordance with contents in a specific address of an RAM to discriminate surely and stably the power supply to the whole of the system due to a main switch and the restart of the power supply to a part of the system. CONSTITUTION:The device is so constituted that a switch circuit 4 is switched to the operation state of a CPU 5 when an auxiliary memory 11 is set and the memory 11 is reset when the CPU 5 completes the operation. In case of the execution of a prescribed processing, it is discriminated whether contents in a specific address of an RAM 7 are a specific code other than all bits ''1'' or ''0'' or not; and if they are not specific code, turning-on of a main switch 2 is recognized to execute the initializing processing such as the write of the specific code to the specific address or the like. If they are the specific code, the operation restart indication due to switching of the circuit 4 is recognized to execute the prescribed processing without executing the initializing processing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a power-saving type microcomputer device k.

In a conventional microcomputer system, the time spent performing a desired task is generally extremely small compared to the time spent waiting for instructions. For example, when inputting data from a keyboard, the ratio of the time interval for a person to press a key and input predetermined data to the time for a microcomputer to process it can reach several hundred times. When a microcomputer is working in the middle of the day, the time it takes is a few hundredths of the time it takes to wait for instructions for that work.

By the way, the microcomputer devices that have been used in the past are constantly energized not only when they are performing the required work, but also when they are waiting for instructions for that work, so it is important to consider their power consumption. , the time spent waiting for the above-mentioned instruction is wasted due to the large value of VC.

In addition, advances in semi-constrained body technology have led to the development of C-MOS with low power consumption, but it is difficult to convert central processing units (hereinafter referred to as CPUs) to C-MOS, and conventional N-MOS C-MOS
It is more expensive than U.

Furthermore, a technique for turning the power supply of the CPU ON and OFF using CPU commands and a keyboard key force detection circuit is disclosed in Japanese Patent Publication No. 17042/1987.

This method uses a memory element that is not controlled by a power supply control circuit that controls the power supply of the CPU as a flag to determine whether power is turned on by the main switch or whether the power supply control circuit is turned on. The flag is a 1-pit storage element,
That is, it is composed of 70 flips and is prone to malfunction due to noise and the like. If this flag malfunctions, there will be cases where power-on of the main switch is mistakenly recognized as power-on of the CPU, and cases where power-on of the CPU is mistakenly recognized as power-on by the main switch. In the former case, the CPU starts executing a specific program without initializing the entire system, such as resetting it, causing the entire system to malfunction or run out of control. A situation may occur in which the entire system is reset even though the desired calculation is being performed, and all the calculations being performed and the data and programs in the memory are erased. Therefore, there is currently a need for something that can reliably and stably distinguish between power-on by the main switch and a power-on operation by an instruction to resume operation of the CPU.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a power-saving microcomputer device that can reliably and stably determine whether a main switch is to energize the entire system or to resume energizing a part of the system.

Structure of the Invention The power-saving microcomputer device of the present invention includes a switch circuit that switches the power consumption of a partial circuit including a central processing unit, and a static random access memory that is written with a command “C” by the central processing unit. , and an auxiliary memory that is set by a key input from a keyboard or an interrupt signal from a peripheral device and reset by the central processing unit, and when the auxiliary memory is in the set state, the switch circuit switches to the central processing unit operating state. However, the auxiliary memory is configured to be reset when the central processing unit completes its previous operation, and the central processing unit is configured to reset the auxiliary memory when the central processing unit completes a predetermined operation. 11m or I
It determines whether or not it is a specific code other than O2, and if it is not a specific code, it recognizes that the main switch is on and executes initialization processing such as writing a specific code to the specific address. The present invention is characterized in that it is configured to recognize an instruction to restart operation of the central algorithm processing unit and execute the predetermined process without executing the initialization process.

Generally, the data in memory (including flip-flops) is undefined when the power is turned on.

Therefore, when the power of the entire microcomputer system is turned on, certain data (mostly all '01', ie, clear) is written into each memory to initialize for subsequent operations. It has been confirmed that it is statistically not constant whether the stored data of a flip-flop is 1()l or 111 when the power is turned on. It has been statistically confirmed that in most cases, all bits of stored data are "lW" or "1o1".The present invention was made by focusing on this fact, and the system Random access memory is static type, and when the main switch is turned on, a specific code with all bits that are not 1' or 0- is written to one or more specific addresses.
For example, in the case of 8 bits, “01011010” (Z
) 5A, '10110100' (2) B4, etc.), and the switch circuit is switched depending on whether the content of this specific address is a specific code or not, thereby reducing the amount of effort required. DESCRIPTION Hereinafter, one embodiment of the present invention will be described based on the drawings.

In the first stage, (1) is a power source such as a battery, and (2) is a manual main that is installed between the power source (1) and the system power circuit (3) and turns on and off the communication to the entire system. It's a switch. The power supply circuit (3) of the system consists of a constant voltage power supply circuit that supplies power to the entire system. 1J
:hf>ri・1m :1ti-+-h', 2a's"1'-1 de. This mode is controlled by the control signal of the switch circuit (4), and the CPU (5) etc. At the same time as □ is energized, the mode is switched to high current output mode.This is to minimize the power consumption in the constant voltage circuit (3) when the CPU (5) etc. are off.

Further, one end of the switch circuit (4) is connected to the output line Q□□□ of the power supply circuit (3), and the other end is connected to the CPU
It is connected not only to (5) but also to the power supply terminal of read-only memory (hereinafter referred to as ROM) (6), and the CPU
(5) and ROM (5) are turned on and off.

Here, the CPU t5) is of the N-MOS type, and controls the entire system by exchanging data with memory and peripheral devices via a data bus 05), an address bus EPJ, and a control bus Oη. Said ROM (
6) is also an IJ-MOS type and has a built-in program to control the CPU (5), and the CPU is connected via each pass line.
PU controlled. (The system random access memory (hereinafter referred to as RAM) is composed of a static C-MOS random access memory, is constantly energized from the power supply line U, and is controlled by the CPU (51). Data is read/written via the pass line. (8) is the keyboard, which is scanned by the address bus 1161 and the result is the data byte, !151
k-suke 1. 1-c-1CPTJ transmitted to TE cPU (51)
(51 't' key operation is detected. (9) is a key human power detection circuit that detects that any key on the keyboard (8) has been operated, and this detection output (a) is sent to the OR circuit GO.
is input to the set terminal of the memo 11+ via the memo IJ1ll). Note that this memory (
11) is composed of a D-type flip-flop, and a specific line D of the data bus; 15). is the D input, and the select signal from the address recorder is the clock input, and when the select signal is generated, the specific line D is input. Load the above data. In other words, memo 1 is stored under CPU control.
It is configured so that data can be written to the month I11. On the other hand, as mentioned above, this memo January Ill has a set input and is connected to the output of the OR gate σ().

The output (b) of the memo January 11) becomes the aforementioned control signal for the switch circuit (4), and the nest stabilizing multivibrator (13) that generates the reset signal for the CPU (51) and N
It is connected to one input of the OR gate 04). The output (C) of multivibrator 03) is NOR gate G4
1 is connected to the other human power. NOR gate (14
7) Output (d) is connected to the CPU (5) C) reset terminal.

In addition to the key human power detection circuit (9) output, the input of the OR gate (1α) also receives interrupts from peripheral devices, No. 46 a9+.
is supplied.

Also, when the main switch (2) is turned on, an interrupt signal H) is automatically generated and the memo IJ full is set, or the memo IJ (11+ itself detects the power restoration and sets it automatically). is configured to be

Next, the operation will be explained.

FIG. 2 shows a timing chart of main parts (a) to (e) of FIG. 1, and (e) is a waveform diagram of the power supply line of the CPU (51) and ROM ((3).
When any key is operated, the detection output (a) of the key human force detection circuit (9) rises to the logic level '11, this signal is read into the memory (11), and the output (b) changes to the logic level j11→' 01, the monostable multivibrator (13) starts operating, and the output (C) rises to logic level 111. The output (d) of the NOR gate which inputs the outputs (b) and (C) is (1)) =
'0', (C) = '1', so (d) = 10'. When the output (1) reaches the logic level °O', the switch circuit (4) is turned on and as shown in Fig. 2 (e ) as in CPU
(5) and ROM (61).However, C
The output (d) of the NOR gate t+41, which is supplied with power to the reset terminal of the PU (5), remains at logic level lOI, that is, since the CPU (51) is at the reset terminal, the CPU (51 is However, the output voltage of the monostable multivibrator (13) is reversed from logic level 111 to 101 after a certain period of time, and (b) =
101, (C) = "o", so (cl) = '
1', the reset of the CPU (5) is released, and the CPU (51f+) starts the %j operation and performs the operation shown in the flowchart in Figure 3.The reset process (a) for the CPU (5) After completion, it is 8 called “5A” (hexadecimal) in the specific address (WARMI) in ItAM (71).
Check if the bit code is stored (b),
If the check (b) determines that W A, RMφ〆5A, a cold start, that is, the initialization process (c) of the entire system is performed, and the check (b) determines that WARMφ=
If it is determined to be 5A, just to be safe, the data at another specific address (WARMI) in RAM (7) is changed to “B4” (
Check (b) whether it is (hexadecimal). In the case of WARM l〆B4, the initialization process (
Execute c) and check) WA, RMl=B4
In this case, WARM 5TART processing (e) is executed.

In the initialization process (c), the memory in the system is initialized (cleared) and a specific address (WARMI) of RAM (7) is set.

(WARMI) to each specific code 15A “g
After writing 134#, WARM S'rART processing (e) is executed.

In WARM 5TART processing (e), RAM (7)
The CPU (5) reads the stack pointer, index, data, etc. saved in
is executed. The predetermined processing (to) mentioned here is, for example, preparation for recognition, display, storage, calculation, etc. of key human power data, and when this predetermined processing (to) is completed, the CPU (51) Execute CPU off processing (step 1).

In the CPU off process (g), after transferring necessary data among the various data in the CPU (5) to the RAM (7), the off data is written in the memo 17 t11+. Then,
As shown in Figure 2(b), the output of memo IJ 1llll (
b) changes from logic level 1o1 to Jl, and the output (d) of NOR gate 04) becomes (b) = '1'.

Since (0) = 'O', it changes to (d) == l o l. In other words, the CPU (5) is reset, and the CPU
(5) The operation stops.

On the other hand, since the output (b) changes to I Q 1.1 l l, the switch circuit (4) changes from on to off, and CP
Power to U(51 and RoM(61) is turned off.

In this way, since the operation of the CPU (5) is stopped by the reset signal before the power supply voltage of the CPU (51) drops, the system operation becomes stable and reliable.

In addition, as shown in FIG. 2(d), the allowable operating time width T of the CPU (5) is determined when the output (d) as a reset signal is between logic levels 1111, and the CPU (5) and the entire system are CPU (5) is activated only when it is in stable operation.
Being able to release the reset also greatly contributes to the stability of system operation.

In the above embodiment, the memo IJ 1ll) has been described as being composed of one 7-lip flop, but this can easily be replaced with a plurality of 7-lip flops or latch circuits. For example, the output of the OR gate [11] is
The output of the first 7-lip flop is input to the second 7-lip flop, and the output of the second 7-lip flop is connected to the switch circuit (4) via the OR gate GO. It is also possible to write data to the first and second flip 70 tabs by the CPU (5).

Furthermore, in the above embodiment, power is saved by turning off the power directly using the switch circuit (4), but as is well known in C-MO8 type CPUs, as the clock frequency increases, power consumption increases and the clock is turned off. If the clock oscillator is stopped, the power consumption is small on the order of microwatts, so instead of turning the power supply on and off, turning the clock oscillator on and off can also save power.

As described in the detailed description of the invention, the power-saving microcomputer of the present invention is mass-produced because it determines whether or not to perform initialization processing depending on the contents of a specific address of a static random access memory. Although it uses parts with large power consumption, it is possible to realize a low-power microcomputer device, and it is highly reliable because it operates reliably and stably even when some circuits are turned on and off.

[Brief explanation of drawings]

FIG. 1 shows the configuration of an embodiment of a power-saving microcomputer according to the present invention, FIG. 2 is a waveform diagram of the main parts of FIG.
The figure is a flowchart of the main part of FIG. 1. (2)... Main switch, (3)... Power supply circuit,
(4)...Switch circuit, (5)...Central processing unit, (6)...Read-only memory, (7)...
・Random access memory, (8) ・Keyboard, (11) ・Memory [auxiliary memory], Q9)・
・Interrupt signal, WARMφ, WARM l...
Specific address of random access memory (c)...
Initialization processing, (f)...predetermined processing, (g)...C
PU off processing agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A switch circuit for switching the gravity consumption of a partial circuit including a central processing unit, a static type back-term access memory that is read and written by the central processing unit, and a keyboard. An auxiliary memory is provided which is set by a key manually or by an interrupt signal from a peripheral device and reset by the central processing unit g, and when the auxiliary memory is in the set state, the front h ; HVC switching is configured to reset the auxiliary memory when the central processing unit operation is completed; Or, it determines whether it is a specific code other than 10", and if it is not a specific code, it recognizes that the main switch is on and executes initialization processing such as writing a specific code to the specific address, and if it is a specific code. - The station building is equipped with a power-saving microcomputer configured to operate by switching the switch circuit (i4 open instruction and execute the predetermined process without executing the initialization process). 8. A power-saving microcomputer device according to claim 1, characterized in that the circuit is configured to turn on/off power supply or a clock signal to the central processing unit. 2. The power-saving microcomputer device according to claim 1, wherein a predetermined specific code is inserted into one or more specific addresses of the random access memory when the main switch is turned on.