JPS59141091A - Corrector for magnetic inversion type digital slave clock - Google Patents

Abstract

PURPOSE:To simplify the correcting operation for setting to standard time by correcting the time of the slave clock all simply by correcting the time of the master clock. CONSTITUTION:A master clock 1 is so arranged that a normal signal and a correction signal smaller in the cycle are selected with the turning of a correction switch 5 and the signals selected are transmitted through the same signal line 7 and a slave clock 6 is equipped with a time display section 8 driven with the outputting of a counter 13 for an input signal and a correction signal detection circuit 16 adapted to reset the counter 13 detecting a correction signal when inputted into the signal line 7. Then, the correction signal is transmitted with the correction switch 5 to correct the time display section 8 of the slave clock 6.

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to a correction device for correcting the displayed time of a magnetically reversible digital slave clock consisting of one master clock and a plurality of slave clocks. [Background Art] Conventionally, a device for correcting the displayed time in a magnetically reversible digital slave clock that drives multiple slave clocks to display the time using a periodic signal from a master clock has provided a reset line for each slave clock. If multiple child clocks go out of order, it is necessary to reset and start each child clock individually, which is very cumbersome and makes it impossible to reset and start multiple child clocks at the same time. It was not possible to match all the clock marks with the single clock. In addition, a reset start line separate from the signal line is provided between the master clock and multiple slave clocks, and a reset start switch is provided on the master clock, so that the display of all slave clocks can be corrected at the same time. It is also possible to do this, but in this case, a reset start line would be required, which would increase the cost of electrical wiring, and moreover, it would be impossible to replace the existing slave clock that does not use a reset start line. [Object of the Invention] The purpose of the great invention is to provide a reset start line separate from the signal line (by simply operating the correction switch on the master clock, the time of all slave clocks can be corrected and the master clock can be adjusted). In FIG. 1, reference numeral 1 denotes a master clock, which has a standard clock display section 2 and a monitor display section 3, and further includes a standard clock reset start switch 4 used to set the time on the standard clock display section 2. and a correction switch 5 for correcting the slave clock. 6...6 are four slave clocks connected to the master clock by line 7. It has a time display section 8 that forms time numerals by magnetically reversing each element.The standard clock display section 2 converts the output of the frequency dividing section 9 into a first counter as shown in FIG.

It counts at 0 and displays the time input through the decoder and driver D, and when the standard clock reset start switch 4 is turned on,
The frequency divider 9 and the first counter [0 are reset, and when the standard clock reset start switch 4 is turned off, the reset is canceled, frequency division and counting are started, and the time on the standard clock display section 2 can be set. 11 is a clock forming section;
A clock for the monitor and child clock, that is, a normal signal with a pulse width T11 and a pulse period of 1 minute is formed. t2 is a correction signal generator, which has a pulse width T1 and a pulse period 'r3(1
It is preferable that T and X2 be smaller than 10 minutes. ) take the correction signal of 4F. The correction switch 5 has one fixed contact 5a.
to the clock forming part 11, the local contact point 5b to the value positive number 1d generation ticket +2, and the switching contact terminal 5c to the signal line 7.
Vc are connected respectively. To explain the slave clock IC in detail, 13 is the counter of the slave clock, and the signal line 7
is connected to the clock input section, counts the sent Ordinary or Zu6 Shohakugo, and inputs each count to the time display section 8 via the decoder 14 and driver 6. Reference numeral 16 denotes a modified signal detection circuit, whose input side is connected to the signal line 7 and whose output side is connected to the reset terminal of the counter 13 via a differentiating circuit 17, respectively. This modified signal detection circuit 1
6 is triggered by the rising edge of the normal output or correction signal, and the pulse width T2 becomes T3! IJ that sends a “H” signal for bribes, etc.
) Mono multi 18 capable of IJ garu, normal or modified signal to C input, "H2" signal of mono multi 18 delayed by time t shorter than pulse width T1 via delay element 19 such as a capacitor, and input to D The D flip-flop 20 is composed of a D flip-flop 20 that inputs signals to the Q output section and outputs "H11" or "L" signals from the Q output section.
The reset terminal of is connected to the power-on clear circuit 21. Further, the monitor display section 3 of the master clock 1 is formed of a magnetic reversal type display element like the time display section 8 of the slave clock 6, and has the same structure for driving it, that is, a counter 13', a decoder 14, etc. ', a driver 15', a modified signal detection circuit 1611, a differentiation circuit 17', and a power-on clear circuit 21'. FIG. 3 shows the configuration per display element in the drivers 15, 15/ of the time display section 8 and the monitor display section 3, and shows the configuration of the normal or correction signal and the decoders 14, 14'.
The segment signal from Q is input, and the transistor Q
The outputs X and Y of 1 to Q4 are outputted to the time display section 8 and the monitor display section 3, and are connected to a single element coil. The parnu width Ts of the normal or ig'h positive signal is determined by the period 1 necessary for the display elements of the time display section 8 and the monitor display section 3 to be inverted. (Operation) The operation of this embodiment will be explained with reference to the time chart of FIG. 4. First, during hunting, the correction switch 5 is set to the normal side, that is, the switching contact is located at one of the identification contacts 5 aJlji. 1 as shown in (a) from the clock forming section 11.
(When the pulse period of 1 minute is output and inputted to the counter 13.13'K via the signal line 7, a segment signal is outputted from the decoder 14.14' accordingly. For example! , when the segment signal becomes "H", the gate 22 listens to the pulse width Tl of the normal signal, and the transistor Q5 remains on and the transistor Q6 remains off. After 74 minutes, when the segment signal is "L" again, the inverse gate 23 opens by the parnu width T1 and the coil is
→By passing a current in the Y direction, the display side and the erase side are reversed, and the time display section 8 and the monitor display section 3 are displayed in accordance with the count contents of the respective counters 13 and 13'. In this way the clock formation fa
Reference numeral 11 outputs not only a normal signal that is necessary for the counters 13 and 13', but also a pulse including an element that determines the time to apply Coil/I/VC. In this state, the correction signal detection circuit 16 outputs a normal signal. Monomulti 18.18'"Hn signal triggered at the rising edge of Cb)
D of D flip-flops 20, 20' with a delay of
Input to human power department or D flip-flop 20.20
Since the normal signal "H++ times signal" has already been input to the C human power section of ', the Q output is "L" as shown in (C).
Maintain I+. Therefore, the counters 13, 13' count without being reset, and the counters 13, 13' count the counts without being reset.
15' to the time display section 8 and monitor display section 3.
Enter. Next, a correction operation when the times of a plurality of slave clocks 6.6 or all of the slave clocks 6.6 are out of order will be described. In this case, the correction switch 5 is switched to the correction side, that is, the switching contact is switched to the other fixed contact 5b side. As a result, a correction signal with a pass/I/pass period T3 is sent out from the correction signal generator (a'l) via the signal line 7, and the correction signal detection circuit 16, 16': the counter 13.137. In this state, the corrected signal detection circuits 16 and 16' detect whether the "f(, signal)" of the monomulti 18, 18' triggered by IJ is delayed by t like (bl) at the first rising edge of the corrected signal. The signal is input to the D input part of the D free knob flow amplifier 20, 20', but the "H9 signal" by is being input, so its Q output maintains "L." However, at the second rise of the correction signal +3 after the first rise, the D input of the D free knob flop 20, 20' Since the "H" signal is input to the section, its Q output changes to "H," as shown in (C). is input to the reset terminal of ', and resets the counters 13 and 13'.
The sorted counters 13 and 13' count the third and subsequent correction signals, and perform correction operations until they match the time on the standard clock display section 2. When they match, the correction signal is activated.
Set the Sochi 5 to the normal side, that is, set the switching contact to one fixed contact 5.
The correction operation is completed by returning to side a. After that, the normal signal sent from the clock forming section n inputs the "Hl" signal to the C input section of the D flip-flop 20, and its Q output becomes "L" as shown in (C). Since the outputs of the differential outputs 17 and 17' also remain at "L +1," the counters 13 and 13' continue counting without being reset. Monomulti 18 (7) of Iki's Palless Width T4
c) Greater than the recess width l112 and the pulse frequency XgT
s is set smaller than 1 minute, preferably about +4 + Tt, while the modified signal detection circuit 16K is a modified example of the modified signal detection means that eliminates the need for the delay element 9 shown in FIG. In the time chart in Figure 6, (a) is the normal or modified signal, (b) is the output signal of the mono multi 18, and (c) is the output signal of the monomulti 18.
shows the Q output signal of the D flip-flop 20, and (d) shows the output signal of the differentiating circuit 17. , the signal is C of the D flip-flop 20
The "L" signal of the monomulti 18 falls and becomes the "L" signal, which is input to the SD input section and is generated by the Q output. In another embodiment, the correction signal is sent out via the signal line 7 by switching the correction input switch 5 of the master clock 1 to the correction side, while the 413y positive signal detection circuit 16 of the child clock 16: Counter 13 is set to 1, and Plankin clock input BI of decoder and driver 14.15 is set to “
H, so that no display output is output, and further activates the mono multi-circuit 24 to erase all displays. At the same time, the correction signal is inputted to the counter U via the wave adjustment (cedar circuit 25), so the counter B counts this and the correction operation is performed, and when the monitor display section 3 matches the standard clock display section 2, Return the correction switch 5 to the normal side. When the correct word is no longer sent out, the blanking manual BI becomes "L", blanking is canceled and the correct time is displayed. The monitor display section 3 in the example m has a display power that is eliminated even during the correction operation.The display of the time display section 8 is erased during the correction operation, so there is no waste. Figure 8 shows the voltage level /l/V of the correction signal generated by the correction signal generator in an application example, and the voltage level of the normal signal. Level V
greater than 1 (-), when a correction signal is input to the men's clock 6, the correction signal detection circuit 26 detects this, resets the counter 13, and inputs both the normal and correction signals to the clock input section of the counter 13. Since the reference voltage VB of the comparator 27 is set to satisfy the relationship V 1 <Vs <V2, the correction signal detection circuit 26 detects the output of the flip-flop 28 when the correction signal is sent out. becomes “H” and counter B
is reset, and is input to the clock input section of the counter B via the OR gate 29 and the delay circuit 30 for counting. When the normal signal is input or when the normal signal is sent out, the AND gate 32 is opened by the inverter 31, so the OR gate 29
is input to the clock input section of the counter 13 via the delay circuit 30 and is counted. [Effects of the Invention] As described above, the present invention selects between the normal signal and the correction signal with a small period by switching between the normal signal and the normal signal, and sends out the selected signal via the same signal line. and a time display section driven by the output of a counter that counts the signals, and an instrument that is connected to the signal line and detects when a positive signal is input and resets the counter. It consists of a slave clock equipped with a positive signal detection circuit, and the time display section of the slave clock is corrected by sending a correction signal at the correct signal line. There is no need to set up a start line, and the time on all slave clocks can be easily corrected to match the standard time on the master clock simply by operating the no-correct switch on the master clock, making it easy to adjust the time. This has the effect of being extremely easy to perform.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram of an embodiment of the present invention, a block circuit diagram of the second door 14, and Fig. 3 is a circuit diagram of the dry nozzle (-).
Figures 4 (a) to (d) are the operation time charts, and Figure 5
The figure shows an 8-block circuit diagram of modified example 1 of the corrected signal generating means, and FIGS. Sui Nte 6...
Child clock 7...Signal line 8...Time display section 11
... Minoru Akinaribe of Kuronku... Corrected signal generator... Counter 16... Corrected key signal detection circuit. Patent applicant Matsushita Electric Works Co., Ltd. Patent attorney Toshimaru Takemoto (and 2 others) Figure 3 Figure 5 Figure 6 (d)

Claims (1)

[Claims] (1) A normal signal and a correction signal with a small period are selected by switching a correction switch, and a master clock that sends out the selected signal via the same signal line and the output of a counter that counts the signal are used. The slave clock is equipped with a driven time display section and a correction signal detection circuit that is connected to the signal line and detects when a correction number is input and resets the counter,
A correction device for a magnetically reversible digital sub-clock that corrects a time display section of the sub-clock by sending a correction signal using the correction switch.