JPS59140576A - Pattern converting device - Google Patents

Abstract

PURPOSE:To shorten a time until the completion of layout display processing using reduced characters and to make the device usable for a document editing device having layout display function using reduced characters by providing a reduction converting section and a shift logic section. CONSTITUTION:A pattern converting section 204 related to a reduction converting section that performs reduction conversion of a pattern by a logical sum method, conversion pattern latches 0-2, shown by 205-207 that temporarily store converted patterns by 4-bit at a time, and a shift logic section 208 that shifts 12 bits of converted patterns according to the shift value in a shift value register 202 are provided in a pattern convertor. By this way, time until the completion of layout display processing in reduced characters can be shortened, and the device is usable for a document editing device having layout display function in practical reduced characters.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a pattern conversion device, and is particularly applicable to a document editing device, such as a Japanese word processor, which has functions such as document input, editing, and printing, and in particular, a dot matrix. A pattern conversion device suitable for use in a document editing device, which is equipped with a type character generator and has a function of displaying the layout of a document using characters that are reduced in size from characters made up of dot matrices stored in the character generator. It is related to.

[Prior art]

In general, the above-mentioned document editing devices store information such as characters and symbols input through an input section, a display section that displays created and edited documents, and control programs and already created documents. A printing section prints a completed document on paper, and a control section is comprised of a computer and the like that controls each of the above sections. Its functions can be broadly divided into document input, collection of input documents, and storage and printing of completed documents.

By the way, it goes without saying that it is generally easier to edit and rearrange a created document while checking the layout and balance of the entire document.

Therefore, in conventional document editing devices, in order to check the layout, balance, etc. of the created document, a display device that displays the layout of the entire document page (hereinafter referred to as layout) is used.
Some devices are provided separately from a display device for displaying documents, and others are designed to display the layout on a screen using screen switching means during proofreading of a document collection.

However, in the former case, two display devices are required, one for displaying the document and the other for displaying the layout, which makes the configuration of the display device complicated and expensive. Since the display is displayed on both devices, there is a drawback that editing processing such as correction or replacement of the document becomes slow.

In both the former and the latter, characters are displayed on the layout display screen with substitute symbols such as "☆" or "★" that are far removed from the actual characters. Therefore, the layout display screen allows only the layout of the document to be confirmed.

Particularly in the latter case, in order to check the layout that takes into account the flow and content of the document, it is necessary to frequently switch between the document display screen and the layout display screen, which is a very complicated operation. Moreover, unless the content of the document can be confirmed on the layout display screen, editing processing such as correction and proofreading of the document cannot be performed on the layout display screen. Therefore, even when editing a document while taking the layout into consideration, it is necessary to frequently switch between the document display screen and the layout display screen, and this operation also becomes very complicated.

Therefore, in order to solve the above problems, we have stopped using alternative symbols such as "*" and "★" that were traditionally displayed in place of characters to indicate the position of characters on the layout display screen. By using reduced characters, which are the characters on the document display screen, as layout display characters, the content of the document can be read on the layout display screen, making it easier to check the layout with the content in mind. We attempted to enable editing processes such as correcting or replacing documents on the layout display screen.

Here, FIG. 1 is an external perspective view of a document editing device used in the trial, and FIG. 2 is a block diagram of its control circuit.

That is, the document editing device, as shown in FIG.
A main body 121 that includes a temporary storage section, a display section, and a control section as described later, a keyboard 122 that is an input section, and a printer 124 that is a printing section as shown in FIG.
It consists of a main body 121 and a printer 124.
As shown in FIG. 2, the keyboard 122 transmits and receives control signals and information signals through cables 130 to 131, respectively.

In addition, in FIG. 1, 123 is a CR related to a CRT monitor.
Tl 125 is a flexible disk device (FDD)
That's what it means. ).

In the main body 121, there is a control section 1 within the broken line in the control circuit shown in the block diagram of FIG.
00 is set.

In other words, the program storage type computer unit (hereinafter referred to as CP)
It's called U. ) 301, a Boo FROM 302 consisting of non-volatile memory and having a program executed when the power is turned on;
A program memory 303 that can be read and written at any time to store programs and information for executing functions as a document editing device, and stores dot data representing characters and symbols in a dot matrix as character and symbol codes as indexes. Character generator (hereinafter referred to as CG) 304, C for displaying documents, etc.
A code refresh memory 310 and a dot refresh memory 311, C which can be read and written at any time to store information such as characters to be displayed on the RT123.
Code refresh memo IJ according to the command of PU301
310 j: CG according to the read character code
Read the dot data from 304 or
The dot data is read from the IJ fresh memory 311, converted to a video signal, and sent to the C-T123 along with the synchronization signal.
A flexible disk control circuit (hereinafter referred to as F'DC) 306 that controls the FDD 125 according to commands from the CRT controller 305, CPU 301, and CP
Sends signals to control the printer 124 and print signals to the printer 124 according to commands from U301,
24 from the printer 124
Printer controller 307, CP sending to U301
A key controller 308 that controls the keyboard 122 according to commands from the U301 and sends input signals from the keyboard 122 to the CPU 301, and the CPU 30.
1. Boot ROM 302, program memory 303, code refresh memory IJ 310, CG 304, dot refresh memory 311, CRT controller 30
5, CRT123, FDC306, FDD125, printer controller 307, key human controller 308
The control unit 10 is configured by an internal wiring path 309 that connects the
0 is set.

Here, the Ii'' DD 125 drives a flexible disk, which is a magnetic storage medium, and records information on the flexible disk and reads information from the flexible disk.On the substantially front side of the main body 121, there is a CRT related to the display section. 123 and an FDD 125 related to a temporary storage unit are installed.

For the above trial, the generation of the reduced character pattern as shown in FIG. 5 was completely processed by software using the program shown in the flowchart of FIG. 3. In FIG. 3, 400 relates to a reduced character pattern generation processing section.

That is, the 24×24 dot characters in FIG. 4 are reduced to the 12×12 dot characters in FIG. 5.

The reduced character writing program will now be explained, as it is the same as the one that will be explained in detail in an embodiment of the present invention, and only the necessary contents will be described here. That's it.

In other words, the reduced character writing program
As shown in Figure 3 (, k, j, m, n are constants, generally,
Character pattern D represented by a dot matrix of kmxjn is expressed as D'(x, y)=D(kx,jy)+D(kx+1.j
y)+...10D[k(x+t)-1,jy)+D(k
x, jy+1)-1-...10IXk(X+1)-1,
jV+1] ・・・・・・+D[kx,j (y+1)
-t) ten...+D[k (X+1) -1,j (y
10-1] (where 10 indicates a logical sum), the character pattern is reduced to an mxn character pattern D', and this reduced character pattern is placed in the corresponding position of the layout display memory in the program memory 303. It performs writing processing.

In the case of Figure 4.5 above, each constant in the conversion formula is set to j = k = 2 m = n = 12, and the reduced character writing program having the flow shown in Figure 3 is used. , when displaying the document, the toto<,C in Figure 4
The character pattern displayed in a matrix pattern of 24 x 24 dots on the R, Tl 23 is read out from the CG 304 in two rows at a time, and the character pattern (9) is read out from the CG 304 in the "0" row 401, as illustrated in FIG. 14, which will be described later. 2 dots in the vertical and horizontal directions for 402 on line Il1, a total of 4. (In Figure 4.5.14, the shaded part is logic II 171.) By sequentially converting dots into one dot according to the formula %)), one line of 403 By repeatedly creating a reduced pattern of 1 and writing it to the display memory in the program memory 303, a pattern of 1 as shown in FIG. 5 is displayed on the CRT 123.
It displays reduced characters in a dot matrix pattern of 2 x 12 dots.

However, due to the above, 24×2 as shown in FIG.
In order to reduce a 4 dot character to a 12 x 12 dot character as shown in Fig. 5, the process of converting 4 x 4 dots into 1 dot must be performed 144 times using the algorithm.

(10) In other words, the reduced character ζ turn occurrence portion 400 in Fig. 3
A part of the left side of the horizontal O of the reduced character pattern
Do one row 12 times, then 1.2. ..., 1
Do the same thing for each row, totaling 1
This is done 12 times for two rows.

Furthermore, the pattern written to the dot refresh memory 311 for display is as shown in FIG. 19, which will be described later.
Since the data is shifted between each byte, it is necessary to shift one line of the reduced character pattern in order to write the pattern to the dot refresh memory IJ 311, as shown in the reduced character pattern generation portion 400 in FIG. . This shift processing takes a longer processing time for a general CPU than writing to and reading from a memory or an I10 device.

Due to the repetition of the above-mentioned reduction processing and shift processing, in this trial, it took a long time to complete displaying the layout using reduced characters, resulting in a result that was not suitable for practical use.

(11) Regarding the above-mentioned reduction processing... - softwareization,
In one direction of rows or columns, take the logical sum of two appropriate rows or columns, and add the newly obtained row or column to the above two
A device that obtains a final reduced character pattern by performing two processes: obtaining a reduced pattern reduced in one direction by replacing rows or two columns, and then reducing in the same manner in the remaining directions. has been proposed, but in order to obtain the final reduced character pattern, two reduction processing devices are required, one each in the column and row directions, and the shift processing necessary for writing to the dot refresh memory. Since the method is not equipped with a means, there is a drawback that the processing time required for the CPU to perform the shift processing cannot be shortened.

[Purpose of the invention]

The present invention has been made in view of the above trial results and the drawbacks of the conventional example,
(12) Provision of a pattern conversion device used to shorten the time required to complete layout display processing using reduced characters and provide a document editing device having a function of displaying a layout using reduced characters that can be put to practical use. This is the purpose.

[Summary of the invention]

The key point of the present invention is to implement pattern conversion processing and shift processing in hardware.

The configuration of the pattern conversion device according to the present invention includes a reduction conversion section that performs reduction conversion of the pattern by the logical sum method, and a reduction conversion section that performs reduction conversion of the pattern by the logical sum method, and a reduction conversion section that performs reduction conversion of the pattern by the logical sum method, and a reduction conversion section that performs reduction conversion of the pattern by the logical sum method. It is equipped with a shift logic section for outputting the data.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described with reference to the respective figures.

Here, FIG. 6 is a block diagram of a control circuit in a document editing device using a pattern conversion device according to an embodiment of the present invention, and FIG. 7 is a schematic flowchart of an operation program of the document editing device. 8 is a flowchart showing the input processing in the flowchart of FIG. 7 in more detail, and FIG. 9 is a flowchart showing the editing processing in (13) in the flowchart of FIG. FIG. 10 is a flowchart showing the layout display processing in the flowcharts of FIGS. 8 and 9 in more detail, and FIG. 11 is a flowchart showing the reduced character writing processing in the flowchart of the layout display processing of FIG. Detailed flowchart diagram, Part 1
FIG. 2 is a flowchart showing the layout editing process in FIG. 1O in more detail, FIGS.
FIG. 15 is a block diagram of a pattern converter according to an embodiment of the present invention, FIG. 16 is a detailed configuration diagram of the pattern conversion section, FIG. 17 is a detailed configuration diagram of the shift logic section, and FIG. 18 is an explanatory diagram of the pattern input order, and Fig. 19 is
FIG. 3 is an explanatory diagram of the position of a pattern when displayed.

First, in FIG. 6, parts with the same symbols as those in the previous FIG. 2 indicate parts with equivalent functions, 100A is a control section, 301
A is a program storage type computer unit (hereinafter referred to as CPU), and 312 is a pattern converter related to the pattern conversion device.

Thus, the control section 100A is installed in the main body 121 instead of the control section 1000 shown in FIG. 2 above to form a document editing device as shown in FIG.

According to the input from the CPU 301A, the pattern converter 312 converts the character pattern of 24×24 dots as shown in FIG.
This converts it into a dot character pattern.

That is, inside the main body 121 shown in FIG.
A control unit 100A is installed, which includes components having the same functions as those described in the figures, and an internal wiring path 309 that connects the pattern converters 312.

Next, the overall operation of the document editing device will be explained.

That is, in the configuration described above, when the power is turned on, this device has the flow shown in FIG. A program to be operated as a document editing device is transferred into the program memory 303, and then the operation as a document editing device is started according to the program transferred to the program/ram memory 303 and having a flow as shown in FIG.

Here, the auxiliary function is a general term for a function that aggregates functions such as copying a document on a flexible disk to another flexible disk.

When input processing or editing processing is selected by the work selection input, an input processing program or an editing processing program having a flow as shown in FIG. 8 or 9 is executed.

The document being inputted or edited is processed according to the inputting or editing processing program having the flow shown in Figure 8 or Figure 9 in the program memo IJ 303.
It is displayed on the CRT 123 by a code refresh method using the code refresh memory 310.

Processing instructions (16) associated with inputting and editing characters in the document are input from the keyboard 122 and detected by the CPU 301A via the human key controller 308. C.P.
U30], A writes the character code of the input character to the code refresh memory 310 according to the input, and displays the input character on CR, T123, or writes the character code of the input character to the code refresh memory 310 according to the commanded editing process. Change the character code in "CRT 123" and change the displayed document in "CRT 123". At this time, CPU301A
This also changes the document information in the portion of the program memory 303 where the document information is stored (referred to as a document buffer).

When a layout display command is input from the keyboard 122, the CPU 301
A detects a layout display execution command, and the CPU 30
1A is the first one stored in the program memory 303.
A layout display program with a flow similar to that shown in Figure 0 will now be executed.

When the layout display process starts, the CPU 301A (
17) gives a command to the CRT controller 305 to erase from the C'RT 123 the document display of the code refresh method by the input processing or editing processing program shown in FIGS. Next, the dot refresh memory 311 is initialized so that nothing is displayed on the CRT 123 even if the CPU 301A instructs the CRT controller 305 to display using the dot refresh method.

After this process is completed, the dot refresh memory 31
The contents of dot refresh memory 311 are displayed on CRT 123 by instructing CRT controller 305 to display the contents of dot refresh memory 311 on CRT 123.

Next, the character codes are sequentially read from the document buffer in the program memory 303, and the display position of the character when displaying the layout is calculated by the CPU 301A. A reduced character writing program with a flow similar to
Write the reduced character pattern obtained by converting (18). By repeating this process until the display of the layout for one page is completed, a layout of reduced characters is displayed on the CRT 123.

When the layout display for one page is completed, select whether to perform editing processing on the layout display screen, and when editing processing, press the keyboard 122 in the same way as editing processing on the document display screen using the code refresh method. A summary command is input and the contents of the document buffer are updated.

As shown in FIG. 12, the flow of the program for editing processing is such that the command input from the keyboard 122 corresponds to editing processing, such as character deletion/correction, movement, format change, or document layout change. and performs the following processing. If none of the instructions are met, the process returns to inputting instructions for editing contents and waits for new instructions.

In the case of character deletion, by instructing the deletion range from the keyboard 122, the CPU 301A deletes the corresponding character code in the document buffer and arranges a new character code according to the program (19).

In the case of correction, the CPU 301 indicates the correction range from the keyboard 122 and inputs the characters to be corrected.
A replaces the corresponding character code in the document buffer with a new character code according to the program, and rearranges the character codes in the document buffer.

In the case of movement, by specifying the movement character string range and movement destination from the keyboard 122, the CPU 301A moves the character codes within the document buffer according to the program and rearranges the character codes.

In the case of format change, by instructing a new format from the keyboard 122, the CPU 301A rewrites the format information in the document buffer according to the program.

In the case of a layout change such as opening a frame or setting an input-prohibited area, when an instruction for the new layout is input from the keyboard 122, the CPU 301A rewrites the frame opening information and display-prohibited area information in the document buffer according to the program (20). Ru.

In the manner described above, the character code in the document buffer is rewritten with new document information.

When the editing process is completed in this way, the flow returns to the point where the character display of the layout display program starts, as shown in the flowchart of FIG.
3 Display on top.

When the editing process is finished or when no editing process is to be performed, the layout display continues until the layout display is finished, and in response to an instruction to finish the layout display, the CPU 301A
The CRT controller 305 is instructed to stop displaying using the dot refresh method and displaying using the code refresh method, and returns to the input processing or editing processing program.

Displaying characters on the CR,T 123 in the layout display program having the flow shown in FIG. 10 is performed by executing the reduced character writing program 911 having the flow shown in FIG.

As mentioned earlier, the above-mentioned reduced character writing program converts character turn D, which is generally represented by a km x jn dot matrix as shown in Fig. 13, into D'(x, y) = D (kx, jy) + D (kx+l,
jy) 10−・−10D(k(X+1) −i, jyl+
D(kx, jy+l+...ten D[k(x+1)-1,
jy+1:]...10D[kx, j (y+1
) -t] ten...+D(k(x+l-1,j(y+1
)-D (However, + indicates a logical sum.) According to the algorithm shown by It is something to do.

In this example, each constant in the conversion formula is set to j==2 m=n='12, and the reduced sentence (22
) By the character writing program and pattern converter 312,
When displaying the document, see Figure 4 <CR, T123” 2-24
A character pattern displayed in a matrix pattern of x24 dots is read out from the CG 304 two lines at a time, and the character pattern is divided into 2 dots in the vertical and horizontal directions, 4 in total, as shown in Figure 14.
(As mentioned above, in Figures 4 and 5, the old line parts are referred to as logic II and III.) Due to the sequential nature of converting dots into one dot according to By repeatedly creating a reduced pattern for lines and writing it to the dot refresh memory 311, C
When 12 is shown by hatching in FIG. 19 on RT123.
It displays reduced characters in a dot matrix pattern of X12 dots.

By using a document editing device with the structure and operation described above, it is possible to edit characters on the layout display screen using the conventional single dot matrix pattern without having to separately prepare a dot matrix pattern for characters for the layerer small display (23). Instead of using alternative symbols such as "*" or "★", it is possible to display the characters as readable characters as shown in FIG. 5 above.

Of course, not all character patterns are legible even after reduction conversion according to this embodiment. However, according to experiments, hiragana.

Almost all characters such as katakana and numbers, which have a relatively small area of the diagonal line in the 24x24 dot pattern in Figure 4, can be read with just one character even after reduction conversion, such as "po" and "bo". This is to the extent that it is difficult to distinguish between semi-voiced and voiced characters. However, the probability that these half-voiced and voiced characters will appear in a document is low, and even if they still appear,
It is legible depending on the context of the document.

Furthermore, many of the reduced characters obtained by reducing the size of Kanji characters can be read as just one character, as shown in Figure 5 Ω, based on the font. Considering the fact that the probability of a kanji appearing in a document is 40 to 50 and the above, there are about 70 to 80 characters in a document that can be read even with just one character (24). It can be estimated that Furthermore, in a document after reduction conversion, it is rare that characters that are unreadable on their own appear consecutively, and even if they appear in large numbers, almost all of them can be read depending on the context. Taken together, it can be concluded that the document on the layout display screen according to this example is legible.

Therefore, by displaying the layout of a document using reduced characters that have undergone reduction conversion, it is possible to read the document displayed on the layout display screen, and it is possible to arrange the document according to the content of the document. It becomes possible to perform confirmation.

Since the content of the document is still legible on the layout display screen, editing processes such as correction, insertion, and movement of the document can be performed on the layout display screen using a program with the flow shown in Figures 10 to 12. You will be able to do it with

As described in detail above, by providing a document editing device with the function of displaying the document layout using reduced characters, when creating a document that takes layout into consideration, (25) It is an easy-to-operate system that eliminates the need for complicated processes such as checking the document layout, switching to the document display screen, editing the document, and then switching to the layout display screen again after the editing process is complete to check the layout. Document editing devices will be available.

Next, a pattern converter 312 according to an embodiment of the present invention will be described.

That is, the pattern converter 312 of this embodiment converts the 24×24 dot pattern in FIG. 4 into the 12×12 dot pattern in FIG. Convert to dottohaturn,
And as shown in FIG. 19, the dot refresh memory 311
This is a hardware implementation of the reduced character pattern generation processing section 400 previously described in FIG.

The configuration of this pattern converter 312 is shown in FIG. 15 (26). As shown below.

That is, a transceiver receiver 201 controls the transmission and reception of 1-byte data, and a shift value register 202.24×24 temporarily stores the shift value of the reduced pattern 7.
The pattern launch 203, which temporarily stores 1 byte of the dot pattern, converts the 16-bit 24×24 dot pattern sent from the transceiver receiver 201 and pattern latch 203 into 4 bits, that is, the reduction conversion of the pattern is performed using the logical sum method. The pattern conversion unit 204, which is associated with the reduction conversion unit that performs A shift logic unit 208 that shifts bits according to the shift value in the shift value register 202, and a multiplexer 2 that transmits data shifted and expanded to 24 bits by the shift logic unit 208 in 8-bit units.
09, and tranneur receiver 2011 shift value register 202, pattern latch 203, conversion pattern (2
7) Nlatch (0) 205, (1) 206, (2)
207, an IJ-read/write control unit 210 that generates a control signal for the multiplexer 209, and a main component 200 of a pattern converter 312 for the read/write control unit 210, which is connected to the CPU 30.
The transceiver receiver 201, shift value register 202, pattern latch 203, pattern conversion unit 204, and conversion pattern latch 205(0) are added to the decoder 211 used to indicate selection by 1A.

206(1), 207(2), shift logic section 208,
Internal data buses 220, 221, 223, .
224, 225, 226, 227 and signal lines 222, 23
3,234,235,236°237.

Unfortunately, the transceiver receiver 201 is connected to the data bus 22.
8, the decoder 211 is connected to the CPU data bus 230 in the internal wiring path 309, and the decoder 211 is connected to the CPU address bus 231 in the internal wiring path 309 and the CPU address bus 231 in the internal wiring path 309.
It is connected to the PU control bus 232 by the illustrated signal line.

The configuration of the pattern conversion section 204 is as shown in FIG.

That is, it is composed of OR gates 0° to 03 and exclusive OR gates eo-e3, and the above-mentioned pattern conversion algorithm is realized by OR gates Oo to 03 and pattern latch 203. eo-e3 is for inverting or non-inverting the pattern converted by the OR gates Oo-03, depending on the value of the signal line 222 from the shift value register 202. The output of the exclusive OR gate eo-e3 is the conversion pattern launch (0) 205, conversion pattern latch (
1) 206, conversion pattern latch (2) connected to 207.

The reduced conversion pattern signal (29) after reduction conversion output from the conversion pattern latch (0) 205, conversion pattern latch (1) 206, and conversion pattern latch (2) 207, PO to pH, are transmitted via the internal data bus 225. , which is input to the shift logic section 208.

As shown in FIG. 17, the shift logic section 208 has a configuration including 19 data selectors dSO to d that select 1 bit from 8 bits according to a signal from the shift value register 202.
s18, and its logic is expressed by the following equation.

SO~823 in the formula is the reduced pattern signal, PO-pH
is a reduced conversion pattern signal, SFO to SF2 are signals from the shift value register 202, and 0 is a general representation of the 0 portion.

(30) '(31) In other words, the shift logic unit 208 having two-note logic converts the reduced conversion pattern signals PO to pH into reduced patterns shifted by the values of the signals SFO to SF2 from the shift value register 202. Extended to signal 5o-823.

Note that the reduced pattern signals 819 to 82 also shown in FIG.
3 is always 0 regardless of the values of the signals SFO to SP, 2, and therefore does not require a data selector, and is connected to <GROUND as shown.

The time required for this expansion is only the time required for the signal to pass through the element, and is constant.

The reduced pattern signals SO to S23 after the shift are input to the multiplexer 209 via the internal data bus 226,
Signal line 2 from the read/write/control unit 210 below
In response to a signal sent through 36, each 8 bits are read into CPU 301A through internal data bus 227 and transceiver 201.

Now, by using the pattern converter (32) 312 having the above configuration, the reduced character writing program having the flow shown in FIG. 3 can be simplified as shown in FIG. 11.

According to the flow shown in FIG. 11, the CPU 301
A writes the shift value to the shift direct register 202 to obtain a pattern as shown in FIG. 19 through the data bus 228.

Next, for example, two lines of the character pattern represented by the dot matrix shown in FIG. 4 are read out from the CG 304 and written one byte at a time as shown in FIG. It's crowded.

The pattern written the first time is the pattern latch 203
It is latched into the pattern, and is reduced and converted by OR gates 0o-03 together with the second written pattern, resulting in a 4-bit reduced pattern, which is latched into the conversion pattern latch (0) 205.

Thereafter, the third written pattern, the fourth written pattern, the fifth written pattern, and the sixth written pattern are similarly reduced and converted, and the respective converted pattern latches ( 1) 206, conversion pattern latch (2) Latched in 207.

As a result, 12 bits for one row of the reduced pattern are formed.

Hereinafter, as described above, one line of the reduced pattern is input to the soft logic unit 208, shifted according to the value of the shift value register 202, expanded into an actual write pattern as shown in FIG. 19, and input to the multiplexer 209. be done.

Next, the CPU 301A reads the reduced pattern from the pattern converter 312. When the read signal of the reduced pattern comes from the CPU 301A, the first read signal
The leftmost 1 byte in FIG. 9 is read out, followed by the second and third readings in the order shown. The CPU 301A writes this reduced pattern into the dot reflex memory 311. As a result, one raster of the reduced character pattern is displayed on the CRT 123.

Thereafter, by repeating this operation until the display of one character is completed, one reduced character is displayed on the CRT 123.

As described in detail above, when reducing a pattern represented by a dot matrix, the reduction conversion and shift processing, which take a particularly long processing time, can be implemented in hardware as a pattern converter. The process can be simplified from the process shown in FIG. 3 to the process having the flow shown in FIG. 11, and the processing time can be shortened.

In Zoshi C1 integrated circuit, semi-custom integrated circuit power 1
As each LSI, which has already formed a transistor 7,
If a master slice LSI manufacturing method is used in which aluminum wiring is added to the chip according to customer specifications, each block shown in FIG. 15 is formed by combining transistor groups formed on the master slice chip. There is,
Since it is included in a library for automatic wiring of circuits using a so-called calculator, it has the advantage that it is easy to develop and manufacture integrated circuit masks.

However, when applying this embodiment to a conventional document editing device, there are advantages such as the fact that it can be easily added without changing the conventional hardware configuration, character generator, dot reflex memory, etc. Yes, it is a general purpose item.

Next, FIG. 20 is a block diagram of another embodiment of the shift logic section.

In the figure, 225-1, 226-1, 229-1 are data buses, 250 is a soft clock circuit, 251 is a shift clock signal, and 254 is the shift clock signal 251.
252 is a load signal, and 253 is a 24-bit shift register.

However, the load signal is 25A! ! 'i, at the same time as informing the shift clock circuit 250 of the shift start, the reduction conversion pattern signal PO~ is sent to the 24-bit shift register 253.
This is the signal that loads the pH.

That is, the structure of the shift logic section can be a structure using the illustrated shift register.

When using this configuration, compared to the configuration using the data selector described above, a shift clock signal 254, a load signal 252 for loading the reduced pattern PO-pH to the shift clock circuit 25o1 shift register 253 (36), etc. are required. Yes, shift value SFO~SF2
The time it takes to complete the shift changes depending on the value of , which may complicate the circuit design and control from the CPU 301A.
When configured with LIC, the board area occupied by the circuit is
This embodiment has the advantage of being smaller than the previous embodiment, and in practical terms, the same effects as the previous embodiment can be expected.

Further, as another embodiment of the present invention, in addition to converting a 24 x 24 dot pattern into a 12 x 12 dot pattern, a 32 x 32 dot pattern etc. is converted to 1/2.1/a,
An example of this is a method in which the data is reduced to 1/4, shifted, and outputted, and these also provide the same effect as the previously described embodiment.

Furthermore, the main component 200 shown in FIG.
It is also possible that the If this is made into an LSI, the pattern converter becomes extremely compact (37), but it increases the flexibility of mounting on the board and still has the effect of saving power consumption compared to configuring it with discrete circuits. .

〔Effect of the invention〕

According to the present invention, it is possible to shorten the time required to complete layout display processing using reduced characters, which improves the operability of a conventional document editing device, and further improves the operability of the document editing device. This invention can provide a pattern conversion device that can perform the following functions, and can be said to be an invention with remarkable practical effects.

[Brief explanation of the drawing]

FIG. 1 is an external perspective view of the document editing device used in the trial, and FIG. 2 is a block diagram of its control circuit.
Figure 3 is a flowchart showing the reduction writing process used in the above document editing device, Figure 4 is a 24 x 24 dot character pattern diagram, and Figure 5 is the reduction when the character pattern is reduced. 6 is a block diagram of a control circuit in a document editing bag (38) using a pattern conversion device according to an embodiment of the present invention.
The figure is a schematic flowchart of the operation program of the document editing device, and FIG. 8 is a flowchart showing the input processing in the flowchart of FIG. 7 in more detail.
FIG. 9 shows the editing process in flowchart 1 in FIG. 7 in more detail.
The figure is a flowchart showing the layout display processing in the flowcharts of Figs. 8 and 9 in more detail, and Fig. 11 is the reduced character writing process in the flowchart of the layout display processing of Fig. 1O. A more detailed flowchart, FIG. 12, shows the first
A flowchart showing the layout editing process in Fig. 0 in more detail, Figs. 13 and 14 are explanatory diagrams of the conversion method for character pattern reduction conversion, and Fig. 15 is
A block diagram of a pattern converter according to an embodiment of the present invention, FIG. 16 is a detailed configuration diagram of the pattern conversion section, FIG. 17 is a detailed configuration diagram of the shift logic section, and FIG. 18 is a pattern input A sequential explanatory diagram, FIG. 19, is an explanatory diagram of the position of the pattern at the time of display (39), and FIG. 20 is a configuration diagram according to another embodiment of the shift logic section. 100A...Control unit, 123...CRT, 301A
...Program storage type computer unit, 302...
Kate ROM, 303...Program memory, 304
... Character generator, 305 ... CRT controller, 306 ... Flexible disk device,
307...Printer controller, 308...Key manual controller, 309...Internal wiring path, 310...
...Code refresh memory, 311...Dot refresh memory, 312...Pattern converter, 20
1... Transceiver receiver, 202... Shift value register, 203... Pattern latch, 204...
Pattern conversion unit, 205, 206, 207... Conversion pattern latch (0) to (3), 208... Shift logic unit, 209... Multiplexer, 210... Read/write control unit, 211...・Decoder, Oo
~03...OR gate, eo-e3...exclusive OR gate, dsO~ds18...data selector,
250...Shift clock circuit, 253...24 bit shift register (40) register. Agent Patent attorney Kosaku Fukuda (and 1 other person) (41) Haya 1 Figure 21 tdo 2 Hitsuji 2 Zuho 3 Zuho 6 Mouth ゛8 Meka/θmeho 73rd 74th Meji 17th dso 225d; /226 te τ ta S. (1 tase se (
Person S/4-2 r7 Santa ds+ 1 Se S, sHji 58 <;
ri S, uran・to
Deta 41 dsq ds/6 u・
11 ＋” h・ se S2 j adultery f
No. 1 S/4 Shishitaku yq Ta6 5t7 F'3 , , , Rework: t O C7 - Each one too
Kita Odgun τ゛ T' A S4 ”I & SlI pHX,
S/84 many many 4 each 1
y/8I! Possible
S! ? ``ll shape, S5 t + ri
δI2shi Y 陀、：rago
゛(-Pl) Hs6rH?
S/3 = P6
L P01 2 2ho 73
Mouth No. 79 Beg

Claims (1)

[Scope of Claims] 1. A pattern conversion device that changes a pattern represented by a dot matrix, including a reduction conversion unit that performs pattern reduction conversion using a logical sum method, and a unit that shifts and outputs the reduced pattern. 1. A pattern conversion device comprising a shift logic section. 2. A pattern conversion device according to claim 1, wherein the shift logic section for shifting and outputting the reduced pattern is constituted by a data selector.