JPS59140531A - Clock transmission system - Google Patents

Abstract

PURPOSE:To attain a high-quality clock transmission system even for a high- speed clock, by transmitting an original clock signal as a divided clock signal group consisting of n-number of clock signals which have different phases and n-fold repeat period of the original clock signal and receiving this signal group in parallel to synthesize individual signals. CONSTITUTION:A clock oscillator 1a of a clock transmitting part 1 transmis an original clock signal of a square wave pulses, and the signal 10 is converted to divided clock signals 11 and 12, which have a twice pulse repeating period 2T of a repeating period T of the signal 10 and have a phase difference of the period T, by the combination between an FF1b and NANDs 1 and 2. Signals 11 and 12 are delayed and buffered by different transmission lines and are sent to a receiving part 2. Signals 11 and 12 are inputted to phase adjusters 2a and 2b through buffers and have the delay phase difference corrected to attain divided clock signals 21 and 22 having a phase difference T. Signals 21 and 22 are inputted to an NAND3 to attain a reproduced clock signals 30 having the same pulse repeating period as the signal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to improvements in high speed clock pulse transmission schemes.

(b) Background of the Technology In recent years, with the development of data processing technology, data processing systems have become larger and faster in order to improve their processing capabilities.

A data processing system is normally operated by a synchronization method in which a common clock signal is sent from a clock generation source to the constituent circuits of each part of the system to operate the system.

(e) Prior Art and Problems Traditionally, clock signals are usually distributed from a clock generation source via a coaxial cable or a constant impedance transmission path within a printed wiring board, but these transmission and reception methods The means and the transmission line have errors themselves, and also have a plurality of connection points, and also have dimensions and effects due to temperature changes. In addition, since the clock signal has a pulse-like waveform, it contains harmonic components that are more than 10 times the repetition period, and the harmonic components in particular are attenuated and delayed, causing the shape of the rising edge and falling edge to become blunt before being transmitted. In recent years, the repetition period of the clock signal has been accelerated to less than Ions, and depending on the transmission distance of the clock signal, even with the advantageous features of digital data processing equipped with signal regeneration means, even one signal pulse may disappear. Considering the strict conditions of the clock signal that cannot be tolerated, the transmission line has a problem that the quality level is insufficient for a high speed clock.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned problems caused by a single quality transmission line in the past, by dividing the clock signal into multiple transmission lines for transmission and reception. The present invention aims to provide a transmission means that can obtain a higher quality clock signal using a higher quality transmission path.

(e) Structure of the Invention The object is to provide a data processing system having a clock transmitter and a clock receiver, wherein the clock transmitter has means for generating a clock signal, synchronizes the original clock signal every n repetition periods thereof, and each transmitting means for transmitting a group of n divided clock signals having n times a repetition period with mutually different phases;
A clock transmission system characterized in that it comprises n different transmission paths, and a clock receiving section receives a group of clock signals in parallel, combines them, and reproduces a clock signal having the same period as the original clock signal. This can be achieved by providing.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram of a transmission system according to an embodiment of the present invention, and FIG. 2 is a time chart thereof.

In the figure, 1 is a clock transmitter, 2 is a clock receiver,
1a is a clock oscillator, 1bll''1.T type flip-flop circuit (FF), 2a and 2b are phase adjustment circuits NAND1.2.3 is a NAND circuit and B11
FF is a buffer circuit.

A clock oscillator 1a in the clock transmitter 1 amplifies and shapes a stable high-frequency oscillation waveform normally obtained by a crystal oscillation circuit, and sends out a rectangular wave pulse such as the original clock signal 10 shown in FIG. 2(a). Signal 3 - Signal 10 is a combination of FF and NAND1, which produces two divided clock signals 11 having a repetition period 2T, which is twice the repetition period T of signal 10, and a phase difference of period T.
is converted into signal 12 and output.

Therefore, every other divided clock signal 11 and signal 12 are synchronized with the original clock signal 10. The signals 11 and 12 obtained in this manner are sent to the clock receiving section 2 via different transmission paths. The signals 11 and 12 received via each transmission path are delayed and slowed by the transmission path as in the past, but the signals 11 and 12 received by the divided clock are
．． If the waveform rate of the original clock is 50%, 12 has 25 signals each, so the space 75q6 that can be used to reproduce the mark and the conventional original clock signal 10 are used.
Since it is three times as large as 2X (T+TX0.5) compared to the TxO,5 of Signal waveform reproduction processing can be performed with higher reliability than before. Note that since two different transmission paths are used, the reproduced divided clock signal 11°12 due to the characteristic difference inherent in each transmission path.
The phase difference T between the pre-transmission divided clock signals 11 and 12 is corrected by the phase adjusters 2a and 2b.
By obtaining divided clock signals 21 and 22 having a phase difference equal to , inputting them to NAND 3 and outputting the NAND thereof, a reproduced clock signal 30 having a repetition period T equal to that of the original clock signal 10 can be obtained. In the above example, the number of divisions n is 2 by the combination of FF and NAND1, which is a binary counter.
Similarly, by combining an n-ary counter and n NANDs, TXn is calculated for the repetition period T of the original clock signal 10.
We obtain n divided clocks that have a repetition period of By transmitting the divided clocks in parallel, and synthesizing them using the same method as in the embodiment of the present invention with a clock receiving section having n parallel reception functions, a reproduction signal having a period T equal to that of the original clock signal 10 can be obtained. Needless to say, the clock signal 30 can be obtained.

(g) As described in detail, according to the present invention, a higher quality clock transmission system can be obtained for high-speed clocks, which could not be realized in the past, by using a transmission line and transmitting/receiving circuit of the same quality as the conventional one. Useful.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock transmission system according to an embodiment of the present invention, and FIG. 2 is a time chart thereof. In the figure, 1 is a clock transmitter, 2 is a clock receiver,
1a is a clock oscillator, 1b is a flip-flop circuit,
2a and 2b are phase adjustment circuits, NANDl, 2 and 3 are NAND circuits, and BuFF is a buffer circuit. 71

Claims (1)

[Claims] In a data processing system having a clock transmitter and a clock receiver, the clock transmitter is a means for generating a clock signal, synchronizes the original clock signal every 1] of its repetition period, and synchronizes the original clock signal by n times with mutually different phases. means for transmitting a group of n divided clock signals having a repetition period of
1. A clock transmission method characterized in that the clock receiving section receives a group of clock signals in parallel, synthesizes them, and reproduces a clock signal having the same period as the original clock signal.