JPS59138333A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59138333A
JPS59138333A JP1141583A JP1141583A JPS59138333A JP S59138333 A JPS59138333 A JP S59138333A JP 1141583 A JP1141583 A JP 1141583A JP 1141583 A JP1141583 A JP 1141583A JP S59138333 A JPS59138333 A JP S59138333A
Authority
JP
Japan
Prior art keywords
film
alloy
electrode
gas
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1141583A
Other languages
Japanese (ja)
Other versions
JPH0416952B2 (en
Inventor
Shinichi Ofuji
大藤 晋一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1141583A priority Critical patent/JPS59138333A/en
Publication of JPS59138333A publication Critical patent/JPS59138333A/en
Publication of JPH0416952B2 publication Critical patent/JPH0416952B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce the movable ion concentration in an insulative film substantially by using an alloy selected from two specified groups of metal as a metallic film for electrodes as well as performing high temperature treatment in the atmosphere including H2 gas. CONSTITUTION:An silicon oxide film 2 for isolating elements and an oxide film 3 for gates are formed on a surface of an Si substrate 1. Next, an alloy film 7 made of metals selected from a group consisting of Cr, Mo and M and a group consisting of Ti, Zr, Hf, V, Nb and Ta is formed on said films 2 and 3. Then, this film 7 is coated with a mask material and is subjected to photolithography to form an alloy gate electrode 8. Next, an impurity ion showing the reverse conductivity type to the substrate 1 is implanted with using the electrode 8 as a mask, thereby forming a source region 5 and a drain region 6 for an MOS transistor. Thus the concentration of movable ions in the insulative film is substantially reduced and deterioration of the characteristics caused by movement of the movable ions can be improved.

Description

【発明の詳細な説明】 (座業上の利用分野) 本発明は、電極配線に接する絶縁膜中の口」動イオン密
度ケ低減化した半導体装置の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Use) The present invention relates to a method for manufacturing a semiconductor device in which the density of mobile ions in an insulating film in contact with electrode wiring is reduced.

(従来技術) 近年、半導体装置の内部に累すとその電極・配線とt尚
省度に集積させるために、高融照金属會電極・配線に用
いたいわゆる自己整置式素子形成法が用いら扛るように
なった。?llえはMO8型果槓回路に2ける自己整置
式素子形成法では、尚融点金属のモリブテン(MO)な
どの膜r半導体基板への不純物イオン注入のマスクに用
い、また、その1ま残して電極・配線として利用する。
(Prior art) In recent years, so-called self-aligning element formation methods used for high-melting metal electrodes and wiring have been used to more efficiently integrate electrodes and wiring inside semiconductor devices. I started to get carried away. ? In the self-aligned element formation method for MO8 type circuits, a film such as molybdenum (MO), which is a melting point metal, is used as a mask for impurity ion implantation into the semiconductor substrate, and it is also used as a mask for impurity ion implantation into the semiconductor substrate. Use as electrodes and wiring.

この工程について、MOSトランジスタ部會部上上けで
図面で説明1−る。lす第1図(a)に示すよりに、S
l基板1に素子間分離用Sl酸化膜2盆形成し、さらに
ケート酸化膜3欠形成する。その後第1図(b)に示す
ように、電憔配線用の高融点金楓膜として例えはMOケ
堆槓させ、こ;t”l−写真蝕刻法で加工してケート電
極4ケ形成する。次に、第1図(C)に示すように S
l基板lと反対の伝尋型孕示す不純物イオンンケート*
極4 zマスクにして注入し、MOSトランジスタのソ
ース領域5及びドレイン領域6會形成する。その後、窒
素カスメ囲気中で1000℃佳度葦で加熱して、不純物
の活性化7行なう。
This process will be explained with reference to the drawings at the top of the MOS transistor section. As shown in Figure 1(a), S
Two sil oxide films for element isolation are formed on the l substrate 1, and three oxide films are further formed on the substrate 1. Thereafter, as shown in FIG. 1(b), a high melting point gold maple film for electroplated wiring, for example MO, is deposited and processed by photolithography to form four gate electrodes. .Next, as shown in Figure 1(C), S
Impurity ion cation that shows the transmission type opposite to the l substrate l *
A source region 5 and a drain region 6 of a MOS transistor are formed by implanting the electrode 4 using a Z mask. Thereafter, impurities are activated by heating at 1000° C. with reeds in a nitrogen atmosphere.

この工程では、ソース直載5及びトレイン鎖酸6へのイ
オン注入に対しでケート電極4tマスクにして目己整会
させでいる/こめ、不純物拡散領域と′開極配線との画
像付わせの/ζめの目会わせずfLに対する余裕葡必賛
としない。使って、素十の占める面積が減少し、眠られ
たペレット面積V」によジ多くの累す音形成することが
口」能となる。
In this process, the gate electrode 4t mask is used to align the ion implantation into the source directly mounted 5 and the train chain acid 6. In addition, the images of the impurity diffusion region and the opening wiring are aligned. / ζ will not be forced to praise fL without seeing it. As a result, the area occupied by the prime is reduced, and the area occupied by the pellet (V) is increased to form a larger number of sounds.

この目己整曾式素子形成法を用いる場合には、ケート電
極となる薄膜か、注入さtしる不純物イオンに対してマ
スクとして作用し、なお・〃・つ1000 C極度1て
の加熱に耐える性質7餉えていることが心安である。M
(JS型果集積路では、このよりなり−ト電極・自1線
として、従来から不純物添加多結晶S1が用いられてき
た。しかし、その比抵抗が約5 X 10−’Ω−a1
以上と高いため、電極・配線の微細構造化により配置部
分の抵抗が増大し、この抵抗増大に起因した信号の伝搬
遅延が問題となつtさた。このため、最近では、不純物
添加多結晶5iLV)比抵抗か約2恰低いMO等の高融
点金属ケケート電極・配線に用いる技術が注目さtして
さている。例えばMOでは、結晶粒径もより小さいため
微細加工か口」能であり、−!た、原子査号が42でバ
ルクの密度が10.21/cm−3と太きいため、イオ
ン注入に対する阻止能力も高い。
When this self-aligned element formation method is used, the thin film serving as the gate electrode acts as a mask for the impurity ions to be implanted, and is heated to an extreme of 1000 C. It is reassuring to know that you have the 7 qualities of endurance. M
(In the JS type integrated circuit, impurity-doped polycrystalline S1 has traditionally been used as this twisted electrode/self-wire. However, its specific resistance is about 5 x 10-'Ω-a1
As a result, the resistance of the arrangement portion increases due to the finer structure of electrodes and wiring, and signal propagation delay due to this increase in resistance becomes a problem. For this reason, recently, the technology used for electrodes and wiring made of high-melting point metals such as MO, which has a specific resistance of impurity-doped polycrystalline 5iLV), which is about 2 times lower, has been attracting attention. For example, in MO, the crystal grain size is smaller, so microfabrication is possible, and -! In addition, since the atomic code is 42 and the bulk density is as large as 10.21/cm-3, the blocking ability against ion implantation is also high.

しかし、実際にMOケ電極・配線に用りで14OSトラ
ンジスタケ製作すると、そのしさい値電圧か長期間の使
用で変動する現象が収態δれる。
However, when a 14OS transistor is actually manufactured for use in MO electrodes and wiring, the phenomenon that the threshold voltage fluctuates over a long period of use subsides.

この現象は、特VCバイアス一温度加速試験全行な9と
しきい値電圧の負方向への変動として顕著に現わ扛る。
This phenomenon manifests itself conspicuously as a negative change in the threshold voltage during all VC bias temperature acceleration tests.

一般l/civi OS型集槓回路に′s?けるIVI
U S トランジスタのしきい1ilI%、圧の安定性
は、業績回路のイ1゛頼性上、最も1要な問題でるり、
上記の変動は許容さ扛ない。このしきい値電圧の変動の
原因については、多くの研究が行なゎ7ムて2シ、主に
Na等のアル刀り金属のイオンがケート酸化膜中で#動
することに因ることが知らγしている。ま1こ、こγし
らの可動イオンは、当初ゲー)′i4物の金属中に不純
物とじで言有さrして′s?ジ、さらに製危工糊中での
金践電極衣面の汚染も加わり1こrしらが筒温熱処理等
の工程でケート酸化膜中に拡散・侵入″Tるものと考え
らγしている。
General l/civi OS type integrated circuit's? IVI
The threshold 1ilI% and pressure stability of U.S. transistors are the most important issues in terms of the reliability of the performance circuit.
The above variations are not tolerated. Many studies have been conducted on the cause of this threshold voltage fluctuation, and it is mainly due to the movement of ions of alkali metals such as Na in the oxide film. I don't know. These mobile ions were initially created as impurities in the metal. Furthermore, with the addition of contamination on the surface of the metal electrode in the manufacturing process paste, it is thought that some of the metal may have diffused and invaded the oxide film during processes such as tube temperature heat treatment. .

ゲートm化膜中の可動イオンの低減については、従来、
棟々の方法かψを究ざ1してきた。第1の方法は、ケー
ト酸化膜中にリン(P)全尋人し、PVCよるNaのケ
ツタリンク効果全オリ用してNaケケート絞化膜甲に固
定しようとするものである。この場合は、バターニンタ
し1cゲート電極上VCP人りシリケード・ガラスケ堆
槓させ、その俊の熱処理によシシリケート・カラス中の
Pケ−ト酸化膜厚へ拡散させる方法が一般的に取ら7し
ている。この方法では、Pc/)4人を熱拡散で行な′
)罠め、その導入鎖板をケート酸化膜中に正確に限定・
制御すること1l−i各局でない。
Regarding the reduction of mobile ions in the gated film, conventionally,
I have been trying to figure out ψ using various methods. The first method involves placing all the phosphorus (P) in the oxide film and fixing it on the oxide film insulating the phosphorus (P) by utilizing the linking effect of Na caused by PVC. In this case, the general method is to deposit the VCP-containing silicate glass on the 1c gate electrode by butter nintering, and then diffuse it into the P-cate oxide film in the silicate glass through a quick heat treatment. There is. In this method, Pc/)4 people are carried out by thermal diffusion.
) to trap and precisely confine its introduced chain plate into the catenate oxide film.
It is not possible to control 1l-i each station.

特に、尚化度化した1vlo s型半導体装置では、ケ
ート酸化膜厚が300^以下と薄くなるため、P拡散の
制御は一段と困難になる。
In particular, in the case of a 1VLO S type semiconductor device which has become more stable, the thickness of the gate oxide film becomes as thin as 300^ or less, making it even more difficult to control P diffusion.

第2の方法には、石川等やヤナガワ等が蒸着法で形成し
たMO電極について報告している尚温水素処理法がめる
( l(、■shikawa、 M、 Yamamot
o。
The second method includes the still-temperature hydrogen treatment method reported by Ishikawa et al. and Yanagawa et al. for MO electrodes formed by vapor deposition.
o.

H,Tokunaga、 N、 Toyokura、 
F、 Yanagawa。
H, Tokunaga, N, Toyokura,
F. Yanagawa.

K、 Kiuchi、 and M、 KOndO: 
IEEE ’l’rans。
K., Kiuchi, and M., KOndO:
IEEE 'l'rans.

Electron Devices、 Vol、 ED
−27,pp、 1586〜1590.198U、 、
 F、 Y’anagawa、 K、 1(iuchi
Electron Devices, Vol, ED
-27, pp, 1586-1590.198U, ,
F, Y'anagawa, K, 1 (iuchi
.

T、 l−1osoya、 T、 Tsuchiya、
T、 Amazawa、 andT−fVlano :
 IEEE ’l’rans、 Electron ]
)evices。
T, l-1osoya, T, Tsuchiya,
T, Amazawa, and T-fVlano:
IEEE 'l'rans, Electron]
)evices.

Vol、 ED−27,pp、 1602〜1606.
1980)。この方法では、バターコンタ後のぬゲート
電惚勿H2−1’J+(10%−90チ)混合カス中で
1000℃の熱処理ケ行な′)か、または、N2力ス中
T100O℃との熱処理を行なった後に、引@続いてN
2  N2混台ガス中で1000℃の熱処理企行なう。
Vol, ED-27, pp, 1602-1606.
1980). In this method, heat treatment is performed at 1000°C in a mixture of slag (H2-1'J+ (10% - 90%)) after butter contouring, or heat treatment is performed at T100°C in a N2 atmosphere. After doing , pull@ followed by N
2 Heat treatment at 1000°C in N2 mixed gas is planned.

その結果、ケートま化膜中の可動イオン照度は、lO〜
lOの程度に1で減少する。し力)し、この方法ケスバ
ッタMO膜に応用した場合には、スパッタ金属膜中の不
純物1a度が蒸看膜に比べて高いため、この熱処理によ
るriJ勤イオン密度の低減効果たけでは不十分である
。スパッタリングでMO膜會堆槓ちせる場合には、スパ
ッタ用のArガスにH2ガスを6≦加すると、Hll−
N2混会ガス中での熱処理時のb」動イオンの秋少がδ
らに強まることが知ら才している(特願昭57−140
955)。たたし、この場合には、1000℃程度の高
温熱処理盆必要とし、900℃では依然として10 ′
。cm−2程度の密度の可動イオンが検出芒れる。
As a result, the mobile ion illuminance in the categorized film is 1O~
It decreases by 1 to the extent of lO. However, when this method is applied to a sputtered MO film, the degree of impurity in the sputtered metal film is higher than that in a vaporized film, so the effect of reducing the riJ ion density by this heat treatment alone is not sufficient. be. When depositing an MO film by sputtering, adding 6≦H2 gas to Ar gas for sputtering results in Hll-
During heat treatment in N2 mixed gas, the fall of b'-mobile ions is δ.
It is known that it will become even stronger.
955). However, in this case, a high temperature heat treatment tray of about 1000°C is required, and at 900°C the temperature is still 10'.
. Mobile ions with a density of about cm-2 can be detected.

一方、ケート電極用尚融点金属1俣については、可動イ
オンの問題に限らす独々の特性改善のために他の全域を
添加する技術が@削されている。
On the other hand, with regard to one block of melting point metal for a cathode electrode, techniques for adding other areas in other areas have been developed in order to improve the unique characteristics limited to the problem of mobile ions.

例えはMOについては、テタ7 (Ti ) yz 2
〜15Wt、%混入させる方法が知らγしている(特公
昭55−35868)。
For example, for MO, Teta 7 (Ti) yz 2
A method of mixing up to 15 Wt% is known (Japanese Patent Publication No. 35868/1983).

この場合、膜堰Ijy、vこは鰺板會部分的にTi板で
被4’JtL7j分割陰極板rスパッタリング方法が主
に用いらrしてい/)。この方法によrしは、MO膜に
比べて基板との接着力が増し、基板温度ケ600℃以上
に高めることなしに、割γし及びにか7L(/Jない膜
を歩@り艮く堆積できる。し27ムレ、こtしらの方法
による可動イオン密度の数置については、報告さnてい
ない。
In this case, the membrane weir Ijy,v is partially covered with a Ti plate, and the sputtering method is mainly used. With this method, the adhesion to the substrate is increased compared to the MO film. However, the numerical value of the mobile ion density by these methods has not been reported.

(発明の目的) 本発明は上記の欠点全改善するために提案さtLlc 
4 (7) r、可jllJ−1オン!Pj度忙低減せ
しめた半導体装置の製造方法を提供すること?目的とす
るものである。
(Objective of the Invention) The present invention is proposed to improve all the above-mentioned drawbacks.
4 (7) r, possible jllJ-1 on! To provide a method for manufacturing a semiconductor device that reduces PJ time. This is the purpose.

(発明の栴Pt) 上記の目的全達成するため、本発明は半導体基板表面に
絶縁膜足形成する工程と、眩絶縁膜上に、クロム、モリ
ブテン、タングステンから成る群から選択でγした金塊
と、チタン、ジルコニウム、ハフニウム、バナジウム、
二号フ、タンタルから成る群から選択さ1した金塊との
混会した膜−1−たに台金膜勿形成丁不工程と、該混什
した膜または該公金膜會パターニングして1kL極・配
線ケ形成″Tる工程と、水素ガスを含む雰囲気中で高温
熱処理上行なう工程とを含むこと奮特歎とづ−る半導体
装置の製造方法を発明の妥旨とするものである。
(Pt of the invention) In order to achieve all of the above objects, the present invention includes a step of forming an insulating film foot on the surface of a semiconductor substrate, and a gamma gold ingot selected from the group consisting of chromium, molybdenum, and tungsten on the glare insulating film. , titanium, zirconium, hafnium, vanadium,
No. 2, a mixed film with a gold ingot selected from the group consisting of tantalum - 1 - The mixed film or the public gold film is patterned to form a 1kL electrode. - The gist of the invention is a method for manufacturing a semiconductor device which includes a step of forming wiring and a step of performing high-temperature heat treatment in an atmosphere containing hydrogen gas.

次に不発明の実施例を趨性図面について説明″j″る。Next, an embodiment of the invention will be explained with reference to a trend drawing.

l寂実施例は一つの例示であって、+5b明の梢神を逸
脱しない範囲で、柚々の哀史めるいは改良を行いうるこ
とは百うまでもない。
The Jaku example is just one example, and it goes without saying that Yuzu's sorrow or improvement can be made without departing from the +5b bright Kozue God.

第2図は、不発明によるIVfO8型半導体装置のケー
ト電極部の製造工@説明図で、工&費朗に′J=−ける
MO8型半導体装置の表部の断面形状ケ示している。ま
す、第2区(a)に示すようにSi基板1の表面に素子
間分離用Si眩化腺2およびケート酸化膜3を形成する
。本発明では、次の第2図(b)に示す工程が従来と異
なる。すなわち、従来ではlo−3〜10−2’[or
r程度の圧力のArガス昼四囲気中高融点金塊の例えば
MO−zスパッタリンク1−7)か、lたは、〜10−
 ”l’orr @度の圧力の真空中でMo 7z電子
ビーム蒸庸法で蒸着してケート11L極用のMO膜を形
成した。本発明では、この代わりに7.5 x 10 
” Torrの圧力のArガス雰囲気中でMOメタ−ッ
ト及びTa(タンク/I/)ターゲットを同時にスパッ
タし、Th f 7 at、%含む厚さ3300AのM
OとTaの公金ケート電極膜7七堆槓させる。たたし、
スパッタリング中の基板加熱(例えば700℃以上)を
十分に行なわない場合には、この時点でのMOとTaと
の会雀化は不十分で概ねMOとTaの混会した膜となっ
ている。しがし、後に行なう尚温熱処理により、合金化
さnる。
FIG. 2 is an explanatory drawing of the gate electrode portion of the IVfO8 type semiconductor device according to the invention, and shows the cross-sectional shape of the surface of the MO8 type semiconductor device according to the invention. First, as shown in the second section (a), a Si blinding gland 2 for element isolation and a catoxide film 3 are formed on the surface of the Si substrate 1. In the present invention, the following process shown in FIG. 2(b) is different from the conventional process. That is, conventionally lo-3 to 10-2' [or
For example, MO-z sputter link 1-7) or ~10-
The MO film for the cathode 11L electrode was formed by depositing Mo 7z electron beam evaporation in a vacuum at a pressure of 7.5 x 10
” MO metal and Ta (tank/I/) targets were simultaneously sputtered in an Ar gas atmosphere at a pressure of Torr, and a 3300A thick M
A public metal electrode film 7 of O and Ta is deposited. Tatashi,
If the substrate is not sufficiently heated (for example, to 700° C. or higher) during sputtering, the combination of MO and Ta is insufficient at this point, and the film is generally a mixture of MO and Ta. However, it is alloyed by the subsequent still-temperature heat treatment.

本笑施例では、便宜上、堆積直後の膜も公金膜と呼ぶも
のとする。この例では、膜堆積にスパッタ法を用いたが
、電子ビーム蒸着法音用いても良い。また、ターゲット
または蒸着源にMOとTaO会金公金いることも可能で
ある。芒らに、こnらの方法では、腺堆@’tArガス
雰囲気中または真空中で行っているが、こ′tLらの雰
囲気にH2ガス?]l−亦加しても艮い。?llえはス
パッタ法では、ルガスの分圧k 2 x 10 ’−1
0−’ Torr 8度とする。このルガスの硲加は、
後に示アように、本発明の効果ケさらに高めるf’t−
用を有している。
In this example, for convenience, the film immediately after deposition will also be referred to as a public gold film. In this example, sputtering was used for film deposition, but electron beam evaporation may also be used. It is also possible to use MO and TaO metals as the target or the deposition source. In addition, these methods are carried out in an Ar gas atmosphere or in a vacuum, but is there H2 gas in the atmosphere? ]l-It doesn't matter if you add it. ? In the sputtering method, the partial pressure of gas is k 2 x 10'-1
0-' Torr shall be 8 degrees. The name of this Lugas is
As shown later, f't-
I have something to do.

また、本実施のごとく、電極の低抵抗化に江目して、主
体となる金塊として比抵抗の低いMO(バルク比抵抗5
.3XlO−’Ω−crn)全用艷、添加金属として比
較的比抵抗の高いTh(バルク比抵抗1.3XlO−5
Ω−ffl)?r用いる組付ソの場合には、添加するT
aの濃度としては、熱処理後の公金膜比抵抗全lX1O
−’Ω−a以下とするために1Oat、%以下とするの
が望ましい。
In addition, as in this implementation, with the aim of lowering the resistance of the electrode, MO with low resistivity (bulk resistivity 5
.. Th (bulk resistivity 1.3XlO-5) has a relatively high resistivity as an additive metal.
Ω-ffl)? In the case of an assembly machine using r, add T.
The concentration of a is the total resistivity of the public gold film after heat treatment lX1O
-'Ω-a or less, it is desirable to set it to 1 Oat, % or less.

この後は、従来工程と同様に第2図(C)に示すように
合金ケート電極膜7の上に@接ホトレジスト等のマスク
拐料を塗布し、写真蝕刻法で加工して合金ゲート電極8
を形成する。次に第2図(d)に示すように、31基板
1と反対の伝導型を示す不純物イオンを合金ゲート電極
8をマスクにして注入し、MOSトランジスタのソース
領域5及びドレイン領域6を形成する。
After this, as in the conventional process, as shown in FIG. 2(C), a masking material such as @photoresist is applied onto the alloy gate electrode film 7, and processed by photolithography to form the alloy gate electrode 8.
form. Next, as shown in FIG. 2(d), impurity ions having a conductivity type opposite to that of the substrate 1 are implanted using the alloy gate electrode 8 as a mask to form a source region 5 and a drain region 6 of the MOS transistor. .

本発明では、この後の工程も従来と異なる。In the present invention, the subsequent steps are also different from the conventional method.

すなわち、従来は、ソース・ドレイン領域に注入した不
純物を活性化するために、N2ガス雰囲気中で1000
℃程度の熱処理會行なった。し刀・し、本発明では、こ
の熱処理k N2ガスを含む雰囲気中で行なう。例えは
、N2ガス全10%、N2ガスを90チ官むl気圧のN
2− N2混合ガス中で1oooc。
That is, conventionally, in order to activate impurities implanted into the source/drain regions, 1,000 ml of impurity was applied in an N2 gas atmosphere.
A heat treatment session was carried out at a temperature of about ℃. However, in the present invention, this heat treatment is performed in an atmosphere containing N2 gas. For example, if the total N2 gas is 10%, then 90 parts of N2 gas is added to 1 atm of N.
2- 1oooc in N2 mixed gas.

30分間、加熱する。また、この熱処理は、はじめにN
2ガス雰囲気中で1000℃の熱処理を行ない、引@絖
いてN2− Nx混合ガス雰囲気中で1000℃の熱処
理を行なっても良い。たたし、熱処理温度は、700℃
以上の高温全装する。
Heat for 30 minutes. In addition, this heat treatment is performed first with N
Heat treatment at 1000° C. may be performed in a two-gas atmosphere, followed by heat treatment at 1000° C. in an N2-Nx mixed gas atmosphere. The heat treatment temperature is 700℃.
Fully loaded at higher temperatures.

以上説明したように、不発明では、電極用金属膜として
、特定の2つの金属群から選は′nた合金を用い、かつ
、N2ガスを含む雰囲気中で高温熱処理全行なうことケ
基本的な特徴としている。
As explained above, the basic principle of the invention is to use an alloy selected from two specific metal groups as the metal film for the electrode, and to conduct all high-temperature heat treatment in an atmosphere containing N2 gas. It is a feature.

次に、本実施例に基つき製作したMOSキャパシタの可
動イオンv2度の特性について、図面を用いて説明する
。第3図は、本実施例で示した工程音用いてp型Si基
板上にケート酸化膜犀が40OA、スパッタ法で堆積し
たゲート電極の形状が500pm月のMOSキャパシタ
を形成し、そのi」動イオン![Nrll−TVS法(
TriangularVoltage Sweep M
ethod ) f用いて測定した結果七本す。横軸は
、電極形成後に行なったN2− N2混合ガス中での熱
処理温度を示す。縦軸は、ゲート酸化膜中の可動イオン
密度Nm’に示す。図中のMO″は、従来技術によシス
ノ(ツタ1ノンク゛で形成したMOゲート!極の試料を
示す。” Mo −Ta”は、本発明によるMOとTa
の合金ゲート電極の試料上水し、” N2− Mo −
Ta ”は、DJloとTaの付会ケート魁&膜形成用
スノくツタガス(Ar:分圧7.5 X 10−” T
orr )にH2ガスf分圧が2 X 1O−3Tor
rとなるように添7JI して製作した試料上水す。従
来の珈ゲート電極では、熱処理温度が1000℃の場合
vc+可動イオン@度Nmは10”crn−2程度ケ示
す。こ1しに比べて、本発明によるMO−Taゲート電
極では、900℃でも10 ” cm−”程度と小aく
、さらに1000℃では、I X 10”+1ff−”
以下となる。さらにHz  Mo−Taゲート電極では
、可動イオン密度猶の減少はより顕著となp、900℃
でも検出されない程度となる。こ扛らの結果から、MO
へのTal7)添加、さらにはスノ(ツタガス中への迅
ガスの添力0は、L−N2混合ガス中での熱処理Vこよ
る可動イオン密度Nmの低減効果音ざらに促進すること
が確かめろt′L′fc0 以上の実施例で示したように、従来のN2ガス會含む雰
囲気中での熱処理に加えて、本発明のごとくゲート電極
に合金膜を用い、さらには電極膜の形成ケルガス會會む
雰囲気中で行なうことによシ、比較的高純朋化の困難な
高融点金属膜全ゲート電極とするMO8型半導体装置に
於ても、ケート酸化膜中の可動イオン密度21x10−
” cvr−”以下の検出限界程度まで低減させること
が可能であることが明らかになった。
Next, the mobile ion v2 degree characteristics of the MOS capacitor manufactured based on this example will be explained using the drawings. FIG. 3 shows that a MOS capacitor with a gate electrode shape of 500 pm was formed by depositing a gate electrode of 40 OA on a p-type Si substrate by sputtering using the process steps shown in this example. Moving ions! [Nrll-TVS method (
Triangular Voltage Sweep M
There are seven results measured using method) f. The horizontal axis indicates the temperature of heat treatment in N2-N2 mixed gas performed after electrode formation. The vertical axis represents the mobile ion density Nm' in the gate oxide film. In the figure, "MO" indicates a sample of an MO gate! pole formed using a conventional technique.
A sample of the alloy gate electrode of "N2-Mo-
Ta" is DJlo and Ta's companion Kate Kai & film formation snow ivy gas (Ar: partial pressure 7.5 x 10-"T
orr ), the H2 gas f partial pressure is 2 X 1O-3 Torr
Sample tap water was prepared by adding 7JI so that r. In the conventional C gate electrode, when the heat treatment temperature is 1000°C, vc + mobile ion @ degree Nm is about 10" crn-2. Compared to this, with the MO-Ta gate electrode according to the present invention, even at 900°C It has a small a of about 10"cm-", and furthermore, at 1000℃, I x 10"+1ff-"
The following is true. Furthermore, for the Hz Mo-Ta gate electrode, the decrease in mobile ion density is even more pronounced at p, 900°C.
However, it remains undetectable. From these results, MO
It should be confirmed that the addition of Tal7) to the Ivy gas, as well as the addition of 0 gas to the Ivy gas, greatly promotes the reduction of the mobile ion density Nm due to the heat treatment V in the L-N2 mixed gas. 'L'fc0 As shown in the above examples, in addition to the conventional heat treatment in an atmosphere containing N2 gas, an alloy film is used for the gate electrode as in the present invention, and furthermore, an electrode film formation process is performed using a gas atmosphere. By performing this in an atmosphere of
It has become clear that it is possible to reduce the detection limit to below "cvr-".

本実施例では、ゲート電極にMO−Ta合金を用いたが
、この合金の組@−せには、高融点金属の中でも比較的
比抵抗が低くかつ室温での)Lt7!/スの吸収量が少
ないCr(クロム)、MOlW(タングステン)から成
る第1の抑の金属と、比較的比抵抗が高くかつ室温での
N2ガスの吸収量が多い’l’i (チタン)、Zr 
<ジルコニウム)、1(f(ハフニウム)、■(バナジ
クムン、Nb(ニオブ)、Taから成る第2の群の金属
と力Sら適宜選択することが(例えばTaとWなどン可
能である。こ扛により、第1の群の金属の優rt、た電
気伝導性を著しく損なうことなく Hzガスの吸収性能
上^めて、)12−N、混合ガス中熱処理時の可動イオ
ン密度Nmの低減効果全促進することがF」能でるる。
In this example, an MO-Ta alloy was used for the gate electrode, but this alloy has a relatively low resistivity among high melting point metals and has a relatively low resistivity (at room temperature) of Lt7! The first suppressive metal consists of Cr (chromium) and MOLW (tungsten), which absorb a small amount of nitrogen gas, and 'l'i (titanium), which has a relatively high resistivity and a large absorption amount of N2 gas at room temperature. ,Zr
<zirconium), 1 (f (hafnium), ■ (vanadium), Nb (niobium), Ta and S (for example, Ta and W) can be selected as appropriate. The effect of reducing the mobile ion density Nm during heat treatment in a mixed gas of 12-N and 12-N, without significantly impairing the electrical conductivity of the metals of the first group. It is possible to promote all.

なお、本実施例ではMOS型の半導体装置ケ取り上けた
が、ゲート絶縁膜はSiの酸化物に限定さtしることな
く、一般のM I S (Metal−Jnsular
or−8emiconductor )型半導体装置に
対して本発明を用いることかできる。また、MIS型半
導体装置に限らす、例えばバイポーラ型半導体装置等の
パシベーション用絶縁膜にも本発明を用いることができ
るのは明らかである。
Although this embodiment deals with a MOS type semiconductor device, the gate insulating film is not limited to Si oxide, and may be made of general MIS (Metal-Jnsular).
The present invention can be applied to semiconductor devices of the type (or-8 semiconductor). Furthermore, it is clear that the present invention can be used not only for MIS type semiconductor devices but also for passivation insulating films for bipolar type semiconductor devices and the like.

(発明の効果) 以上説明したように、本発明によγLは、半導体装置の
絶縁膜上の電極・配線を、Cr1M0IWから成る解か
ら選択した金員とTi 、 zr 、 1−4t 。
(Effects of the Invention) As explained above, according to the present invention, γL is made of metal selected from a solution consisting of Cr1M0IW, Ti, zr, and 1-4t for electrodes and wiring on an insulating film of a semiconductor device.

V 、 Nb 、 ’l’aから成る群から選択した金
員との合金で構成し、かつ、この合金電極を水素ガスを
含む雰囲気中で高温熱処理すれば、上記絶縁膜中に含ま
nる可動イオン密度全大幅に低減させることができる。
If the electrode is made of an alloy with a metal selected from the group consisting of V, Nb, and 'l'a, and this alloy electrode is heat-treated at high temperature in an atmosphere containing hydrogen gas, the movable material contained in the insulating film can be removed. The total ion density can be significantly reduced.

従って、このようにしで製作した半導体装置に於いては
、バイアス一温度加速試験時に見らj’Lる可動イオン
の移動に起因した特性劣化は著しく改善される。よって
、本発明は、半導体装置の細粗性を著しく向上させる効
果を有するものである。
Therefore, in the semiconductor device manufactured in this manner, the characteristic deterioration caused by the movement of mobile ions observed during the bias-temperature acceleration test is significantly improved. Therefore, the present invention has the effect of significantly improving the fineness of a semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(c)は従来のMOSトランジスタの製
造工程全説明するための要部拡大断面図、第2図(a)
〜(d)は本発明によるMO8型半導体装置の製造工程
全説明するための要部拡大断面図、第3図ばH2−N2
混合ガス中での熱処理温度と可動イオン密度との関係を
示す特性図でるる。 l・・・・・・・・・Si基板 2・・・・・・・・・素子間分離用si[化膜3・・・
・・・・・・ケート酸化膜 4・・・・・・・・・ゲート電極 5・・・・・・・・・ソース領域 6・・・・・・・・・ドレイン領域 7・・・・・・・・・合金ケート電極膜8・・・・・・
・・・含金ゲート電極 !+!f許出願人 日本電信電話公社 第1図 6 第2図 第3図 900 1000
Figures 1 (a) to (c) are enlarged sectional views of main parts for explaining the entire manufacturing process of a conventional MOS transistor, and Figure 2 (a)
~(d) are enlarged sectional views of essential parts for explaining the entire manufacturing process of the MO8 type semiconductor device according to the present invention, and FIG. 3 is a H2-N2
This is a characteristic diagram showing the relationship between heat treatment temperature and mobile ion density in a mixed gas. l...Si substrate 2... Si [chemical film 3...] for isolation between elements...
......Cate oxide film 4...Gate electrode 5...Source region 6...Drain region 7... ...Alloy cate electrode film 8...
...Gold-containing gate electrode! +! f Applicant Nippon Telegraph and Telephone Public Corporation Figure 1 6 Figure 2 Figure 3 900 1000

Claims (2)

【特許請求の範囲】[Claims] (1) 半導体基板六面に絶縁膜全形成する工程と、該
絶縁膜上に、クロム、モリブテン、タンクステン刀≧ら
成る群から選択さ扛′fc金属と、チタン。 ジルコニクム、ハフニウム、バナジウム、ニオブ、タン
タル刀)ら成る群から選択さlした金属との混合した族
lたは会金農勿形■する工性と、呟混会“した膜または
該合金膜tバターニングして電極・配置を形成する工程
と、水累カスr會む暮囲気中で尚温熱処理ケ行なう工程
と葡會むことケ%徴とする半導体装置の製造方法。
(1) A step of forming an insulating film on all six sides of the semiconductor substrate, and coating a metal selected from the group consisting of chromium, molybdenum, tank stainless steel, and titanium on the insulating film. A film mixed with a metal selected from the group consisting of zirconium, hafnium, vanadium, niobium, and tantalum, or an alloy film of the same type. A method for manufacturing a semiconductor device, which includes a step of patterning to form electrodes and arrangements, a step of performing still-temperature heat treatment in a dark atmosphere in which water deposits are present, and a step of forming an electrode/arrangement.
(2)混合した族または合金膜を形成する工程ケ水累ガ
スr包む雰囲気中で行なりこと勿特徴とする特許請求の
範囲第1.!Jtに記載の半導体装置の製造方法。
(2) The process of forming the mixed family or alloy film is carried out in an atmosphere containing aqueous gas. ! A method for manufacturing a semiconductor device according to Jt.
JP1141583A 1983-01-28 1983-01-28 Manufacture of semiconductor device Granted JPS59138333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1141583A JPS59138333A (en) 1983-01-28 1983-01-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1141583A JPS59138333A (en) 1983-01-28 1983-01-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59138333A true JPS59138333A (en) 1984-08-08
JPH0416952B2 JPH0416952B2 (en) 1992-03-25

Family

ID=11777406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1141583A Granted JPS59138333A (en) 1983-01-28 1983-01-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59138333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281621A (en) * 1989-03-22 1990-11-19 American Teleph & Telegr Co <Att> Semiconductor device and method of forming the same, apparatus for metal deposition and manufacture of metal source

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5481082A (en) * 1977-12-12 1979-06-28 Fujitsu Ltd Manufacture of semiconductor
JPS5535868A (en) * 1978-09-05 1980-03-13 Matsushita Electric Ind Co Ltd Humidity controlling method for air conditioner

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5481082A (en) * 1977-12-12 1979-06-28 Fujitsu Ltd Manufacture of semiconductor
JPS5535868A (en) * 1978-09-05 1980-03-13 Matsushita Electric Ind Co Ltd Humidity controlling method for air conditioner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281621A (en) * 1989-03-22 1990-11-19 American Teleph & Telegr Co <Att> Semiconductor device and method of forming the same, apparatus for metal deposition and manufacture of metal source

Also Published As

Publication number Publication date
JPH0416952B2 (en) 1992-03-25

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