JPS59135945A - Digital pll method - Google Patents

Abstract

PURPOSE:To eliminate a pilot signal from a demodulating signal by operating a PLL by a phase error signal between a stereo pilot signal and a timing pulse. CONSTITUTION:A timing pulse PT at time intervals of 1/fs (fs=76kHz) is formed from an output of a digital variable frequency divider 11, and outputs converting 7 digitally an FM stereo composite signal in the timing of the pulse PT are assumed sequentially as DA(i-1), DB(i-1), DC(i-1), DD(i-1), DAi, DBi, DCi, DDi, DA(i+1), DB(i+1),..., then the PSN value expressed as PSN=DAN-DBN- DCN+DDN is calculated 8 at each 4/fs period (where; N is ..., (i-2), (i-1), i, (i+1),...). The PLL is operated by using the PSN value as a phase error signal between the stereo pilot signal and the pulse PT in the composite signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to a digital PLL, especially in an FM stereo receiver, which detects a signal synchronized with a stereo pilot signal in an FM detection signal (stereo composite signal) and a stereo signal from a stereo composite signal. The present invention relates to a digital PLL square for outputting a cancellation level for removing a pilot signal.

Conventional Structure and Problems Conventionally, the analog I)LL system has been commonly used as a method for generating a stereo demodulation timing signal synchronized with a stereo pilot signal.

FIG. 1 shows an overview of FM stereo demodulation using an analog PLL system. (1λ is a phase comparator, and the input signal is the stereo composite signal cs2. Figure (6) shows the stereo pilot signal (frequency ls kllz ) which is a part of the stereo composite signal)] and the switching signal [Fig. (0), and the stereo composite signal when the switching signal is at the H level is used as a phase error signal. (2) is a loop filter, and the phase error signal of the output of the phase comparator (1) is used as the phase error signal by the VCO (described later). (3) is a magnetic pressure controlled oscillator (hereinafter referred to as vCO) whose output frequency is controlled by the VCO control voltage output from the loop filter (2). The output waveform of is shown in Figure 2.

The fundamental frequency of the output signal of the VCO (3) is determined when the PLL circuit shown in Fig. 1 is synchronized, that is, when the phase relationship between the stereo pilot signal in the stereo composite signal and the switching signal is as shown in Fig. 2 (b). (Relationship shown in 0 [
761 & (=19 times 4).

In addition, in Fig. 1, (4) is the first frequency dividing circuit that divides the output frequency of V CO (3) by 2, and the first frequency dividing circuit when the PLL circuit in Fig. 1 is synchronized. The output of the circuit (4) has a fundamental frequency of 8 as shown in FIG. 2 (6).

(1)) is a stereo demodulation circuit that converts one stereo composite word (Figure 2 (6) shows the signal waveform obtained by removing the stereo pilot signal components 1-11f from the stereo composite signal) into the left channel and right channel. It demodulates audio signals. In other words, if the signal shown in Figure 2 (6) is used to switch the signal shown in Figure 2 (G)), the left channel audio signal will be changed to the left channel audio signal, and the signal shown in Figure 2 (T) will be changed to the signal shown in Figure 2 (T). ), the right channel audio signals are demodulated. (6)
The output of the first frequency divider circuit (4) is divided by two again to obtain the result shown in Figure 2 (
As shown in Q, this is a @2 frequency divider circuit that outputs a switching signal with a fundamental frequency of 19 seconds, and this second frequency divider circuit (6)
The output (sign) is applied as a switching signal to the phase comparator (1).

Note that, as described above, each waveform in FIG.
(3) shows a state in synchronization with the stereo composite signal.

As explained above, conventional timing signals for pm stereo demodulation are generated using an analog PLL, and have not been converted to a digital PLL.

On the other hand, various proposals regarding digital PLL have been made, but these generally consider the input signal to be a single signal [if the input signal is not a single signal, the signal is filtered before input to generate a single signal]. ], 1? There is no such method that directly uses an M stereo composite signal as an input signal of a digital PLL and synchronizes it with a stereo pilot signal, which is one signal in this composite signal.

Purpose of the Invention The present invention provides the analog PL in FM stereo demodulation.
It is an object of the present invention to provide a digital PLL method that can digitally perform the same operation as L.

Furthermore, the present invention provides a digital PLL that can also remove a stereo pilot signal from a stereo demodulated signal.

The purpose is to provide a method.

Structure of the Invention The digital PLL method of the present invention generates a timing pulse PT with a time interval of 1/1 sus≠76 from the output of a digital variable frequency divider, and digitally converts an FM stereo composite signal at the timing of this timing pulse PT. The outputs are sequentially...DA(1-1)+Dn(
+-+), Dc(+-t), DDC+-1>#D
AD, DBI, Dct, DDI, I) h<++
1>.

When DB(++1)..., PSN = DAN DBN DCN +DLIN
However, N is...g (i-2)+ (1-1)l l
# A PSN value of (++1)+... is calculated every 4/fs period, and this PSN value is used as a phase error signal between the stereo pilot signal in the FM stereo composite signal and the timing pulse FT for phase synchronization. It is characterized by operating a loop.

In addition, the digital PLL method according to the present invention is based on the digital variable portion L'';I I'l, : 1/fs (fs
≠76 klt,), and generate a timing pulse P1 with a time interval of 76 klt, and at the timing of this timing pulse P1,
The output of the digitally converted stereo composite signal is sequentially...1) A (i-t), D++ (i-1)
, Dc(+-t), Do(t-t), DA,, D
BI, Dct, Dpi.

I) A(ilIL I)n(ilD, ``'' When 1P SN = DAN 1) BN DCN
+ DDN However, N is...* (+-2L (+-
The PSN value of +L il (++t)+... is 4/fs
The PSN value is calculated for each cycle, and the phase-locked loop is operated using this PSN value as the stereo pilot signal phase error signal in the FM stereo composite signal.
The LPN value is calculated, and the LPN value obtained by integrating the LPN value is set as the stereo pilot signal level to be removed from the stereo composite signal.

DESCRIPTION OF EMBODIMENTS The digital PLL method of the present invention will be described below based on a specific embodiment.

FIG. 3 shows a configuration diagram of a digital PLL circuit.

(7) converts the stereo composite signal as an input signal to 1/f using the variable frequency division '/=E Ql11 output, which will be described later.
An analog-to-digital converter (hereinafter referred to as ADC) samples and holds it at a period of s (here, fs = 76) JIZ) and converts it into digital data. (8) is an addition/subtraction circuit, and the output of ADC (7) DA(i
-1), DB(+-1)* DC(1-1)+DD(
+ ri+ DAD, I)13+, DC+, DDl
v DA(il1)+ DB(1+1)*...When bound, PSN=DAN DBN DCN+DDNHowever, i
: integer, N;...a (+-1)* in (1+1
)... is calculated at a cycle of 47 fs.

(9) is a processing circuit that uses the PSN value of the output of adder/subtractor circuit (8) as an input signal and processes it according to the flowchart in Figure 5 to determine the division ratio described later, and ao is a fixed frequency that outputs a signal with a frequency of N-fs. The oscillator ao is a variable division divider which divides the output of the fixed frequency oscillator aQ by a division ratio N, (N+I) or (N-IX) determined by the output of the processing circuit (9).

Note that the addition/subtraction circuit (8), processing circuit (9), etc. can be integrated by using a signal processor, but here they are explained separately by pot function.

In addition, when the digital PLL is synchronized with a phase error of "zero", DAIII of the output of the ADC (7),
DBN, DCN.

Of the DDNs, DAN and DCN have left channel audio signal components and pilot signal components, and DBN and DDN have right channel audio signal components and pilot signal components. Therefore, the DAN, DBN, DCN,
If the pilot signal component is removed from the DDN, the left side.

Only the right channel audio signal component is present.

Next, before explaining the flowchart of FIG. 5, the reason why such processing is necessary will be explained.

The stereo composite signal Sc is expressed by the following equation.

5c=(L+R) +l"5ina+pt+(L-R
) (LIS-tL: Left channel A! channel audio signal, R: Right channel audio number, P: Pilot signal amplitude, ωP
: Pa・f4tsu1-signal angular frequency, here 2πX19
1 &, o) s' subcarrier angular frequency, here 2π
There are 88 songs. Here, focusing only on the pilot signal Sp represented by p-5inω,・t, DAN'
e DBN'e DCN' e DDN',
8π 5π 7π Ilot signal sp is ω2・t=7. Assuming that the signal sampled and held at the timings 〒, T, 〒 is converted into a digital value, PSN' = DSI'DBN'DCN' + DDN
'= 0. Further, if the phase conversion value of the deviation from the above timing of sampling is Δθ, the relationship between PSN' and Δθ is as shown in FIG. That is, the digital P in FIG.
When LL is synchronized with the pilot signal in the input signal in the phase relationship described above, the 19th song pilot signal component equivalent value PSN' in the PSN value becomes zero, and the phase is advanced (Δθ〉0). When PSN'<0.

When the phase is delayed (Δθ<0), P SN'>
It becomes O. On the other hand, the input of the digital PLL (1
Since it is not only a pilot signal but a stereo composite signal, the phase lead or lag can be determined using PSN.
'We have no choice but to use the PSN value instead of the value.

The flowchart in FIG. 1455 shows a process in which the influence of signal components other than the pilot signal power in the stereo composite signal can be seen in the above determination.

Next, the flowchart of FIG. 5 will be explained in detail.

Initialize the variable splitter (lυ and processing circuit (9) with (a-1) and (a-2) (N=No, Np =NH=O
a PSUM = 0) Data DAN, 1) BN, DCN updated once every 4/fs after L/
From DDN, calculate PSN″DAN-DIIN +DCN DDN (a-3) L, the size of the PSN value as (a-4:) and (a
-5,1 is determined. When the psN value satisfies K+ <PSN <Kl, the frequency division ratio N of the variable divider αυ is set to No.
Set (a-6:) and wait for the next data update.

In (a''4) and (a-5), the magnitude of the PSUM value is determined by (b-2) and (c-2), respectively, if PSN>Kle PSN<, Ks.

If PSUM>K3 is satisfied in (b-2), then set the division ratio N to N. Set to -1 (b-8) L/, P S
UM value s Np value.

N, initialize the value (a-2) and wait for the next data update.

In addition, if (c-2) satisfies P sum < -K3, then set the division ratio N to NO+1 set (C-a
) L/, initial setting (a-2) L/ waits for the next data update. (b-2)) In (c-2), PSUM riKs e PSUM', in the case of ``2-3, respectively (b-4), (c-4) XuNp';
2 N (#NN > N
). Also, in (b 4) and (c-4), NP≧N
(*If NH≧Nc is satisfied, Npe NN* N
(and from Kf, calculate (d-1) , determine the magnitude of the binary value calculated in (d-2), (d-8). In (d-2), P S
If UM > K2 is satisfied, Ps in (d-8)
If UM < − satisfies 2, then (
Execute b-8) and (c-8), and -2<PsUM:
< If K2, set branch ratio N to No (d-4)
Then, initialization (a-2) is executed in the same way as when executing (ba) and (1:c-8).

Note that N(, Kl p K2 + K
3 is zero or a positive constant.

As described above, the processing circuit (9) calculates the number of times (Np or NN) that PSN>Kl or PSN<-4.
At the same time, the PSN value when the above conditions are satisfied is calculated as P SUM, and this PSUM value is PSU
If M > K3 or PsUM < -3, then
Regardless of the NP and NN values, set the division ratio N of the variable divider Oυ to N=No-1 or N=No+1 to advance or delay the phase of the digital ■CO output signal, and -3 to <PSUM≦3 to In the case of , when either the NP value or the NN value reaches a certain value Nc, calculate the binary value, and when P SUM > Kz, advance the digital vCO output phase as N=No-1. and when PSUM < -2, N =
As No+1, control is performed to delay the output phase of the digital ■CO.

In this way, by processing the PSN and setting the division ratio of the variable splitter αυ, it is possible to remove interference caused by signal components other than the pilot signal in the stereo composite signal, and to eliminate periodic phase errors, which are no problem in practice. (within a range where a sufficient degree of stereo separation can be obtained).

Note that the constant value Kl * Kl * K2' * x2
/ l K3 s-6 value respectively Kl + Al+
Kl +Al e K2'10A2 e K2'10A
As they say, 2 slgs 10 A3- K3+
By offsetting the constant value AI, A2-Aar, the 19kHz pilot and Gaishital VC
The phase of the O output can be offset from the predetermined phase and synchronized, and this can be used for the degree of separation F[ during stereo demodulation.

Also, in addition 1g jl-times iri <s), DA
N, DBN, DCN, DDN value, LPN"" 1JAN+DBN DCN DDN is also calculated every 4/fs, and this LPN value is sent to the processing circuit (9).
By performing integration processing on the 61st;;l such that ;1<
It can also be used as a pilot signal component level to be removed from DCN and DDN, and as a stereo/monaural discrimination signal of received radio waves. Ns is a constant value [subdivision constant]
It is. Furthermore, K1 p K2' * k3 + A)
By changing the *A2* At value etc. in proportion to the LPM value, it is also possible to eliminate variations in the synchronization state of the digital PLL (variations in the phase error range) due to variations in the sensitivity of the FM detection circuit.

As described in the detailed description of the invention, according to the digital PLL method of the present invention, the output of the digitally converted stereo composite signal is processed to set the frequency division ratio of the variable divider, so periodic phase errors are virtually eliminated. It can be within a range without any problems.

Further, since the LPN value is calculated every 4/fS period and the LPM value obtained by integrating this value is used as the level of the pilot signal component to be removed, the stereo pilot signal can also be removed from the stereo demodulated signal.

As described above, the present invention is very effective when complex digital processing circuits, analog/digital converters, digital/analog converters, etc. can be manufactured at low cost due to advances in semiconductor technology.

[Brief explanation of the drawing]

Figure 1 shows PL for pilot signal synchronization using analog method.
L circuit configuration diagram, Figure 2 is a waveform diagram explaining the operation of Figure 1, Figure 8
The figure is a digital PLL circuit configuration diagram of a specific embodiment of the digital PLL method according to the present invention, FIG. 4 is a diagram illustrating the operating principle of FIG. 8, and 5L'1. FIG. 6 is a flow chart of the main part of FIG. 8, respectively. ('7)...Analog-to-digital converter, (8)...
...addition/subtraction circuit, (9)...processing circuit, excitation...fixed frequency oscillator, 0υ...variable splitter agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. 1/fs (fs≠
A timing pulse PT with a time interval of 76kl(i) is generated, and the output of the FM stereo composite signal that is digitally converted at the timing of this timing pulse FT is sequentially converted to s-DA(t-1), DB(i-D, Dc(+) -x)
, Do(t-D, DAi, DBt, Dc+. Dog, DA(++1), DBC++1), ”'
°”6, PSN = DAN DBN - Ash N 1000 N However, N is...# (+・-2), (t-
B, +, (++t), ..., PSN value is 4/f
A digital PLL method in which a PSN value is calculated every s period and is used as a phase error signal between a stereo pilot signal in the FM stereo composite signal and the timing pulse PT to operate a phase locked loop. 2. 1/fs (fs≠
Create a timing pulse FT with a time interval of c7st),
At the timing of this timing pulse PT, the FM stereo composite signal is digitally converted and the output is sequentially converted by 1°.
°°DA(1-1), DB(t-t), DC(1-
1), DD(1-1), DAI, DBI. DCi, DDi, DA(++1), DB(++1
)* "' means 1PSN" DAN DBN
DCN + DBN However, N is..., (+-2
), (i-1), i, (++1)... are calculated every 4/fs period, and this PSN value is calculated by combining the stereo pilot signal in the FM stereo composite signal and the timing pulse PT. When operating a phase-locked loop as a phase error signal between. Together, every 4/fs period, LPN ” DAN +DBN DCN DDNO
A digital PLL method in which an LPN value is calculated and an LPλ electric value obtained by integrating the LPN value is used as a stereo pilot signal level to be removed from a stereo composite signal. 8. Phase locked loop, PSN > K1 or P5N
<-K. (However, K1 is zero or a positive constant value).Assume that the number of times NF or NN is satisfied and the above conditions are satisfied is P.
Accumulate the SN values to obtain the PiSUM value, then calculate the NP value or NN value.
When one of the values reaches the constant value formula, 2=(Tamatuto)・K5 Nc However, ■(2 is zero or positive constant value)
When the 1'SUM value satisfies the condition of PSUN > K2, the phase of the digital variable frequency divider output forming a part of L is advanced, and PSUM < -
3. The digital PLL method according to claim 1, wherein the phase is controlled to be delayed at 7 o'clock when the condition of K2 is satisfied. 4. Set the phase of the digital variable frequency divider output to the NP value NN
The value is related to t, i, <P value is PSUM> K3
(However, K3 is a positive constant value larger than 2) The control is performed to proceed to a platform that satisfies the condition, and to delay when the condition PSUM < -K3 is satisfied. 2. Digital PLL method according to item 2. 5. The phase relationship between the FM stereo composite signal and the timing pulse PT is expressed as K1* K1* K2*
3 m to K2 * K3 value to 1 +
AI r K1 + Alm K2. /+ A2 e
K2. + A2 e K3 +A3 m K3+ A
s (However, A2 = 苧)AG, Al e As
e A3 is a positive or negative constant value, respectively),
Claim 1, characterized in that the degree of stereo separation is adjusted by offsetting I + A2 * A3.
Digital PL as described in Items 2, 8, and 4
L method. 6. The digital PLL method according to claim 2, wherein the LPN value is used as a stereo/monaural discrimination signal. ? , Kl r K≦t K3 m AH* A2
The digital PLL method according to claims 2, 8, 4, and 5, characterized in that constant values such as +A3 are set in proportion to the LPM value.