JPS59135090U - GTO gate circuit - Google Patents
GTO gate circuitInfo
- Publication number
- JPS59135090U JPS59135090U JP2843983U JP2843983U JPS59135090U JP S59135090 U JPS59135090 U JP S59135090U JP 2843983 U JP2843983 U JP 2843983U JP 2843983 U JP2843983 U JP 2843983U JP S59135090 U JPS59135090 U JP S59135090U
- Authority
- JP
- Japan
- Prior art keywords
- gto
- gate
- circuit
- voltage
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
- Protection Of Static Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のゲート回路の一例を示す回路図、第2図
aは第1図に示されるGTOのアノード電流を示す波形
図、第2図すは第1図に示されるGTOのゲート電流を
示す波形図、第3図は第1図のゲート回路を備えたGT
Oを構成した場合の波形図であり、同図aはアノード・
カソード間電圧を示す波形図、同図すはアノード電流を
示す波形図、同図Cはゲートオン電流を示す波形図、同
図dは同図Cのゲートオン電流を常時供給した場合の波
形図、第4図は本考案に係るGTOのゲート回路の一実
施例を示す回路図、第5図中aは第4図に示す回路図、
第5図中aは第4間電圧を示す波形図、第5図中すは第
4図に示されるGTOのアノード電流を示す波形図、第
5図中Cは第4図に示されるGTOのゲートオン電流を
示す波形図である。
GTO・・・ゲート・ターンオフ・サイリスタ、T、。
T2・・・トランジスタ、■F・・・電流供給回路、T
3・・・トランジスタ、E□、E2・・・直流電源、C
・・・コンデンサ、SN・・・スナバ回路、DS・・・
ダイオード、C3・・・ダイオード、MT・・・監視回
路、VS・・・電圧検出回路、CMP・・・コンパレー
タ。
RTl
−E1−巳 C工
丁−丁
E2↓二 ?
2
゛第2図
に
第4図Figure 1 is a circuit diagram showing an example of a conventional gate circuit, Figure 2a is a waveform diagram showing the anode current of the GTO shown in Figure 1, and Figure 2 is the gate current of the GTO shown in Figure 1. Figure 3 is a waveform diagram showing the GT equipped with the gate circuit shown in Figure 1.
This is a waveform diagram when O is configured, and a in the figure is an anode
A waveform diagram showing the cathode voltage, a waveform diagram showing the anode current, a waveform diagram showing the gate-on current, and a waveform diagram showing the gate-on current of C in the diagram. 4 is a circuit diagram showing an embodiment of the gate circuit of the GTO according to the present invention, a in FIG. 5 is a circuit diagram shown in FIG. 4,
In FIG. 5, a is a waveform diagram showing the voltage across the 4th line, A in FIG. 5 is a waveform diagram showing the anode current of the GTO shown in FIG. 4, and C in FIG. FIG. 3 is a waveform diagram showing gate-on current. GTO...Gate turn-off thyristor, T. T2...transistor, ■F...current supply circuit, T
3...Transistor, E□, E2...DC power supply, C
...Capacitor, SN...Snubber circuit, DS...
Diode, C3...Diode, MT...Monitoring circuit, VS...Voltage detection circuit, CMP...Comparator. RTl -E1-Snake C-King-DingE2↓2? 2 ゛Figure 2 and Figure 4
Claims (3)
、GTOのアノード・カソード間の電圧状態を監視する
手段と、該監視手段による監視結果に応じて定常時にゲ
ートオン電流が供給されるゲートに所要のパルス状電流
を加算的に供給し得る手段とを備えたことを特徴とする
GTOのゲート回路。(1) In a GTO gate circuit equipped with a snubber circuit, there is a means for monitoring the voltage state between the anode and cathode of the GTO, and a gate-on current is supplied to the gate in a steady state according to the monitoring result by the monitoring means. 1. A gate circuit for a GTO, comprising means for additively supplying a pulsed current.
もしくはGTOのアノード・カソード間電圧を検出する
電圧検出回路と、該電圧検出回路の電圧検出出力に応じ
た値とGTOをターンオンさせるのに適当な所定の電圧
レベルと比較し、前記検出出力に応じた値が前記電圧レ
ベルに達したら前記電流供給手段へ指令を発するコンパ
レータとからなることを特徴とする実用新案登録請求の
範囲第1項記載のGTOのゲート回路。(2) The monitoring means includes a voltage detection circuit that detects the snubber capacitor voltage of the snubber circuit or the voltage between the anode and cathode of the GTO, and a value corresponding to the voltage detection output of the voltage detection circuit and a value suitable for turning on the GTO. The utility model according to claim 1, further comprising a comparator that compares the voltage level with a predetermined voltage level and issues a command to the current supply means when a value corresponding to the detected output reaches the voltage level. GTO gate circuit.
よりONとなるトランジスタから構成され、GTOのゲ
ートへ定常的なゲート電流を供給するトランジスタにO
N状態で所要のパルス状電流を加算するように接続きれ
ていることを特徴とする実用新案登録請求の範囲第2項
記載のGTOのゲート回路。(3) The current supply means is composed of a transistor that is turned on in response to a command from the comparator, and is turned on to the transistor that supplies a steady gate current to the gate of the GTO.
A gate circuit for a GTO according to claim 2, characterized in that the gate circuit is connected so as to add a required pulsed current in the N state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2843983U JPS59135090U (en) | 1983-02-28 | 1983-02-28 | GTO gate circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2843983U JPS59135090U (en) | 1983-02-28 | 1983-02-28 | GTO gate circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59135090U true JPS59135090U (en) | 1984-09-10 |
JPH0424787Y2 JPH0424787Y2 (en) | 1992-06-11 |
Family
ID=30159327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2843983U Granted JPS59135090U (en) | 1983-02-28 | 1983-02-28 | GTO gate circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59135090U (en) |
-
1983
- 1983-02-28 JP JP2843983U patent/JPS59135090U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0424787Y2 (en) | 1992-06-11 |
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