JPS59134835U - Division arithmetic device using memory elements - Google Patents

Division arithmetic device using memory elements

Info

Publication number
JPS59134835U
JPS59134835U JP2963583U JP2963583U JPS59134835U JP S59134835 U JPS59134835 U JP S59134835U JP 2963583 U JP2963583 U JP 2963583U JP 2963583 U JP2963583 U JP 2963583U JP S59134835 U JPS59134835 U JP S59134835U
Authority
JP
Japan
Prior art keywords
digit
value
switching circuit
address
selection number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2963583U
Other languages
Japanese (ja)
Other versions
JPH021624Y2 (en
Inventor
冨家 文穂
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2963583U priority Critical patent/JPS59134835U/en
Publication of JPS59134835U publication Critical patent/JPS59134835U/en
Application granted granted Critical
Publication of JPH021624Y2 publication Critical patent/JPH021624Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による除算演算装置の実施例を示すブロ
ック図である。 A・・・除算演算の被除数、1. 2. 3. 4・・
・記憶素子、5・・・BCD加算器、7・・・アキュム
レータ、8・・・制御回路、9・・・桁選択番号、10
・・・被除数の2つの桁の値。
FIG. 1 is a block diagram showing an embodiment of a division arithmetic device according to the present invention. A: Dividend of division operation, 1. 2. 3. 4...
・Storage element, 5... BCD adder, 7... Accumulator, 8... Control circuit, 9... Digit selection number, 10
...The value of the two digits of the dividend.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被除数の各桁の値を複数のアドレス指定端子に割り振り
する桁切替回路と、前記アドレス指定端子対応毎に設け
られ、アドレス番号で示される値に対応した値すべてに
ついて一定の値で除した値を記憶している記憶素子群と
、加算器と、累算器と、桁選択番号を供給することによ
り前記桁切替回路にその桁選択番号に対応する被除数の
桁の値を前記記憶素子群に供給させ、この桁の値と桁選
択番号とにより生成される前記記憶素子群のアドレスに
格納されている値を読出させ、この読出した値と前記累
算器の値とを前記加算器によって加算させ、以上の動作
を前記桁切替回路に順次供給する桁選択番号毎に繰り返
えさせ、前記加算器出力を前記累算器に累算させるよう
に制御する制御回路とから構成した記憶素子を用いた除
算演算装置。
A digit switching circuit that allocates the value of each digit of the dividend to a plurality of address designating terminals, and a digit switching circuit that is provided for each address designation terminal and calculates the value obtained by dividing all the values corresponding to the value indicated by the address number by a constant value. By supplying the stored memory element group, an adder, an accumulator, and a digit selection number, the value of the digit of the dividend corresponding to the digit selection number is supplied to the memory element group to the digit switching circuit. the value stored in the address of the storage element group generated by the value of this digit and the digit selection number, and the read value and the value of the accumulator are added by the adder. and a control circuit that controls the above operations to be repeated for each digit selection number sequentially supplied to the digit switching circuit and to cause the accumulator to accumulate the output of the adder. division arithmetic device.
JP2963583U 1983-03-01 1983-03-01 Division arithmetic device using memory elements Granted JPS59134835U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2963583U JPS59134835U (en) 1983-03-01 1983-03-01 Division arithmetic device using memory elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2963583U JPS59134835U (en) 1983-03-01 1983-03-01 Division arithmetic device using memory elements

Publications (2)

Publication Number Publication Date
JPS59134835U true JPS59134835U (en) 1984-09-08
JPH021624Y2 JPH021624Y2 (en) 1990-01-16

Family

ID=30160496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2963583U Granted JPS59134835U (en) 1983-03-01 1983-03-01 Division arithmetic device using memory elements

Country Status (1)

Country Link
JP (1) JPS59134835U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942182A (en) * 1972-04-27 1974-04-20
JPS5270727A (en) * 1975-12-10 1977-06-13 Fujitsu Ltd Computation system
JPS5299030A (en) * 1976-02-17 1977-08-19 Yokogawa Hokushin Electric Corp Dividing operation circuit with constant divisor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942182A (en) * 1972-04-27 1974-04-20
JPS5270727A (en) * 1975-12-10 1977-06-13 Fujitsu Ltd Computation system
JPS5299030A (en) * 1976-02-17 1977-08-19 Yokogawa Hokushin Electric Corp Dividing operation circuit with constant divisor

Also Published As

Publication number Publication date
JPH021624Y2 (en) 1990-01-16

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