JPS59133746A - Level control circuit of analog waveform - Google Patents

Abstract

PURPOSE:To simplify the comparison and control of level without using a level meter by using an analog multiplexer at an input part. CONSTITUTION:An analog multiplexer 1 covers the emitter voltage and the drain voltage and is controlled by a switch part 2. The switch part 2 controls also a multiplexer 21. Both the signal to be measured and the basic wave input of the multiplexer 21 are selected, and a level control circuit itself is controlled and checked when the basic wave is selected. The analog waveform passed through filter 11 is supplied to an effective value/DC level converter 3, and the signal converted by the converter 3 is supplied to a comparator 6. For the other input of the comparator 6, the maximum and minimum outputs are applied if the values outside the maximum and minimum standard range are obtained through comparison with the maximum and minimum standards of the signal to be measured. Otherwise an output within the standard is applied to the other input of the comparator 6 if the value within the standard is obtained through the comparison. These outputs are displayed at a display part 8 respectively.

Description

TECHNICAL FIELD The present invention relates to an analog waveform level adjustment circuit, and more particularly to a signal transmission level measurement and adjustment circuit in facsimile transmission.

Prior Art Conventionally, when adjusting the sending level of facsimile signals,
Adjustments are made using a level meter, but using a level meter just for level/I/adjustment is a big loss because it requires extra cost and space.
Furthermore, since the level meter may not have been calibrated, accurate adjustment may not be possible.

Purpose An object of the present invention is to provide a low-cost, small-capacity analog waveform level adjustment circuit that can be easily compared and adjusted without using a level meter, in order to eliminate such drawbacks.

composition Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 1 is a block diagram of a level adjustment circuit showing an embodiment of the present invention.

In FIG. 1, 9 is a circuit to be adjusted, and an amplifier 91
and a variable resistor 92 which is an adjustment point. The signal level is extracted from the mark (3) and input to the level adjustment circuit of the present invention. In the level adjustment circuit, 1 is an analog multiplexer, 11 is a filter, 21 is an analog multiplexer, 2 is a switch section, 3 is an analog effective value/DC level converter, 41 is a maximum value set circuit, and 42 is a minimum value set circuit, 5 is a digital/analog converter, 6 is a comparator,
7 is a logic circuit, and 8 is a display section.

Analog multiplexer 1 in the input section uses C"MOS transistors, and the input range is emitter voltage ■
. and drain voltage ■DD (-15 to 5V). The analog multiplexer I is controlled by the switch section 2, which selects another channel except when used for measurement, and its input section is pulled down. The switch unit 2 also controls the multiplexer 1 and the multiplexer 21 after passing through the filter 11 at the subsequent stage. The multiplexer 21 after the filter 11 selects the input of the signal under test and the input of the fundamental wave.The fundamental wave is selected when used for adjusting and checking the circuit itself. In other words, when making internal adjustments,
When checking the internal circuit, turn on the standard adjustment switch to input the fundamental wave (standard signal). Then, by pressing the check 't4 start switch, checking becomes possible, and by pressing it again, checking is canceled. The filter 11 forms an active high-pass filter, and for example, the frequency band of the carrier wave used for facsimile +J is 1800H,
It has a center frequency nearby.

The analog waveform passed through the filter 11 is input to the effective value/DC level converter 3, where the effective value of the analog waveform is converted to a DC level.

The signal converted to the DC level is input to the comparator 6 at the next stage. The other input of the comparator 6 is the maximum specification and minimum specification values of the signal under test, and these values are set digitally. The value set with digital 8 bits is
The signals are weighted by the next-stage D/A converter 5 and input to the comparator 6 as the maximum and minimum levels, respectively.

In the comparator 6, if the comparison result is outside the standard range for the maximum and minimum levels, the respective outputs are higher than the maximum (Y, =
A) or less than or equal to the minimum (Y, -B). Furthermore, if it is within the standard, an output indicating that it is within the standard is given based on the logical formula Y6=A-B. Note that A represents the maximum value or more, and B represents the minimum value or less.

These outputs are displayed on the display unit 8.

In the adjustment operation, the gain adjustment circuit 92 of the signal under test is adjusted while looking at these displays (three types: maximum out of specification, minimum out of specification, and within the range).

FIG. 2 is a block diagram showing a specific example of the D/A converter shown in FIG. 1.

The values set in the eight bits (Al to A8) between the maximum value (MSB) and the minimum value (LSB) are weighted by the D/A converter 5.

Output value ■ in Figure 2. is given by the following equation.

...0) For example, assuming that Q dBm is set as the maximum value, V1=0.7745966 (V) V, r! n8-0.2738612 (V)shima,V
R,, -+5V, R, = 5Kt +R to R14=2
If the value is 2, then the value outside of [ ] in the above equation α) will be the value of the thorn.

Since Vo= 0.2738612, A6=I
1 in AT.

Therefore, to set QdBm, set the digital value (7) A l ~A 5, A8 to '''O''Si2
．． Just set A7 to 'l'.

In the embodiment, the adjustment is performed manually while viewing the display on the display unit, but it is of course possible to perform automatic adjustment.

That is, by feeding back the output of the comparator 6 and varying the impedance 92 of the negative feedback loop of the amplifier section 91 of the circuit to be adjusted 9, it is possible to adjust the output within the digitally specified standard by oneself. .

Furthermore, since the filter 11 provided at the input stage in FIG. 1 is a filter for removing low frequencies, it may not be necessary depending on the type of signal under measurement. Accordingly, the analog multiplexer 1 at the previous stage can also be deleted.

Effects As explained above, according to the present invention, matching is easy by using an analog multiplexer in the input section, and comparison is easy by converting the effective value of the input signal to a DC level. . Furthermore, since the set of adjustment ranges can be specified in digital quantities, it is easy to interface with other systems.Furthermore, since there are three types of output: above the maximum value, below the minimum value, and within the standard,
Adjustment is extremely easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a level adjustment circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram of the D/A converter of FIG. 1. 1.21: Analog multiplexer, 11: Filter, 2: Switch section, 3: DC level converter, 5: D
/A converter, 41: maximum value set circuit, 42: minimum value set circuit, 6: comparator, 7: logic section, 8: display section.

Claims (1)

[Claims] (1) An analog multiplexer that inputs the signal under test, a means for converting the effective value of the signal under test to a DC level, and a digital value that sets the maximum and minimum values of the adjustment range of the signal under test. D/A converting to DC level
Converter, means for comparing the value of the signal to be measured converted to the DC level, the maximum value, and the minimum value with the value converted to the DC level, and the comparison results are determined to be greater than or equal to the maximum value, less than or equal to the minimum value, and within the adjustment standard. An analog waveform level adjustment circuit characterized by having means for providing three types of logical outputs.