JPS59133642A - Panel control circuit - Google Patents

Abstract

PURPOSE:To confirm visually a switch operation, by providing a means, which picks up an OR signal among plural switch output signals on a panel operation part, and a means which generates a reset signal of a display digit selective controlling counter of a multidigit display device. CONSTITUTION:When a switch 4 (or 5) is turned on, an output signal 103 (or 104) goes to low-level, and a data line 117 goes to high-level, and an FF 2 is reset. Then, an LED control signal 108 of a counter 1 is reduced to 0, and a decoder 13 makes only a line 116A low-level to drive only a cathode-side driving signal 115A. Therefore, only an LED 11A is driven to light, and this driving is continued while the switch 4 is turned on, thus, the operaor confirms that the switch is turned on. If chattering occurs, the counter 1 is counted up to drive all of LEDs 11A-11F because a reset signal 105 is not outputted during chattering. When chattering is terminated, only the LED 11A is driven to display. Consequently, LEDs are not displayed for confirmation erroneously during the occurrence period of chattering.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an interface between a switch on a panel operation section of a computer and an internal circuit of the computer, and a panel control that controls the display of a display on the panel operation section. Regarding circuits.

[Prior art]

2. Description of the Related Art Electronic computers are provided with a panel operation section having switches and a display as an interface means between an operator and the inside of the computer. The operation of a switch thrown at this panel control section is transmitted to the internal circuit of the computer via the panel control circuit, but a switch such as a touch switch that can be made or broken by a light touch by the operator is used. In this case, the operator cannot easily determine whether the switch operation has been reliably transmitted to the inside of the computer.

Conventionally, countermeasures have been taken such as adding a circuit to the panel control circuit that detects switch operation and generates a confirmation sound so that switch operation can be confirmed. However, such a system has the problem that the switch operation confirmation circuit becomes considerably large and the amount of hardware of the panel control circuit increases.

In addition, the noise caused by the confirmation sound that is emitted each time the switch is operated can be a problem.

Furthermore, since a switch generally has a chattering phenomenon, the contact state (make or break) of the switch is determined only after the chattering ends after the switch is operated. Therefore, the confirmation sound for switch operation is
It is necessary to allow the occurrence of chattering to occur after the chattering occurrence period has elapsed since the switch operation. If this is not done, a confirmation sound will be generated even though the switch has been restored while chattering is occurring, leading to erroneous confirmation.Moreover, the period during which chattering occurs varies depending on the type of switch. However, in the conventional panel control circuit as described above, if a different type of switch having a longer chattering period than the switch assumed at the time of design is used, there is a risk that a confirmation sound may be erroneously generated.

To prevent such erroneous confirmations, the circuit must be designed in advance to accommodate switches with a sufficiently long chattering period.
All you have to do is design it. However, in a configuration where the generation of the confirmation sound is simply delayed from the switch operation, if a switch with a short chattering period is used, the generation of the confirmation sound will be unnecessarily delayed, which may impair the operability of the switch. arise.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a panel control circuit that solves the above-mentioned problems regarding confirmation of switch operations.

[Summary of the invention]

The present invention includes a means for obtaining a logical sum signal of output signals of a plurality of switches on a panel operating section, and a means for obtaining a logical sum signal of output signals of a plurality of switches on a panel operating section, and a means for obtaining a logical sum signal of output signals of a plurality of switches on a panel operating section. By providing the panel control circuit with means for generating a reset signal for the counter for display digit selection control of the above multi-digit display, switch operations can be visually confirmed on the display.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a panel control circuit according to the present invention. Although the explanation will be made assuming that two switches are provided on the panel operation section, this is for the purpose of simplifying the explanation, and the number of switches is essentially arbitrary.

In the figure, 4 and 5 are switches on the panel operation section. Output signals 103, 101 of these switches 4.5
4 becomes LOW level when the contact is made, and sets the flip-flop 6.7. Furthermore, this signal 103,
104 is connected to the data line 117 of the flip-flop 2 for switch state identification through the OR circuit 3, and is connected to the data line 117 of the flip-flop 2 for switch state identification, and is
latched to.

The output signal of this flip-flop 2 is given to the counter 1 as a reset signal 105. The power-on reset line 106 is connected to the flip-flop 6.7 in the initial state.
and set flip-flop 2.

The carry signal 107 of counter 1 is connected to the trigger input of flip-flop 6.7. The counter 1 counts up by the free run clock 101 when the reset signal 105 is not generated (at LOW level), and outputs the 7-segment LEI) control signal 108.

The 7-segment data control circuit 9 receives input data 1llX, 111Y, from the computer internal circuit 14.
The output data signals 112A to 112F of the LED display data register 8 that latch 111Z are used as the LED control signal 10.
8 to select 7 segment data 1138 to 1
Output as 13G. According to this 7 segment data, the segment anode drive circuit 10 outputs common segment anode drive signals 114A to 114G to all 6 digits 0 LED IIA to IIF on the panel operation section.

On the other hand, cathode side drive signals 1158 to 115F for each digit of LEDIIA to IIF are given from the cathode drive circuit 12, but these signals are LOW level signals among the LED selection signals 116A to 116F output from the decoder 13. Only those corresponding to are selectively driven.

That is, the 6-digit, 7-segment LEDs IIA to IIF are dynamically driven, and the display digit selection control (digit scanning) is performed by the counter 1.

Counter 1 and code 8 related to such display control,
The circuits 9.10 and 12.13 have conventionally existed in panel control circuits and are not newly provided. Furthermore, the flip-flop 6.7 is also conventionally provided for the interface between the switch 4.5 and the computer internal circuit 14. The difference from the conventional method is that an OR circuit 3 and a flip-flop 2 are provided, and the carry signal 107 of the counter 1 is transferred to a flip-flop 6.7.
This is the point at which the signal is input to the trigger terminal.

Next, the operation of this embodiment will be explained with reference to the timing diagram of FIG.

When the switch 4 (or 5) is operated to make the contact, the output signal 103 (or 104) becomes LOW level, and therefore the data line 117 becomes HIGH level. The clip-flop 2 is reset at the timing of , and the reset signal 105 is generated (becomes HIGH level). As a result, counter 1 becomes free rank clock 1.
01, and the value of the 7-segment LED control signal 108, which is the output signal of counter 1, is °゛0.
'', the decoder 13 outputs the LED selection signal 116A.
- Only 116A among 116F is set to LOW level.

Therefore, the cathode side drive circuit 12 has the most significant digit 0LEDI.
Since only the cathode side drive signal 115A corresponding to IA is driven, only the LED 11A is driven for display. This state continues while switch 4 (or 5) is being made.

That is, in this embodiment, when the switch 4 or 5 is operated to make, only the LED IIA is displayed, so that the operator can confirm whether the switch is made or not.

Immediately after making the switch 4 (or 5), the flip-flop 6 (or 7) is set, and its output signal 109 (or 110) becomes HIGH level.

After that, when the switch 4 (also the switch 5) that was open is broken, both the output signals 103 and 104 (7) become HIG)-II level and the data line 117 becomes LOW level, so immediately after that, at time t2 Defu 1
The knob flop 2 is reset to 1, the reset signal 105 is no longer output (becomes LOW level), and the counter 1 starts counting up by the free run clock 101. However, all digits of C and LED IIA to IIF are dynamically driven. Since virtually all digits are displayed simultaneously, the operator can confirm the break of switch 4 (or 5).Thereafter, at time t3 when the carry signal 107 is output, flip-flop 6 (or '1) is reset. .

The above explanation was based on the assumption that chattering does not occur at switch 5 (although the explanation is based on the assumption that S is the channel control circuit according to the present invention), even if chattering occurs at switch 4.5, the channel control circuit ensures that the chattering ends. A confirmation display like the one above will be displayed.

Moreover, the delay time from the operation of the switch σ) to the confirmation display changes automatically according to the length of the chattering occurrence period. In other words, the delay in confirmation display is shortened as much as possible in accordance with the chattering occurrence period. Therefore, it can be used with a variety of switches without sacrificing the operability of the switch, and is extremely versatile.

The operation when chattering occurs will be described below with reference to the timing diagram of FIG.

If a chattering car occurs in the switch 4 (or 5) during the period from the operation time t4 to the time t5, the output signal 103 (or 104) will not stabilize to the LOWL level immediately as shown in the figure, and will be intermittent. HIGi(
Turn to level. Since the reset signal 105 is no longer output during the HIGH level period due to this chattering (becomes LOW level), the counter 1 restarts counting up, and not only LED IIA but also all or part of LED II B to 11F are driven for display. Only the most significant digit 0LEDIIA is continuously driven to display after time t5 when the chattering ends. Therefore, there is no possibility that a confirmation display will be erroneously displayed during the period when chattering occurs. Moreover, it is clear that this effect can be achieved even if the period during which chattering occurs is short (or long).

Further, in this embodiment, the flip-flop 6.7 is triggered by the carry signal 107 of the counter 1 in order to prevent an erroneous switch operation state due to occurrence of chattering from being transmitted to the computer internal circuit 14.

That is, during the chattering occurrence period from time t4 to time t5, since the carry signal 107 is not output from the counter 1 as described above, the flip-flop 6 (or 7)
is kept set. Furthermore, even if the operation of switch 4 (or 5) is released at time t6, flip-flop 6 (or 7) is maintained in the cent state. This flip-flop 6 (or 7) is reset by
This is time t7 when the carry signal 107 is output after the chattering ends. In this way, the states of the flip-flops 6 and 7 do not change due to chattering.Therefore, there is no fear that an incorrect switch operation state will be transmitted to the computer internal circuit 14.Furthermore, such an action will prevent chattering from occurring. Since this can be achieved regardless of the length of time, it can be said to be an extremely versatile chattering prevention method.

Although this embodiment uses a 6-digit LED display, it is clear that the present invention can be similarly applied to panel control circuits using other displays. Also,
It is clear that even in the case of a panel operation unit that uses switches that are set when not operated and broken when operated, this can be handled simply by changing the logic level of the signal, etc. so that the counter is reset when one of the switches breaks. .

〔Effect of the invention〕

As described in detail above, according to the present invention, extremely few 1. c.
It is possible to check switch operation with a small amount of circuitry, and
It can be universally applied to various switches with different chattering occurrence periods, and it can also achieve many effects, such as solving the problem of noise.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram for explaining the operation of the embodiment, and Fig. 3 is a timing diagram for explaining the operation of the embodiment when chattering occurs. FIG. 1... Counter, 2.6.7... Flip-prop, 3... OR circuit, 4, 5... Switch,
IIA~11F...LED (indicator), 14
...Electronic computer internal circuit.

Claims (2)

[Claims] (1) In the panel control circuit that controls the interface between the switches on the panel operation section of the computer and the internal circuits of the computer, and the display control of the multi-digit display on the panel operation section, A means for obtaining a logical sum signal of output signals, and when one of the plurality of switches is operated using the logical sum signal as an input,
A panel control circuit comprising means for generating a reset signal for a counter for controlling display digit selection of the multi-digit display. (2) A flip-flop for an interface between a switch on a panel operation unit and an internal circuit of a computer is triggered by a specific output signal of a counter for controlling display digit selection. panel control circuit.