JPS59132682A - Protection diode - Google Patents
Protection diodeInfo
- Publication number
- JPS59132682A JPS59132682A JP835183A JP835183A JPS59132682A JP S59132682 A JPS59132682 A JP S59132682A JP 835183 A JP835183 A JP 835183A JP 835183 A JP835183 A JP 835183A JP S59132682 A JPS59132682 A JP S59132682A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- junction
- epitaxial layer
- shallow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 239000012141 concentrate Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はサージ電圧から接合破壊を防止する保護ダイオ
ードに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a protection diode for preventing junction breakdown from surge voltages.
従来例の構成とその問題点
接合分離型半導体集積回路装置（以下、パイボ２ ／
シ
ーラＩＣと呼ぶ）では、サージ電圧から接合破壊を防止
する手段として、保護ダイオードをそ々えている。従来
の保護ダイオードは、第１図に断面構造図を示すように
、浅いＰ型拡散領域１をＮ型エピタキシャル層２内に設
け、これらをＮ型埋込み領域３およびＰ型分離領域４で
囲った構造であり、Ｐ型基板６上に形成されている。す
なわち、この構造は、浅いＰ型拡散領域１をエミッタ、
Ｎ型エピタキシャル層２をベース、Ｐ型分離領域４をコ
レクタとする寄生の横型ＰＮＰトランジスタ６を形成し
ている。この構造で、浅いＰ型拡散領域１に正極性のサ
ージ電圧が加わると、横型ＰＮＰトランジスタに電流が
集中し、その表面部のエミッタ・ベース接合部、つまり
、浅いＰ型拡散領域１とＮ型エピタキシャル層２との間
のＰＮ接合面は破壊されるおそれがある。Conventional configuration and its problems Junction-separated semiconductor integrated circuit device (hereinafter referred to as Pibo2/
Sealer ICs (called sealer ICs) are equipped with protection diodes as a means of preventing junction breakdown from surge voltage. As shown in FIG. 1, a conventional protection diode has a shallow P-type diffusion region 1 in an N-type epitaxial layer 2, which is surrounded by an N-type buried region 3 and a P-type isolation region 4. This structure is formed on a P-type substrate 6. That is, in this structure, the shallow P-type diffusion region 1 is used as an emitter,
A parasitic lateral PNP transistor 6 is formed having the N-type epitaxial layer 2 as a base and the P-type isolation region 4 as a collector. In this structure, when a positive surge voltage is applied to the shallow P-type diffusion region 1, the current is concentrated in the lateral PNP transistor, and the emitter-base junction on the surface, that is, the shallow P-type diffusion region 1 and the N-type There is a possibility that the PN junction surface between the epitaxial layer 2 and the epitaxial layer 2 will be destroyed.
発明の目的
本発明は、上述のよう々保護ダイオードにおける寄性の
横型ＰＮＰ ）ランジスタでの電流集中を有効に緩和す
ることができる構造を提供するものである。OBJECTS OF THE INVENTION The present invention provides a structure that can effectively alleviate current concentration in a parasitic lateral PNP transistor in a protection diode as described above.
発明の構成
本発明は要約すると、−導電型半導体基板に反対導電型
の埋込み領域および接合分離されたエピタキシャル層領
域を有するとともに、前記エピタキシャル層領域内に前
記基板と同じ導電型の浅い拡散領域と、この浅い拡散領
域を囲んで前記埋込み領域に達する反対導電型の深い拡
散領域とをそなえだ構造の保護ダイオードである。この
構造によれば、寄生の横型トランジスタのベース領域濃
度を実質的に高め、したがって、寄生の横型トランジス
タの電流増幅率を小さくして、浅い拡散領域の局部に電
流集中が起こる現象を抑制することができる。SUMMARY OF THE INVENTION The present invention can be summarized as follows: - having a buried region of opposite conductivity type and a junction-separated epitaxial layer region in a semiconductor substrate, and a shallow diffusion region of the same conductivity type as the substrate in said epitaxial layer region; The protection diode has a structure including a deep diffusion region of an opposite conductivity type surrounding the shallow diffusion region and reaching the buried region. According to this structure, the base region concentration of the parasitic lateral transistor is substantially increased, and therefore the current amplification factor of the parasitic lateral transistor is reduced, thereby suppressing the phenomenon of current concentration locally in the shallow diffusion region. I can do it.
実施例の説明 第２図に本発明の実施例装置の断面構造を示す。Description of examples FIG. 2 shows a cross-sectional structure of a device according to an embodiment of the present invention.
この実施例装置は、浅いＰ型拡散領域１がＮ型エピタキ
シャル層領域２内にあり、これを囲んでＮ型の深い拡散
領域７がＮ型の埋込み領域３に達するように形成されて
いる。そして、前記Ｎ型エピタキシャル層領域２は、通
常構造の接合分離領域４によって島状に分離されている
。この構造によれば、正極性のサージ電圧に対して陽極
部となるＰ型の浅い拡散領域１の周囲をＮ型の深い拡散
領域７で埋込み領域３に達するように取り囲み、これに
よって、寄生の横型ＰＮＰ ）ランジスタのベース領域
は全周囲にわたって実効的にＮ型濃度の高いものになる
。したがって、との構造によってもたらされる寄生の横
型ＰＮＰ ）ランジスタはその電流増幅率ｈＦＥが実効
的に小さく々す、正極性のサージ電圧を受けたとき、Ｐ
型の浅い拡散領域１での接合電流が分散し、局部に電流
の集中する傾向が避けられる。すなわち、サージによる
注入電荷は、はとんど、Ｎ型埋込み領域３とＰ型半導体
基板６との逆方向接合での比較的広い接合面において放
電させることができる。経験によれば、１００ｐＦのコ
ンデンサの放電に対して、従来の保護ダイオードでは２
６０ｖ〜３００Ｖが破壊特性の限度であったものが、本
実施例によれば、３６０ｖ〜４００’Ｖに大幅に改善さ
れた。In the device of this embodiment, a shallow P-type diffusion region 1 is located in an N-type epitaxial layer region 2, and surrounding this, a deep N-type diffusion region 7 is formed so as to reach an N-type buried region 3. The N-type epitaxial layer region 2 is separated into islands by junction isolation regions 4 having a normal structure. According to this structure, a P-type shallow diffusion region 1 that serves as an anode portion for a positive surge voltage is surrounded by an N-type deep diffusion region 7 reaching the buried region 3, thereby preventing parasitic The base region of the lateral PNP transistor has an effective N-type concentration all around. Therefore, when the parasitic lateral PNP transistor is subjected to a positive surge voltage, its current amplification factor hFE is effectively small.
The junction current in the shallow diffusion region 1 of the mold is dispersed, and the tendency for the current to concentrate locally can be avoided. That is, the charge injected by the surge can be discharged mostly at a relatively wide junction surface in the opposite direction junction between the N-type buried region 3 and the P-type semiconductor substrate 6. Experience has shown that for a 100 pF capacitor discharge, a conventional protection diode
According to this example, the limit of the destructive characteristic was 60v to 300V, but it was significantly improved to 360v to 400'V.
５ 、 。5.
発明の効果
本発明によれば、接合分離されたエピタキシャル層領域
内に浅い拡散領域によるＰＮ接合を形成し、かつ、この
ＰＮ接合を囲んで高濃度の深い拡散領域を前記エピタキ
シャル層領域の直下の埋込み領域に達する深さに形成し
たことにより、前記ＰＮ接合を通じてサージ電圧を受け
だときの注入電荷を、前記埋込み領域と基板部との広い
面積の接合面でのブレークダウンによって放電させるか
ら、寄生の横型バイポーラトランジスタ効果に起因する
前記ＰＮ接合の局部に電流集中を生じることがなく、し
たがって、局部における接合破壊がなくなり、高性能、
高安定性が確保される。Effects of the Invention According to the present invention, a PN junction is formed by a shallow diffusion region in a junction-separated epitaxial layer region, and a high concentration deep diffusion region is formed immediately below the epitaxial layer region surrounding this PN junction. By forming the PN junction deep enough to reach the buried region, the injected charge when receiving a surge voltage through the PN junction is discharged by breakdown at the wide-area junction surface between the buried region and the substrate, thereby reducing parasitic Current concentration does not occur locally in the PN junction due to the lateral bipolar transistor effect, and therefore local junction breakdown is eliminated, resulting in high performance and
High stability is ensured.
第１図は従来の正極性のサージ保護ダイオードの構造を
示す断面図、第２図は本発明の正極性のサージ保護ダイ
オードの構造を示す断面図である。
１・・・・・・浅いＰ型拡散領域、２・・・・・・Ｎ型
エピタキシャル層領域、３・・・・・・Ｎ型埋め込み領
域、４・・・・・・Ｐ型分離拡散領域、６・・・・・・
Ｐ型基板、６・川・・寄生６１、ジ
の横型ＰＮＰ ）ランジスタ、７・・・・・・深いＮ型
拡散領域。FIG. 1 is a cross-sectional view showing the structure of a conventional positive-polarity surge protection diode, and FIG. 2 is a cross-sectional view showing the structure of the positive-polarity surge protection diode of the present invention. 1...Shallow P-type diffusion region, 2...N-type epitaxial layer region, 3...N-type buried region, 4...P-type isolation diffusion region , 6...
P-type substrate, 6. Parasitic 61, di-horizontal PNP) transistor, 7... Deep N-type diffusion region.
Claims (2)
よび接合分離されたエピタキシャル層領域偵 を有するとともに、前記エピタキシャル層積域内に前記
基板と同じ導電型の浅い拡散領域と、この浅い拡散領域
を囲んで前記埋込み領域に、達する反対導電型の深い拡
散領域とをそなえた構造の保護ダイオード。(1) - Having a buried region of the opposite conductivity type and a junction-separated epitaxial layer region in a semiconductor substrate of a conductivity type, and a shallow diffusion region of the same conductivity type as the substrate in the epitaxial layer stack, and this shallow diffusion region. and a deep diffusion region of opposite conductivity type that surrounds and reaches the buried region.
。 域がＰ型でなる特許請求の範囲第１項に記載の保護ダイ
オード。(2) Epitaxial layer region is N type and shallow diffusion region
. 2. The protection diode according to claim 1, wherein the region is P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP835183A JPS59132682A (en) | 1983-01-20 | 1983-01-20 | Protection diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP835183A JPS59132682A (en) | 1983-01-20 | 1983-01-20 | Protection diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59132682A true JPS59132682A (en) | 1984-07-30 |
Family
ID=11690799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP835183A Pending JPS59132682A (en) | 1983-01-20 | 1983-01-20 | Protection diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132682A (en) |
-
1983
- 1983-01-20 JP JP835183A patent/JPS59132682A/en active Pending
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