JPS59132668A - Output device of charge transfer element - Google Patents

Abstract

PURPOSE:To enable to obtain an output signal of a good S/N ratio and linearity under a given power source voltage and a large level by providing a voltage boosting circuit which produces a voltage of an absolute value larger than that of the power source voltage and supplies to a drain region as a reset voltage. CONSTITUTION:Signal charges are inputted to a floating diffused region 9 by means of an output gate electrode 10, and then the potential thereof becomes PG. This charge 31 is detected at certain timing, and, the potential PRL under a reset gate electrode 13 at this time cuts off the drain region 11 and the region 9. When a reset pulse phiR becomes a high voltage VRH, the potential PRH under the electrode 13 makes the region 9 and 11 conduct, and accordingly the region 9 is reset at the level P'D of a reset voltage. The voltage VGG becomes higher than the power source voltage VDD by providing the pressure increasing circuit, and the dynamic range DR of an output signal increases by the difference between the potential P'D of the region 11 and that PG under the electrode 10. Therefore, the output signal of good S/N ratio and linearity under the given power source voltage and a large level can be obtained.

Description

[Detailed description of the invention] [Technical division of the invention] The present invention provides solid-state imaging devices, charge transfer type slow i-line, <L
The present invention relates to an output device for a charge transfer element used in a shaped filter, a transversal filter, etc.

[Technical prefectural expenses for Kamei]

In recent years, charge transfer confectionery (hereinafter abbreviated as CTD) has been developed by A.
11 has been used to realize charge transfer type delay lines, comb filters, transversal filters, etc. Each of these INCTDs incorporated external circuits internally for the purpose of improving characteristics and lowering the overall cost of the computer system, and was developed as an integrated circuit that had a number of functions in one chip. It has become.

Conventionally, the CTD output method has been a floating diffusion method or a floating capacitor method. This floating cell method has the advantage of being able to release charges non-destructively to the main body, but has the disadvantage that it is difficult to obtain a gain compared to the floating diffusion method and is not suitable for SA. On the other hand, although the floating diffusion method has the disadvantage that the charge can only be detected once, it has many advantages such as easier gain and better SA compared to the 7 loading gate method, so it is generally used. is used.

FIG. 1 shows the structure of a conventional CTD collector circuit, and FIG. 2 shows a part of the structure shown in FIG. 1 (for example, an N-channel embedded CTD). . In Figures 1 and 2, 1 is an input terminal, 2 is an output terminal, 3 is the first voltage terminal at ■DD potential, and 4 is the second ηi at v88 potential.
．． This is the ljt terminal. 5 is a semiconductor substrate of an integrated circuit, 6 is a film for loquats, 2 is an input part that applies a DC bias to the analog signal input from input terminal 1 to perform voltage/charge conversion, and 8 is a series connection from this input part 7. given to? 4yHf'+ i
9 is a floating diffusion region (N-swelled diffusion layer) adjacent to the bottom of the output dart electrode 10 at the final stage of this charge transfer section 8; 1 is a CTD drain region to which the power supply voltage vDD is applied; (diffusion layer). 12 has a reset dart i1 and a pole 13 between the floating diffusion region 9 and the drain region 1, and a low voltage RL. Reset that changes between and high voltage V□
This is a reset means for discharging unnecessary charges from the floating diffusion region 9 to the drain region 11 when the zf pulse φ8 is applied and the reset pulse φ8 is a high voltage vRH. 14 is a charge detection (charge/?t].pressure conversion) phase conversion ET (field effect transistor) whose dart is connected to the floating diffusion region 9 and whose drain is supplied with a power supply voltage vDD, and 15 is at least one FET. A source follower consisting of the FW'rM'4 and the circuit block 15, which has a current source function and is connected between the source of the FFi; The circuit is an output circuit 16, and FET1
The four sources 5 and 5 are connected to the output terminal 2. Note that the transfer unit 8
is, for example, a two-phase transfer block φ1.

It is a two-phase drive type CTD that is driven by lF! ．． The stage has an output 1θ to which the current city pressure v8 is applied. In addition, the reset 1 voltage vl1G and the reset z9 pulse φ8 high voltage vRI
K hasorezore v. , ≦vDD,vR1{≦vr,D.

Next, Q'rJ's work in the above CTD integrated circuit will be explained in the third section.
This will be explained with reference to the figures. The input section 2 converts the analog signal input into a DC bias charge according to the busy input level or into a J- AC charge.

The charge 3l is transferred to the transfer unit 8 and input into the floating diffusion region 9.The charge 3l is transferred to the FET 74 at a certain timing.
The charge is converted into a charge/total pressure and detected. At this time,
The reset pulse φ8 is at a low voltage vRL, and at this time, the potential value PRL below the reset voltage vGo is maintained at the reset voltage vGo level.
1 and 70-ting area 9 are cut off. Next, reset nose f φ8 or jh air pressure V □
Then, the floating wave number region 9 and the drain region 1 are made to pass through the floating wave number region 9 and the drain region 1 to the potential value PRH below the reset data)'i1.4113. The reset dart passes under the positive electrode 13 and is discharged (absorbed) into the drain region 1, and the floating diffusion region 9 is reset to the reset voltage - GG level. And reset Yarusφ. When the town's pressure reaches RL, the floating diffusion region becomes a floating state and waits for θ'IQ:i'(i+1 human power).

J:p for charge/voltage conversion as described above.
The dynamic 17-range DR of the output signal that is detected and served by the output signal 2 is connected to the 71 potential IY port of the drain region 11. It is expressed as the difference (pD-p,) between the output dart and the potential fi1th)6 below the pole 10.

[Problems with background technology]

By the way, in a CTD kamokasu circuit with higher dα,
Even if the power supply voltage v1.)D becomes very low, the S/N and linearity are good, and the demand for obtaining a larger output level increases, even if the power supply voltage v1. If there is a request to obtain an output signal level with good linearity and the same level as the current level, conventionally the output dirt is '1-7%7.

This is dealt with by lowering the applied voltage VB. However, even in this case, the final stage transfer polarity 17n, 18n of the transfer unit 8
The voltage (pressure of clock φ2) is OV, ”+7)(!:
When the potential value pnL under the transfer electrode 18n of a becomes a certain low value, the transfer '..., the front becomes easier to receive the influence of the surface level, so that the lower limit of the absolute value of the potential value PnL I am very limited by myself, and I can't fully respond to the request of the former master. Also, the absolute value of the potential under the output dart electrode 10 is the absolute value P of the potential under the electrode 18n.
. As the value becomes lower, the charge storage capacity of the transfer section 8 becomes slightly smaller.

[Object of the Invention] The cold valve 1 is developed based on the above little finger, and has good S/N and linearity under a predetermined source voltage, making it possible to obtain a large level output signal. Or S,,-
The present invention provides an output device for a charge transfer element that has good N and linearity and can use a low power supply voltage to receive an output signal of a predetermined level.

[Invention 1! In other words, the CTD output device of the present invention generates a voltage whose absolute value is larger than the source voltage by using heavy pressure. A booster circuit for supplying reset voltage to the drain region as a reset voltage is formed on the same chip as the CTD.

As a result, the potential value range of the 70-ting diffusion region becomes larger, the dynamic range of the CTD output signal becomes larger, and a high-level output signal with excellent 9-8/N and linearity can be obtained. become.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 shows the CTD integrated circuit 11. and the cumulative φ. The cross-sectional structure of a part thereof is 5h<IVC2j.

CTD collection circuit No. 1 shown here: 1. Also CTT) jll, 1.
'r: Compared to the circuit, an external voltage circuit 41 is provided to boost the power supply voltage VDo, and the voltage output of this voltage boosting circuit 4 is set to the reset voltage V of the drain region 11. The difference is that the voltage is applied as 0, and the rest is the same, so the same reference numerals as in the first and second parts are given, and the so-called explanation thereof will be omitted.

The operation of the above CTD circuit is as shown in FIG. 6, which is almost the same as the operation described above with reference to FIG. 3, except for the reset voltage V. Since the relationship between IVo and DIVDDI is established between 0 and the power supply voltage v110, the range of change in the potential value of the floating diffusion region 9 is increased compared to that in the conventional example. 1,000). That is, in this embodiment, the reset box pressure is 1 V. 0 is 1
t1y city, pressure V. Since it is higher than 9, the output electrode 1
Assuming that the applied voltage VB of θ is the same as the conventional example,
Dynamic range DR of output signal (drain region 11
potential value P. ' and the potential value P below the output electrode 1'') is larger than that of the conventional relay.

In other words, the reset voltage V is boosted to a value vDD' which is lower than the value vDD of the above embodiment.

By setting 0 to vDD, it is possible to achieve the same dynamic range as the conventional example. Therefore, the power supply voltage of the above CTI) Komaga circuit”
It becomes possible to reduce the voltage of the DD and apply it to a system using the same power supply system.

Furthermore, according to the above embodiment, the CTD output Wl≦ [1-1'' can be accommodated in one direction without increasing the capacitance component existing in the 70-ring diffusion region 9 compared to the conventional example. Capacity is increasing.

Note that the reset voltage of the drain region 11 is 1 pressure. If 0 is higher than the voltage vDD of the power supply box, the reset voltage vGo is applied to the FETs 14 for the power supply box and L1 when the 70-teing diffusion region 9 is reset. Now, when detecting the signal (1) Upper i; t4FET14 dart voltage,
Pressure VG, drain source song 'ton pressure ke■Da.

When the gate-source voltage is VGS, the threshold voltage is VTH, and the source voltage (at output, 20 peaks 1 voltage) is -V, then vDB=vDD"0-(1) ■J'T11""VG-VO-vTH...(2). Therefore, in order for the FET 14 to perform almost the 11th operation when 1F='rj is detected, vGs-vTH<"DB'-<:3). It is necessary to define (1), (
It is necessary to substitute 2) to obtain ■o−■, □<vDl) (4). In other words, when output 1 + j is required to have good kana-green shape, it is necessary to determine the voltage 1 + j so that the above equation (4) holds true at the time of signal detection. This limit is sufficient when such linearity is not required.

In the above embodiment, the reset voltage V of the drain region 1. When the relationship reaches the level of 0, the reset pulse φ,
However, the potential value P□ under the reset dirt electrode 13 when the pressure is □ becomes so low that it becomes impossible to reset.

In order to solve this problem, 1, l of reset pulse φ8 is required.
-FH15j: Pressure V□ is also boosted in CTD&q=, in the ramming circuit, and vRH slip set fIi, pressure ■. Just make it higher than G.

In addition, the low frost pressure vRL of the reset Qrus φ8 is equivalent to forming a potential value corresponding to the level of the load flowing into the floating 1mm Y#J area 9 under the reset dart electrode 13. Keep it below the voltage level Q.
good.

Figure 7 shows an example of the boost circuit 13 (Figure 4 41) for boosting the reset voltage GG. N-channel depression type VO8) Run Soster, 77 has a low voltage of V88 and a high voltage of DD.Grus φ is input (Rus input terminal, 78 is a boosting capacity, 7g is a boosted voltage output node. Yes. That is,
The source of the transistor 7) is connected to the V8s power supply, its source is connected to the source input terminal 77, and between its drain and the VDD power source, a transistor 74 connected to the source 11 is connected to the load. An inverter is formed by being connected as one. One end of the input/output node 801/Cf1i) is connected to the output node 78, and transistors 72 and 76 are connected in series between the other end of the capacitor 78 and the vs8 power supply. Further, the dart of the transistor 72 is connected to the pulse input terminal 7, and the drain and source of the transistor 76 are connected to each other. The transistor 75 has a drain
The darts are connected to each other, VDD, '4. ' source and the connection point between the dosin 14 and the distaff 2, 76. Further, a transistor 73 is inserted between the other end of the capacitor 78 and the booster/output cup door 9, the drain and the drain being connected to each other.

Therefore, when the input voltage φ is V voltage, the voltages 1 and 72 are turned on, and the inverter output node 80 (rJ-V, 'mlc
voltage, and the other end of customer month -78 is transistor 75.76
becomes the voltage VA at the interconnection point. Next, the input e system φ
When becomes the V8B voltage, transistors 7) and 72 are turned off, the inverter output node 80 of the capacitor 78 has a voltage of vDD', and the voltage at the other end of the capacitor 78 is the effect of the capacitor 78. It increases to a value of approximately (■Dl, 10VA).

Here, the threshold value ``voltage'' (j:
At VTH? When this is done, the voltage (becomes 0 due to reset) of the boosted voltage output two-door 9 rises to a value of 1, which is approximately (vDD + vA - vTH).

FIG. 8 shows the reset position φ as described above.

A specific example of a booster circuit built into the CTD4 + booster circuit when there is a need to boost the voltage is shown in Figures 8 and 82.
are N-channel delusion type MO8) transistors, and their drains and darts are connected to each other, and they are connected in series between the vDD and v8s' sources.

The above transistor 8. ．． N-channel enhancement type MOS transistors 84 are connected in the 111th column between the interconnection point of 1.82 and the boost pulse output node 83, and the low voltage at the r-t is vs8 and the high voltage is V. It is connected to a pulse input terminal 85 to which the pulse φ of D is input. Further, one ring of a load/pressure capacitor 86 is connected to the boost pulse output node 83, and the other part of the load/pressure capacitor 86 is inputted with an inverted system φ having an opposite phase to the pulse φ.
is connected to the pulse input terminal 87.

Thus, the input pulse φ is V. rW voltage, φ reaches V38 voltage, transistor 84 turns on, transistor 8
The voltage vc at the interconnection point of 1.82 is supplied from the boost pulse output node 83 as the low voltage vRL of the reset pulse φ. At the same time, the capacitor 86 is charged with a charge such that the terminal voltage becomes vc. Input curl 4 φ is v8
8 voltage, when φ reaches the vDD voltage, the transistor 84 is turned off, and the boost pulse output node 83 is reset) p
Ideally, the Kochi and pressure RH of 4 pulses φ8 would be the lower 11 component on the gate electrode side.

The above embodiments have shown CTD integrated circuits of N'' channel type, embedded channel type, two-layer polysilicon structure, and two-phase drive type. It can also be applied to the transfer channel, shape, electrode (sea lion structure, electrode structure, depth of the channel section, input section addition, transfer section structure including the number of phases of the transfer lock, etc.). The CTD itself has a charge transfer type delay of approx.
<17- It is possible to form square-shaped (comb) fields, transverse filters, etc., but this article also applies to various applied products of A11; 1:KjJ-11r] ] I can do it. For example, the present invention can also be applied to the charge output part (horizontal circuit CTD register and O output circuit) of the line + inner and 7'. In this case, the horizontal direction IM'' horizontal direction column from the imager section is input to the transfer section in parallel.

If the filter is +fjffJ"t, "11.1n
All you have to do is add a digit.

〔Effect of the invention〕

As mentioned above, the CTD σ) output device of this invention can provide a high-level output signal with good SAt and quietness under a predetermined acupuncture voltage, or
/'Nj' - Good line J performance <i; Power supply 1 [1: Pressure = w-1L! :(
This has the advantage of being able to do this.

[Brief explanation of the drawing]

Figure 1 shows a conventional charge transfer circuit 1'1 circuit.
8- Figure 2 shows the structure of a part of the charge transfer element in Figure 1, Figure 3 shows changes in the potential distribution in the substrate in the charge transfer element in Figure 2. i4S?
, FIG. 4 is a diagram showing an embodiment of the output device of the charge transfer device according to the present invention, and FIG. 5 is a diagram showing the output device of the charge transfer device of FIG. FIG. 6 is a diagram showing a partial cross-sectional structure of the charge transfer device shown in FIG. Figure 7 is a circuit diagram showing a specific example of the reset voltage booster circuit shown in FIG. 4; Figure 8 is a diagram showing a specific example of the reset pulse booster circuit shown in FIG. It is a circuit diagram. 5... Semiconductor, jIj,')fi, 8... Charge transfer section, 9... Floating diffusion region, 1... Drain region, 12... Reset means, No. 3... Reset Dart i [&, 14...FET, 76... Output circuit, 41... Boost circuit, vI) D... Power supply voltage, v
GG...Reset voltage, φ8...Rehit pulse. Patent attorney for applicant Takehiko Suzue 19- Figure 1 iI2 Figure 6 s7 Figure VQS-11o% W cocop (Voo, Vss)

Claims (6)

[Claims] (1) A floating diffusion region formed on a conductive substrate and to which signal charges are transferred from the deafening sound μ, a drain region to which reset pressure is applied, and this drain region and the floating diffusion region. a reset means for controlling conduction or non-conduction between the two regions by a voltage level of reset/resistance; Output 5
In a real-equivalent transfer 54-element extension blade device that includes an output circuit that digitizes the number, the electric 1L pressure is larger than the iid pressure of the counterfeit power circuit, and the insects are removed by external pressure. An output device for a charge transfer element, characterized in that a booster circuit connected as the reset voltage is formed on the barrel-shaped substrate. (2) Voltage level applied to the reset + stage when conducting the floating discharge region and the drain region IdAiJ The box Yb1 ( 'Tun IJE also has 17 so that the absolute value becomes large. 4+H,.
lik's tf't, r:h transfer element output device. (3) The output circuit is connected to the dart or the previous equation 1-' floating diffusion region.
) Using a source follower circuit using a transistor, Mokugo)
The above-mentioned I11j, l, meter is characterized in that the above-mentioned electric cable V effect 1, □transistor or -1'' is the output device for the first term h1-・1'+1j of the range 1 decoy transfer purple. (4) The output device for the charge transfer system described in the patent, characterized in that '+', '+' and 'Q', and the sending part and '', respectively, are transfer-type delay lines. (5) The above '+1i what transfer unit 1'; l:if what transfer type transpersulfinoreta A'l fortune-telling: the range of the 114 search for the charge described in the first box Transfer system output device. (6) The frost one-direction transfer section is configured such that one of them φ, (1a
At the step, add the charge transferred from other charge transfer confectionery.
An output device of a patented charge transfer element characterized by forming a comb-shaped filter.