JPS59130472A - Insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To prevent a negative feedback loop generated when avalanche multiplies and thus prevent the phenomenon of negative resistance generated after drain withstand breakdown by a method wherein the resistance value of a substrate in a high withstand MOSFET is reduced, thus putting the transistor in a structure wherein the drain withstand voltage is determined by the junction voltage between the drain and the substrate. CONSTITUTION:A P type epitaxial layer 1' has the impurity concentration NA at 1.3X10<15>cm<-3> and the thickness at 12mum, and the P type high impurity concentration substrate 1'' has NA at 5X10<18>cm<-3>. A source region 2 and a drain region 3 is 1.5mum deep, and a gate insulation film 6 is 130mum thick. An N type high specific resistance region 5 is formed by ion implantation; the length LR is 13mum, and the amount of ion implantation NDS is 1X10<12>cm<-2>. An N type drain intermediate region is 8mum deep. The dimensions of this element are: 4.3X4.3mm. in chip size, 8mum in channel length, and 18cm in channel width. For assembly, a chip is attached and wired by means of an Al wire of 300mum phi. The breakdown characteristic between the drain and source of this MOSFET does not generate negative resistance phenomenon at all.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as an I
GFET), especially L with high drain breakdown voltage
Regarding G E F T.

[Background of the Invention] In general, I n5ulated-Gate FET
Currently, IGFETs, which are called
It was used as a switching element for low voltages below 0V and small currents below several milliamps.

However, for the following reasons, it is desirable that the ICEFT be applied not only to such conventional low voltage and small current applications but also to high voltage and large current applications. For example, ICE
In FT, when the drain current is relatively large, this drain current has a negative temperature coefficient, and even if a potential difference is generated on a large semiconductor pellet due to the current flowing through the electrode, a current concentration phenomenon does not occur, so destruction due to thermal runaway occurs. It's hard to do.

IGEFT has a high input impedance, and the drain current is proportional to the square of the gate-source voltage, and has almost no high-order components. Therefore, ICEFT has high power gain and exhibits characteristics of lower distortion. In addition, the drain voltage vs. drain current characteristic of the IG"EFT exhibits saturation characteristics, so-called pentode characteristics, so it exhibits good characteristics against fluctuations in power supply voltage. You can freely choose.Also,
Changes in gate-source capacitance and gate-drain capacitance due to changes in gate voltage, drain voltage, etc. are much smaller than in junction field effect transistors.

Therefore, in order to use IGEFTs at high voltages and large currents, high voltage structures have been developed. FIG. 1 shows a cross-sectional view of the structure, which is a so-called offset gate structure. In the figure, 1 is a P-type silicon substrate, 2 is an N-type source region, 3 is an N-type drain low resistivity region, 41. An iN-type train intermediate region, 5 an N-type high resistivity region connected to the drain intermediate region, a so-called offset gate region, 6 a silicon oxide film, and 7 a silicon substrate 1 between the source and drain regions via the silicon oxide film 6. A gate electrode made of, for example, polycrystalline silicon is formed on the surface of the channel region, and 8 and 9 are source electrodes, respectively.

This is the drain electrode.

This MO8 type IG with offset gate structure for high voltage
The breakdown characteristic between the drain and source of the EFT is shown by curve 8 in FIG. As is clear from the curve, this structure breaks down at 200V, and after the breakdown current IDS flows, negative resistance development appears prominently. This is particularly noticeable in N-channel devices. Therefore, in this MO5 type ICEFT for high voltage,
Due to the high applied voltage, a large current flows due to the negative resistance phenomenon, and once it enters the negative resistance region, it has the disadvantage of being extremely susceptible to destruction, which is a major problem in the production of high voltage, large current devices.

[Object of the Invention] The object of the present invention is to improve the conventional high voltage MOSFE described above.
M with excellent destruction resistance that completely eliminates the negative resistance phenomenon of T.
Our goal is to provide OSFETs.

[Summary of the Invention] In order to achieve the above object, the present invention uses a source region as a substrate of a high voltage MO8FET.

By using a substrate in which a semiconductor including a semiconductor region with a drain region is connected to a semiconductor or a conductor having a lower resistance than the semiconductor through ohmic contact, and by making the length of the high resistivity region more than a predetermined value, the drain breakdown voltage can be increased. is limited by the junction breakdown voltage between the drain and substrate.

The principle of the present invention will be explained in detail below. First, the results of the inventor's analysis of the reason why the negative resistance phenomenon exists in the structure shown in FIG. 1 will be described. 3 is a schematic diagram for explaining the operation of the structure shown in FIG. 1, FIG. 3(a) is a cross-sectional structural diagram, and FIG. 3(b) is an equivalent circuit diagram thereof. In the figure, a parasitic NPN bipolar transistor (E is an emitter, B is a base, and C is a collector) is constituted by a source region 2, a substrate 1, and drain regions 3' and 5. Now, when avalanche multiplication occurs in the substrate surface area near the gate electrode 7, that is, the high resistivity region 5, the generated hole current flows to the substrate 1, and the resistance R existing in the substrate 1
Generate voltage at 8IJB. Therefore, the potential of the substrate 1 becomes about 0.5V higher than the potential of the source region 2,
A leprosy bias is applied between E and B of the parasitic NPN bipolar transistor, causing electrons to flow from the source region 2 to the substrate l. When the injected electrons again undergo avalanche multiplication in the high electric field on the substrate surface near the gate electrode 7, they form a positive feedback loop, and as a result, it is thought that negative resistance occurs. In addition, the hole current generated by avalanche multiplication in the substrate surface portion also flows into the source region 2, which is considered to form a positive feedback loop.

The reason why the negative resistance phenomenon is less likely to occur in P-channel MOSFETs can be explained by the fact that the carriers injected from the source region into the substrate are holes, which have a lower ionization rate than electrons, so the positive feedback loop described above is less likely to occur. .

Based on the above recognition of the reason for the occurrence of negative resistance phenomenon.

The present inventor discovered that the following two points are effective in preventing the negative resistance phenomenon. That is, as a first step, by substantially lowering the value of the resistor R9ua present in the substrate l, the PN junction between the source region 2 and the substrate l is made less likely to be biased in the forward direction. Second, by making the electric field strength near the substrate surface weaker than the electric field strength inside the substrate, avalanche multiplication does not occur at the surface but occurs inside the substrate, and carriers injected from source region 2 is not related to avalanche multiplication.

The above two points make it possible to prevent the above-mentioned positive feedback loop and, by extension, the occurrence of the negative resistance phenomenon.

Regarding the above-mentioned first point, the substrate has two layers, a low resistivity layer and a high resistivity layer. For example, a high resistivity layer is formed by epitaxial growth on a low resistivity semiconductor substrate, and a source region, a drain region, etc. are formed in this layer. Furthermore, regarding the second point mentioned above, the length of the high resistivity region is hereinafter referred to as LR. ) shall be a value greater than or equal to a predetermined value. This can be explained as follows.

That is, in order to determine the drain breakdown voltage by the junction breakdown voltage between the drain and the substrate, it is sufficient to create a portion where the electric field strength is maximum when a certain voltage is applied to the drain at the junction between the drain and the substrate. To achieve this, the length of the depletion layer extending on the substrate surface should be made longer than the depletion layer extending at the junction between the drain and the substrate, so the length Ll12 of the high resistivity region formed on the substrate surface should be set to a predetermined value or more. By doing so, the length of the depletion layer extending on the substrate surface is increased.

[Embodiments of the invention] The present invention will be explained in detail below using examples.

FIG. 4 shows a cross-sectional view of one embodiment of the invention.

1' is a P-type epitaxial layer with an impurity concentration NA of 1.
．． It is 3×10 cm and has a thickness of 12 μm.

+8-3 1# is a P-type high impurity concentration substrate with NA of 5×10 cm. Source area 2. Drain region 3 has a depth of 1.5μ
m, the gate insulating film 6 has a thickness of 130 nm. The N-type high resistivity region 5 is formed by phosphorus (P) ion implantation, has a length LR of 13 μm, and an ion implantation amount NDS.
is I x 1012on-''.The depth of the N-type drain intermediate region is 8 μm.The dimensions of this device are 4.3 x 4.3 mm for chimney size, 8 μm for channel length, and 18 cm for channel width. -3 A chip was attached to the stem, and wiring was done with an AQ wire of 300 μmφ.

The drain-source breakdown characteristic of this M,08 FET is shown in curve 5 in FIG. Even after breakdown occurs at 200V and breakdown current IDS flows, no negative resistance phenomenon occurs at all, unlike the conventional 8 curves. This is because the substrate is formed of the high impurity concentration substrate 1# and the epitaxial layer 1', and the high resistivity region 5
Since the length LR is set to 13 μm, the thickness xp of the epitaxial layer 1' under the drain region 4 is larger than 4 μm, and the depletion layer on the substrate surface is larger than the depletion layer extending between the drain and the substrate. This is because avalanche multiplication occurs inside the substrate, so no negative feedback loop occurs.

Furthermore, the effects of the present invention can also be exhibited by other characteristics. FIG. 5 shows a comparison between the conventional example shown in FIG. 1 and the above-described embodiment of the present invention with respect to the safe operating area (ASO) corresponding to the breakdown resistance characteristics of a MOSFET.

In this measurement, the To-3 stem was set in an infinite heat sink, DC power was applied, and the point at which the element broke was plotted. a is a conventional element with a voltage VDS of 1
00■ or more, the current 1o5 decreases rapidly. This is due to the negative resistance phenomenon appearing in the characteristics shown in FIG. 2a. On the other hand, b is the element of the above example, Vo
II) No sudden drop in S appears until S reaches the breakdown voltage of 200V. That is, according to the present invention, A
This means that the SO range has increased significantly.

Next, another embodiment of the present invention is shown in FIG. The figure shows, when viewed from FIG.
The only difference is that ' also serves as a source field plate and covers the high resistivity region 5, and everything else is the same. In this example, in addition to the negative feedback loop prevention effect described above, good results were also obtained in a reliability test using high temperature reverse bias. Regarding the effects of the source field plate, please refer to Japanese Patent Application No. 141653/1983.

FIG. 7 shows experimental results showing changes in drain breakdown voltage B VpS when the length LR of the high resistivity region 5 is changed in the MOSFET of the present invention shown in FIG. Note that the following facts apply not only to the embodiment shown in FIG. 4 but also to all MOSFETs having the structure of the present invention. The amount N, s of ion implantation of phosphorus (P) into the high resistivity region 5 is 7.5 to 1.
2. ! Although it was varied between 5 x 10"cm-", it shows almost the same trend. The common points are that BVD5 increases depending on LR until LR is 6.5 μm.
At 6.5 μm or more, it does not depend on L and exhibits a substantially constant value. This is mentioned earlier, when L is greater than a predetermined value (
Region S) of the present invention means that the region that limits the breakdown voltage changes from the substrate surface to the junction between the drain and the substrate.

The results of computer simulations conducted to theoretically support this fact are shown in FIGS. 8 and 9. Figures 8 and 9 show that LR is 6μ in the embodiment shown in Figure 6.
This is the calculation result of the electric field distribution in the cross section of MO8FET when m is 20 μm, and a voltage of 140 V is applied between the drain and source.

In FIG. 8, the electric field concentration occurs at the substrate surface 21' at the end of the gate electrode 7. In FIG. In other words, when LR is short, the breakdown voltage of the high voltage MOSFET is limited by electric field concentration on the surface of the substrate, and avalanche multiplication occurs on the surface of the substrate. On the other hand,
In the structure of the present invention shown in FIG. 9, the electric field concentration is
This occurs at the joint portion 22 between the substrates. That is, when LR is greater than a predetermined value, the breakdown voltage of the high voltage MOSFET is limited by the junction breakdown voltage between the drain and the substrate, and avalanche multiplication also occurs in this portion.

The length LR required of this high resistivity region 5 depends on the impurity concentration Na of the substrate, that is, the epitaxial layer 1' in FIG. Figure 10 shows Na 5X10 −
LR and B when changing between 3X10 cm
It shows the relationship between VDs. As is clear from the figure,
As Na decreases, the critical point of LR changes to a larger value. This is explained as follows. Area of the invention:
In other words, the drain breakdown voltage B is the junction breakdown voltage between the drain and the substrate.
In the region where VCl5 is limited, as Na decreases, the depletion layer extending to the substrate increases, and thus the drain breakdown voltage increases. On the other hand, in a region where the drain breakdown voltage BVDS is limited on the substrate surface, as Na decreases, the depletion layer formed on the substrate surface reaches below the edge of the gate electrode, and the depletion layer no longer extends. Since the drain voltage becomes smaller, the drain breakdown voltage of 87 fish decreases. That is, in FIG. 10, in the region where the drain breakdown voltage BVl)S is limited at the substrate surface, as the impurity concentration Na of the substrate increases, the slope of the curve increases. Therefore, the critical point, which is the intersection of each, increases as Na decreases. In implementing the present invention, it is necessary to consider the dependence of this critical point on the substrate impurity concentration.

Other embodiments of the present invention are shown in FIGS. 11 and 12. The basic structure is the same as the embodiments shown in FIGS. 4 and 6. However, in FIG. 11, drain region 3' is formed only of N-type high impurity concentration regions, and eleven N-type low impurity regions are interposed between gate electrode 7 and source region 3. The feature of this structure is that the manufacturing process is simplified and that even if the length of the gate electrode 7 is short, it can be manufactured with good yield. In FIG. 12, the substrate is composed of an N-type impurity semiconductor 12, a P-type buried region 13 having a high impurity concentration, and a P-type epitaxial growth layer 1'. This structure is suitable for integration, and bipolar transistors can also be placed on the same substrate.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto.

[Effects of the Invention] The present invention substantially reduces the resistance value of the substrate in a high breakdown voltage MO3FET, and increases the drain breakdown voltage to the drain voltage.
By adopting a structure determined by the junction breakdown voltage between the substrates, we have made it possible for the first time to prevent the negative feedback loop that occurs during avalanche multiplication and to prevent the negative resistance phenomenon that occurs after drain breakdown voltage breakdown.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional high-voltage MO8FET, and FIGS. 2 and 5 are diagrams for comparing the effects of the conventional example and the present invention.
Fig. 3 is a diagram for explaining the negative resistance phenomenon in a conventional high voltage MO8FET, Fig. 4, Fig. 6, Fig. 11,
FIG. 12 is an embodiment diagram of the present invention, and FIGS. 7, 8, 9, and 10 are diagrams for explaining the present invention. In the figure, 1 is the substrate, 1' is the epitaxial growth layer, 1' is the high impurity concentration substrate, 2 is the source region, 3' is the drain region, 4 is the train intermediate region, and 5 is the high ratio. Low resistance region, 6 is the gate insulating film, 7 is the gate electrode, 8 and 8' are the source electrodes, 9t is the drain electrode, Fig. 1, Fig. 2, and Z pressure VDs [V], Fig. 3, Fig. 4. Figure 7 Figure 51''2I Voltage VD5 [V] Figure 7 Figure 1-→ZR [/lL'In] $ 8 Figure 9u Figure 10 Figure 1θ0 Nos l Main (/θ''n:〃B-2. −″′β・
···· / the law of nature /
15 -3/JI10 C Guangnobu Higashi 200 1', -/ 3 Minoto-kou [Mukawa, Takasaki Factory, Hitachi, Ltd., 111 Nishiyokote-cho, Takasaki City, Inventor Yukio Shirota, 9-5 Noguchi-mae, Shiratori-cho, Toyokawa City, Toyokawa Factory, Hitachi, Ltd. Author: Hidefumi Ito Takasaki 111 Nishiyokote-cho, Hitachi, Ltd. Takasaki Factory, Hitachi, Ltd. Author: Shikano Ochi, 1-280 Higashi-Koigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory: Minoru Nagata, 1-280 Higashi-Koigakubo, Kokubunji City Inside the manufacturing center laboratory

Claims (1)

[Claims] 1. A source region and a drain region of a second conductivity type provided apart from each other on a semiconductor substrate of a first conductivity type, and a source region and a drain region of a second conductivity type formed on the semiconductor substrate between the source region and the drain region. an insulated gate type electric field comprising: a gate electrode provided on a part of the insulating film; and a high specific resistance region of a second conductivity type is formed in a surface portion of the substrate between the gate electrode and the drain region. In the effect transistor, the semiconductor substrate is
The high resistivity region is connected by ohmic contact to a semiconductor or conductor having a resistance value smaller than the resistance value of the semiconductor substrate, and the length L of the high specific resistance region is set to a predetermined value larger than the thickness Xp of the semiconductor substrate under the drain region. An insulated gate field effect transistor characterized in that the drain breakdown voltage is limited by the junction breakdown voltage between the drain and the substrate by setting the drain breakdown voltage to a certain value. 2. The insulated gate field effect transistor according to claim 1, wherein the semiconductor substrate is an epitaxial growth layer formed on the semiconductor. 3. The drain region is composed of a low resistivity region and an intermediate region having a higher resistivity than the region, and the thickness X− is the distance from the intermediate region to the semiconductor or conductor. An insulated gate field effect transistor according to claim 1 or 2.