JPS59130456A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable high speed actions and reduce the consumed power by a method wherein a well region formed necessarily on the substrate of a complementary MOS type integrated circuit is divided, and the device is arranged on on this region by selecting the propriety of impressing a high reverse directional voltage. CONSTITUTION:A plurality of P-channel type MOS transistors TrP's are formed on the substrate 1, and P type well regions 2 and 3 alienated from each other are formed on the substrate 1. A plurality of N-channel type MOS transistors TrN1 and TrN2 are formed on these region 2 and 3 respectively; an MOS element such as a memory cell to which a high reverse directional voltage is not impressed is formed on the region 2, and an MOS element to which the high reverse directional voltage is desired to be impressed is formed on the region 3. Then, one power source voltage VDD used in a main complimentary memory circuit is impressed on the substrate 1, the other power source voltage VSS on the well region 2, and a high power source voltage Vsub higher in the negative direction than the voltage VSS on the well region 3. Such a constitution enables to cause the memory cell of the well region 2 to well perform information memory, and to contrive to speed up the action because the junction capacitance becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device suitable for shortening data read time of a semiconductor memory.

[Technical background of the invention and its problems] In recent years, the development of large-capacity memories using MO8 type semiconductors has been remarkable, and high-density integration and high-speed operation have become major themes. Increasing the speed of MO8 type memory means shortening the data read time tACC, but this is true for memory that originally uses MOS transistors, which are voltage control elements.

tAC is the sum of the propagation delay times for charging and discharging the capacitance associated with all parts of each circuit.
Since C is determined, one approach to increasing speed is how to reduce stray capacitance.

Generally, in the case of MO8 integrated circuits, stray capacitance can be broadly divided into gate capacitance and diffusion capacitance.

It is well known that the diffusion capacitance is inversely proportional to the square root of the reverse voltage applied to the PN junction, and as the reverse voltage increases, the junction capacitance decreases. To achieve this, the reverse voltage applied to the MO8 integrated circuit board may be increased, but this does not solve the problem. In other words, in the case of a complementary MO8 type memory, the memory cell needs to statically hold the stored information when it is not operating, and the current consumption must be limited to only leakage current, so a high reverse voltage is applied to the substrate and the MOS transistor is It is not allowed to fluctuate the threshold voltage Vth.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that enables high-speed operation and low power consumption.

[Summary of the Invention] The present invention divides a well region that is inevitably formed on a complementary MO8 type integrated circuit board, and selects regions to which a high reverse voltage is allowed to be applied and regions to which it is not allowed. The present invention aims to provide a semiconductor device that enables high-speed operation by arranging the semiconductor devices in the same manner as described above, and also enables reduction of power consumption by applying the high reverse voltage mentioned above only when necessary. .

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In the figure, reference numeral 1 denotes an N-type substrate constituting a complementary MO8 type memory, and a large number of P-channel type MO8 transistors Trp are formed on this substrate 1. Further, P-well (P-type well) regions 2 and 3 are formed in the substrate 1 to be separated from each other. In these regions N and 3, a large number of N-channel MOS transistors TrN1 are provided.
, TrN2 is formed, but in region 2 an MO8 element such as a memory cell to which a high reverse voltage cannot be applied is formed, and in region 3 an MO8 element to which a high reverse voltage is to be applied is formed. Form. And on board 1, this complementary M
One power supply voltage VDD used in the OS memory circuit is applied, the other power supply voltage VSS is applied to the well region 2, and the power supply voltage Vsu higher in the negative direction than V8S is applied to the well region 3.
b is applied. In FIG. 1, 4 is a P-type diffusion layer, 5 is an N-type diffusion layer, 6 is a field oxide film, 7 is a gate oxide film, and 8 is an electrode wiring layer.

With this configuration, the memory cells in the well region 2 can store information well, and the well region 3 can also store peripheral circuits of the cell array, such as address decoder circuits, voltage sense circuits for memory output lines, buffer circuits, etc. The rate-limiting part of the readout time tACC such as (where tAC(,j)
1), the junction capacitance of this portion becomes small, and high-speed operation becomes possible. Also, the impurity concentration in the P-type well region is higher than that in the N-type substrate 1]
It is 0 times or more. Therefore, the junction capacitance within the P-type well region is several times larger than the junction capacitance within the N-type substrate 1, so N
If the junction capacitance in the P-type well region is reduced more than in the type substrate, the effect of improving the t ACC time will be greater.

FIG. 2 is an example in which the concept of FIG. 1 is applied to a decoder circuit of a complementary MO8 type memory.

The substrate potential of the P-channel type MO8) transistors 110 to 1I3 connected in series between the output terminal O and the ground (corresponding to Vss) is the voltage Vsub in FIG. Output terminal 0 and 'VD
N-channel MOS transistor 12 connected in parallel between D potential supply terminals. , 122 are formed on the substrate 1, so the substrate potential is the voltage VDD. In this way, the junction capacitance between the substrate sources and drains of the transistors 11o to 113 is reduced by the effect of the high voltage Vsub in the opposite direction, which can contribute to shortening tACC. In Fig. 2, AO""' A3 is the address signal, CE
indicates the chip enable signal.

3 and 4 are circuits for obtaining the voltage Vsub, and FIG. 3 is an unstable multivibrator circuit that oscillates a rectangular wave. When the chip enable signal CB is at a high level, this circuit oscillates a rectangular wave and supplies it from the output terminal 01 to the input terminal Il of the substrate bias generation circuit in FIG. 4, and when CB is at a low level, Stop the above square wave oscillation. In the circuit shown in Fig. g4, each time the square wave pulse supplied to the input terminal of the inverter 21 rises, the positive charge on the output terminal 02 side is drawn into the capacitor n side via the diode n, and the square wave pulse falls. A positive charge is discharged through the diode every time. By repeating this operation, there will be no positive charge on the output terminal 02 side, and a power supply voltage Vs ub, which is lower than the VSS (ground) potential, will be obtained at the output terminal 02.
This is used as the substrate voltage V s u b in the figure.

The supply of this voltage Vsub is controlled by the chip enable signal shown in FIG. 3, and since the rectangular wave oscillation stops when the signal CE is on the low level side, it is supplied only when necessary. As a result, the oscillation circuit shown in FIG. 3 stops operating when it is not required to operate, thereby making it possible to reduce power consumption.

FIG. 5 shows an embodiment in which the present invention is applied to a voltage sensing circuit of a complementary MO8 type memory. This circuit turns on (conducts) the transistors 311 and 312 by the chip enable signal CB, and connects the data output line BUS of the cell γ-ray.
, BO2 is precharged to 1'' level (VDD level). Note that 321 and 322 are high resistances.

Then, transistors 331 and 332, which have the timing signal φ3 as the gate input, supply the voltages of the output lines BU8 and BO2 to the parasitic capacitances at points 31 and 32, and if any of these voltages changes when reading data from the cell array, the transistors Voltage sensing is performed by turning on the voltage with the timing signal φ2 and inverting the flip-flop 35 to either one by the action of the transistors 1 and 362.

Thereafter, the output of the flip-flop is sent to the memory cell by transistors 37□ and 372 whose gates receive the timing signal φ1, and data is rewritten. Even in such a circuit, N-channel MO8) transistors 34, 36 . , 362, the aforementioned V
Since sub is supplied, the flip-flop operates at high speed, and N with Vsub as the substrate bias.
By performing high-speed rewriting using the channel transistors 37□ and 37□, it is possible to shorten tACC.

Further, in this circuit, since the transistors 331 and 332 are P-channel type, the timing signal φ0. Similar to φ2, φ3 also has the advantage that the voltage between VDD and ground can be varied in amplitude.

FIG. 6 shows an embodiment in which the present invention is applied to a complementary MO8 type memory cell. That is, in the above explanation, it was said that it was not allowed to use reverse voltages v and ub for the transistors that constitute the memory cell, but this applies to the cell body 41, and the N-channel MOS as a transfer element that transmits the cell output. Transistor 42. ．． Regarding 42□, it is shown that vsub may be applied to the substrate electrode of the transistor as long as the leakage current caused by this can be tolerated.

This will also help shorten tACC. FIG. 7 shows an example of application of the substrate bias circuit. This circuit is the input terminal
1 receives the launch output from 01 in FIG. 3, outputs the voltage Vsub when the chip enable signal CE is at a high level,
This circuit outputs voltage Vss when CE is at a low level.

Note that the present invention is not limited to the above embodiment, and for example, the N
It can also be applied when the type substrate is a P type substrate. In this case, since the well region is of N type, the transistor to which the voltage Vsub of the substrate electrode is applied becomes an N channel transistor.

[Effects of the Invention] As explained above, according to the present invention, the junction capacitance can be reduced without causing any problems in circuit operation.
--- 1. The data read time tACC can be greatly shortened, and the reverse voltage needed to reduce the junction capacitance can be selectively applied at a certain time.
A semiconductor device that can reduce circuit power consumption can be provided.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of a device showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a specific example of the same device, Figs. 3 and 4 are circuit diagrams for obtaining Vsub of the same circuit, 5 to 7 are circuit diagrams of applied examples of the present invention. l...N-type substrate, 2.3...P-type well region, vDD = VSS, vsub ""dl power supply voltage CE...chip enable signal 0

Claims (1)

[Claims] In an MO8 integrated circuit in which transistors (MOS) are integrated, a semiconductor substrate of a first conductivity type to which one of the power supply voltages of the integrated circuit is applied, and a semiconductor substrate of a first conductivity type formed on this substrate to which a power supply voltage of one of the integrated circuits is applied a first well region of a second conductivity type to which a power supply voltage is applied; and a second conductor formed in the substrate spaced apart from the well region and to which a voltage exceeding a range between the respective power supply voltages is applied. a second well region of the type, and means for selectively applying the other voltage to the region at a selected time. The other voltage is a voltage at which the junction capacitance formed in the second well region is smaller than the junction capacitance formed in the first well region, and the second well region has a MOS transistor in the first well region. ) MOS that requires higher speed operation than transistors
) A semiconductor device characterized by having a transistor arranged therein.