JPS59128733U - 3-V group compound semiconductor surface treatment equipment - Google Patents

3-V group compound semiconductor surface treatment equipment

Info

Publication number
JPS59128733U
JPS59128733U JP23884U JP23884U JPS59128733U JP S59128733 U JPS59128733 U JP S59128733U JP 23884 U JP23884 U JP 23884U JP 23884 U JP23884 U JP 23884U JP S59128733 U JPS59128733 U JP S59128733U
Authority
JP
Japan
Prior art keywords
compound semiconductor
surface treatment
group compound
container
treatment equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23884U
Other languages
Japanese (ja)
Other versions
JPS6322671Y2 (en
Inventor
渡辺 久恒
野口 今朝男
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP23884U priority Critical patent/JPS59128733U/en
Publication of JPS59128733U publication Critical patent/JPS59128733U/en
Application granted granted Critical
Publication of JPS6322671Y2 publication Critical patent/JPS6322671Y2/ja
Granted legal-status Critical Current

Links

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  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本考案を実施した一例を示す■−■族
化合物半導体の表面処理装置について、主に断面を示し
た説明図である。 図中、1.21は一連の手順が実施できる容器本体を2
,22は処理される■−■族化合物半導体ウェハーを、
3.23はウェハー支持台を、4゜7.25および27
はウェハー2.22の高さより高い容器1,21の位置
に設けられた導入排出パイプを、13は同じくウェハー
の高さより高い位置に設けられた導入排出口を、14は
容器の底部に設けられた導入排出口を、2Bは同じく容
器の底部に設けられた導入排出パイプを、12は分岐さ
れた導入排出パイプを、6.26は容器のフタを、32
は水を流すフタの中空部分を、5.8゜9.10,29
.30および31は種々の気体や蒸気や液体を制御する
バルブを示す。11. 24はウェハー支持台3.23
を加熱するためのヒータで容器内の温度を任意に制御す
る。
FIGS. 1 and 2 are explanatory diagrams mainly showing cross sections of a surface treatment apparatus for a ■-■ group compound semiconductor showing an example of implementing the present invention. In the figure, 1.21 indicates the container body in which a series of procedures can be performed.
, 22 represents the ■-■ group compound semiconductor wafer to be processed;
3.23 is the wafer support stand, 4°7.25 and 27
13 is an inlet/exhaust pipe provided at a position of the containers 1 and 21 higher than the height of the wafers 2 and 22, 13 is an inlet/exhaust port also provided at a location higher than the wafer height, and 14 is an inlet/exhaust pipe provided at the bottom of the container. 2B is the introduction/discharge pipe provided at the bottom of the container, 12 is the branched introduction/discharge pipe, 6.26 is the lid of the container, 32
The hollow part of the lid that drains water is 5.8°9.10,29
.. 30 and 31 indicate valves for controlling various gases, vapors, and liquids. 11. 24 is the wafer support stand 3.23
The temperature inside the container can be arbitrarily controlled using a heater.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 液体あるいは蒸気あるいは気体を満す上部にフタが設け
られた処理容器で、かつ上記液体あるいは蒸気あるいは
気体の導入および排出を兼ねる口もしくはパイプを少な
くとも2つ以上有し、該導入排出口もしくはパイプの少
なくとも1つが被処理ウェハーの上記容器内装填時の高
さ以上の位置に上記導入排出口もしくはパイプの先端が
設けられ、他の少なくとも1つの口もしくはパイプが上
記容器底部に設けられ、かつ上記各々の導入排出口もし
くはパイプに接続したパイバルブが設けられた処理容器
であることを特徴とするI−V族化合物半導体の表面処
理装置。
A processing container that is filled with liquid, vapor, or gas and has a lid on the top, and that has at least two or more ports or pipes that also serve as the introduction and discharge of the liquid, vapor, or gas; At least one of the inlet and outlet ports or the tip of the pipe is provided at a position higher than the height when the wafer to be processed is loaded into the container, and at least one other port or pipe is provided at the bottom of the container, and each of the above 1. A surface treatment apparatus for a group IV compound semiconductor, characterized in that the processing container is equipped with a pie valve connected to an inlet/outlet or a pipe.
JP23884U 1984-01-05 1984-01-05 3-V group compound semiconductor surface treatment equipment Granted JPS59128733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23884U JPS59128733U (en) 1984-01-05 1984-01-05 3-V group compound semiconductor surface treatment equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23884U JPS59128733U (en) 1984-01-05 1984-01-05 3-V group compound semiconductor surface treatment equipment

Publications (2)

Publication Number Publication Date
JPS59128733U true JPS59128733U (en) 1984-08-30
JPS6322671Y2 JPS6322671Y2 (en) 1988-06-22

Family

ID=30131994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23884U Granted JPS59128733U (en) 1984-01-05 1984-01-05 3-V group compound semiconductor surface treatment equipment

Country Status (1)

Country Link
JP (1) JPS59128733U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001830A1 (en) * 2002-06-25 2003-12-31 Tokyo Electron Limited Substrate processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001830A1 (en) * 2002-06-25 2003-12-31 Tokyo Electron Limited Substrate processing device

Also Published As

Publication number Publication date
JPS6322671Y2 (en) 1988-06-22

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