JPS5912804Y2 - Push-pull type output buffer circuit using MOST - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a push-pull output buffer circuit using an insulated gate transistor (simply referred to as MO3T in this invention).

As shown in Fig. 1, the push-pull type output circuit using MO8T has the output MO8T, T, T2 connected in series with the power supply VD, and both MO8T(Ti)(T
The middle point of connection 2) constitutes an output terminal OUT, which is connected to an external circuit.

In such a configuration, gates G1 . One of G2 is at low level, and both cannot be at high level at the same time.

When G1 is at high level, G2 is at low level.
At that time, a low level output signal is obtained at the output terminal OUT, and in the opposite case, a high level output signal is obtained.

However, when G□ is low level and 62 is high level, and a high level output signal is obtained at the output terminal OUT,
If the output terminal OUT is short-circuited to the ground potential due to incorrect operation of the external circuit, this MO3T (T1
)(T2) is a large one because it constitutes the output MO3T, that is, the gain factor (GAINFACTOR)
Since it is large, a large current flows through MO3T and T2, and the power consumption there becomes large.

For example, the internal resistance of MO3T and T2 when conducting is 50Ω,
If the power supply VD is 5■, this MO3T, T2
The power consumption is 0.5W.

Generally, a large number of such output circuits exist in one LSI, and if there are, for example, 16 sets, the power consumption of this output circuit alone reaches as much as 8W.

Normally, the power consumption of an entire LSI is around 1W at most, but if the thermal resistance of the LSI package is 60C/W, the LSI will reach a very high temperature in this case, and the threshold voltage and gain factor will change significantly. , changes in the characteristics of the LSI,
It may cause deterioration.

The present invention has been devised in view of these points, and will be described in detail below with reference to FIG. 2.

FIG. 2 is a circuit diagram showing an embodiment of the output buffer circuit of the present invention, in which MO3Ts and T1 to T9 shown in the figure are all N-channel enhancement type, the threshold voltage is 1, and the power supply is VD. is 5■, and the auxiliary power supply vD' is 12■.

IV is MO8T (Ta) (T4) (Ts)
In the bootstrap type inverting circuit consisting of capacitors C1 and C2, an input signal IN is applied to the gate of MO3T (T3), and an inverted signal IN which is an inversion of this signal IN is applied to the gate of MO3T (T3).
is obtained from the connection point of MO8T (T3) and (T4).

This inverted signal IN is applied to the gates of the first outputs MO3T and T2, and the input signal IN is directly applied to the gate of the second output MO8T (T1).
O3T(T1)(T2) constitute a push-pull type output buffer circuit, and the connection midpoint of both MO8T(T, )(T2) is set as output terminal OUT.

VC is a voltage compensation circuit consisting of five MO5Ts (T6) to (Tlo), and even though the potential of the output terminal OUT is internally at a high level, it is forced to a low level from an external circuit. , the inverted output signal I of the inverting circuit IV
It functions to lower the level of N and reduce the excessive current flowing to the first output MO3T (T2).

A more detailed configuration of this voltage compensation circuit VC will be described below.

MO8T (Tlo) placed between the auxiliary power supply vD' and the output terminal of the inverting circuit IV, and MO3T (Tlo) placed between the output terminal of the inverting circuit IV and the connection midpoint of the output MO3T (T1) (T2). T, ) and both capacitors C of the inverting circuit IV
1. MO8T (T8) between the center of C2 and the connection midpoint of output MO5T (T1) (T2), and the power supply ■.

The two MO8T (T7) (T6) connected in series between the output MO3T (T1) (T2) and the connection midpoint of the output MO3T (Tg) (Ts) (
The gates of T9) are connected together to form MO8T(T6)(
It is connected to the connection midpoint of T7).

Furthermore, the gain factor of MO3T (T6) is MO5T (
T7) is set more than 20 times higher than that of M
The gain factor of O8T (TIO) is M of inverting circuit IV.
It is selected to be smaller than that of O8T (T3).

Therefore, when the input signal IN is at a high level, the inverting circuit ■V
MO5T (T3) of the circuit Iv is turned on, the inverted output signal IN of the circuit Iv is at low level, and the first output MO3T (T3) of the circuit Iv is turned on.
2) is turned OFF, while the second output MO8T (T1)
Since the high level input signal IN is directly applied to , this MO8T (T1) is ON and the output terminal OUT
A low level output signal is obtained.

At this time, the voltage compensation circuit VC operates as follows.

The gain factors of MO3T (T6) (T7) are as described above. Since T6 is set larger, both M
The potential at the connection midpoint of O8T (T6) (T7) is for each MO
It is higher than the threshold voltage of 8T, and as a result, MO8T (
T6) ('rs) (T9) are all turned on, and the inversion circuit IV
Since it acts in the direction of lowering the potential at the output terminal of , it has no effect on the fact that the output terminal OUT is at a low level.

Also, MO3T (Tlo) is also ON, but MO3T (Tlo) is also ON.
Since the gain factor is selected to be smaller than that in 3), it hardly affects the fact that the inverted output signal IN is at a low level.

On the other hand, when the input signal IN is low level, the inverted output signal IN is high level, and the first output MO8T (T2)
is ON, while the second output MO8T (T1) is OF
At F, a high level output signal is obtained at the output terminal OUT.

Since this high level is higher than the threshold voltage of each MO5T, MO8T (T6) (T8) and (T, ) of the voltage compensation circuit VC are turned OFF and have no effect on the high level of the output signal.

Next, consider a case where the input signal IN is at a low level and a high level output signal is obtained at the output terminal OUT, and this terminal OUT is forcibly grounded from an external circuit.

Since the connection midpoint of MO8T (T6) (T7) of the voltage compensation circuit VC is higher than the threshold voltage of each MO3T, MO8
T (T8) (T, ) is turned on, and 12 of the auxiliary power supply vD' is turned on by the bootstrap capacitor C2 of the inverting circuit IV.
The voltage at the terminals of this capacitor C2, which was slightly higher than V, is reduced by the discharge path through MO8T (T8).

The time constant of this terminal voltage drop is the ON state of MO8T (T8).
It is determined by the internal resistance at the time and the capacitance of capacitors C1 and C2.

As the terminal voltage of capacitor C2 decreases, the potential at the output end of inverting circuit IV decreases through capacitor C2.

If the potential at this output end drops from 12V of the auxiliary power supply VD' to, for example, 5V, the first output MO8T (T2)
The current flowing through the circuit decreases approximately.

Therefore, the internal resistance when MO5T (T8) (T9) is ON,
In addition, by increasing the capacitance of capacitors C0 and C2, the current amount of output MO3T (T2) can be reduced to a round value over a period of 1 μs or more, and this internal resistance and capacitor can be used as a kind of delay circuit. The short-time large current that occurs during transient periods is absorbed by this delay circuit, which prevents malfunctions.

When the forced grounding of the output terminal OUT by the external circuit was released, the first output MO8T (T2) was not completely OFF, and MO5T (T5) of the inverting circuit IV MO5T of voltage compensation circuit VC
(T8), MO5T (Tlo) and (T9) and MO8
The output MO5T (
A current flows into the connection midpoint of T1) (T2), returning the level of this midpoint, that is, the output terminal 0UT) to the current level.

MO5T (T8) (T9) of the voltage compensation circuit VC turns OFF when the potential of the output terminal OUT rises to a level higher than that.

Therefore, when the forced grounding to the output terminal OUT is released, the output terminal OUT returns to the original high level, allowing the original buffer circuit to operate.

As is clear from the above explanation, the present invention has a voltage compensation circuit between the inverting circuit and the output terminal, so if the output terminal is forcibly grounded from the external circuit when it is at a high level, the output MO8T The excessive current that flows is automatically reduced, the power consumption at the output MO8T does not increase abnormally, the LSI becomes hot, and troubles such as characteristic changes and deterioration are completely eliminated.

Furthermore, since the voltage compensation circuit used in the present invention includes a detour, it will not operate under short-term excessive currents such as transient conditions, and the voltage compensation circuit used in the present invention will only operate effectively when an abnormal situation occurs. However, under normal conditions, there is no adverse effect on the original operation.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a conventional output circuit, and FIG. 2 is an electric circuit diagram of a circuit according to the present invention, in which T represents MO8T, IV represents an inverting circuit, and VC represents a voltage compensation circuit.

Claims (1)

[Claims for Utility Model Registration] A bootstrap type signal inversion circuit that inverts an input signal, and a first output MO5 to which the output signal of the inversion circuit is applied.
A push-pull type using MO8T, which consists of a second output MO8T and a second output MO8T to which the above input signal is applied, and this surface output MO8T is connected in series with the power supply, and the midpoint of the connection is used as the output terminal. In the output buffer circuit, two MO8Ts are connected in series between the power supply and the connection midpoint of the above output MO8T, and the gain factor on the connection midpoint side is set larger than that on the power supply side, and the above signal. MO8T connected between the output of the inversion circuit and the connection midpoint of the output MO3T, and MO8T connected between one end of the bootstrap capacitor of the signal inversion circuit and the connection midpoint of the output MO8T.
The middle point of the connection between the two MO8Ts of the voltage compensation circuit is connected to the gates of the remaining two MO8Ts, and this voltage compensation circuit is connected to the above inverting circuit and the output MO3T. The voltage compensation circuit is provided between the connection center point and the connection center point, and when the connection center point is forced to a low level from an external circuit while the potential of the connection center point is high level, the output of the inverting circuit is controlled by this voltage compensation circuit. A push-pull type output buffer circuit using MO8T, which is characterized by lowering the signal level and reducing the current flowing to the output MO8T.