JPS591275U - Composite synchronous signal regeneration circuit - Google Patents

Composite synchronous signal regeneration circuit

Info

Publication number
JPS591275U
JPS591275U JP9577382U JP9577382U JPS591275U JP S591275 U JPS591275 U JP S591275U JP 9577382 U JP9577382 U JP 9577382U JP 9577382 U JP9577382 U JP 9577382U JP S591275 U JPS591275 U JP S591275U
Authority
JP
Japan
Prior art keywords
synchronization signal
noah
gate
pseudo
composite synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9577382U
Other languages
Japanese (ja)
Inventor
縫村 義己
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP9577382U priority Critical patent/JPS591275U/en
Publication of JPS591275U publication Critical patent/JPS591275U/en
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

笹1図は従来方式による映像とコンピュータからの文字
出力を重畳表示するシステムのブロック図、第2図は本
考案の実施例に係る複合同期信号 3再生回路を示す回
路図、第3図は第2図の回路の各点における信号波形を
示す動作波形図である。 7・・・同期分離回路、10・・・フライバックトラン
ス、13・・・垂直出力回路、23・・・第1微分回路
、27・・・第2微分回路、24. 25. 28. 
29゜32.36・・・インバータ、26.30.31
゜33・・・ノアゲート、35・・・整流回路。
Figure 1 is a block diagram of a conventional system for superimposing display of video and character output from a computer, Figure 2 is a circuit diagram showing a composite synchronization signal 3 reproduction circuit according to an embodiment of the present invention, and Figure 3 is a block diagram of a system for superimposing display of video and character output from a computer. FIG. 3 is an operational waveform diagram showing signal waveforms at each point of the circuit in FIG. 2; 7... Synchronous separation circuit, 10... Flyback transformer, 13... Vertical output circuit, 23... First differentiating circuit, 27... Second differentiating circuit, 24. 25. 28.
29°32.36...Inverter, 26.30.31
゜33... Noah gate, 35... Rectifier circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ブラウイ管の映像に重畳して別システムから送出される
文字出力を表示するために必要な複合同期信号を再生す
る回路であって、水平ブランキングパルスを微分回路及
びインバータにより疑似水平同期信号とし、又垂直ブラ
ンキングパルスを微分回路及びインバータにより疑似垂
直同期信号とし、夫々を第1ノアゲートに入力して両者
のノアを取る一方、前記両疑似信号をインバータにより
、   再反転し第2ノアゲートに入力してノアを取り
、この第2ノアゲート及び第1ノアゲートの両川力を第
3ノアゲートでノアを取り、更にこの第3ノアゲートの
出力を、映像信号中に含まれる複合同期信号で制御し、
複合同期信号の有無に対応した疑似複合同期信号を得る
ようにしたことを特徴とする複合同期信号再生回路。
This is a circuit for reproducing a composite synchronization signal necessary for displaying a character output sent from another system superimposed on a Blouie Tube image, which converts a horizontal blanking pulse into a pseudo-horizontal synchronization signal using a differentiating circuit and an inverter, Further, the vertical blanking pulse is made into a pseudo vertical synchronizing signal by a differentiating circuit and an inverter, and each is inputted to the first NOR gate to take the NOR of both, while the above-mentioned two pseudo signals are re-inverted by the inverter and inputted to the second NOR gate. taking a Noah from the second Noah gate and the first Noah gate, taking a Noah from a third Noah gate, and further controlling the output of the third Noah gate with a composite synchronization signal included in the video signal,
A composite synchronization signal reproducing circuit characterized in that a pseudo composite synchronization signal corresponding to the presence or absence of a composite synchronization signal is obtained.
JP9577382U 1982-06-28 1982-06-28 Composite synchronous signal regeneration circuit Pending JPS591275U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9577382U JPS591275U (en) 1982-06-28 1982-06-28 Composite synchronous signal regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9577382U JPS591275U (en) 1982-06-28 1982-06-28 Composite synchronous signal regeneration circuit

Publications (1)

Publication Number Publication Date
JPS591275U true JPS591275U (en) 1984-01-06

Family

ID=30228552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9577382U Pending JPS591275U (en) 1982-06-28 1982-06-28 Composite synchronous signal regeneration circuit

Country Status (1)

Country Link
JP (1) JPS591275U (en)

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