JPS5912652A - Synchronizing circuit of viterbi decoder - Google Patents

Abstract

PURPOSE:To attain the synchronism of a code word at a decoder itself, by discriminating whether or not a path exists between states corresponding to the maximum metric discriminated at a different time for switching the phase. CONSTITUTION:A signal to be decoded inputted to a terminal 100 is supplied to a Viterbi decoder 200 through a phase shifter 10, and a signal decoded from a terminal 101 is outputted. A metric of each internal state at each point of time of the decoder 200 is given to a maximum metric discriminating circuit 20 of the synchronizing circuit and a status number having a metric is fed to a register 30 as an input signal at the same time, then a path discriminating circuit 40 discriminates whether or not a path exists between a state having a maximum metric at the past point of time and a state at other point of time including the present point of time. As a result, the signal is integrated and compared and the phase generating the maximum integral value in the signal is discriminated as the phase of the synchronizing state, allowing to discriminate the synchronism/asynchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit for a Viterbi decoder.

In digital communications, one of the methods for reducing transmission errors is a Viterbi decoder. The principles and operation of the Viterbi decoder were published in March 1973 by the U.S. I.I.
Proceedings published by IBIJ (IBIJ).

ceedings of IEBE) Volume 61, No. 3
The paper “The Viterbi Algorithm” is published on pages 268 to 278 of the issue.
Alg.

-rithm).

In order to operate the Viterbi decoder, on the transmitting side, a transmission code is encoded in a predetermined method and transmitted as a code word. On the receiving side, codewords are extracted in synchronization with the encoding on the transmitting side and input to the Viterbi decoder. Conventionally, a synchronization signal from an external system, such as a PCM frame L/-frame synchronization signal, has been used for this synchronization. However, this conventional method has the disadvantage that the synchronization circuit must be designed for each system because the formation of the synchronization signal differs from system to system. Furthermore, it is difficult to apply the Viterbi decoder to systems where it is difficult to obtain a frame synchronization signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit capable of synchronizing code words in a Viterbi decoder itself, while eliminating the drawbacks of the conventional method.

Hereinafter, the configuration and operating principle of the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoder to which a synchronization circuit according to the present invention is added. The decoded signal input to the terminal 100 is passed through the phase shifter 10 and sent to the ViterPi decoder 2.
00 is applied to the decoded signal input terminal 104. terminal 1
The decoded signal is output to 01. The maximum metric determining circuit 20 in the synchronization circuit of the present invention has the internal states of the Viterbi decoder 200 at each point in time, and the register 30 receives as an input signal the state number having the metric. Then, the state number having the metric determined to be the maximum metric by the maximum metric determination circuit is set in the register 30.

In the path determination circuit 40, the state with the maximum metric at the past time and the state with the maximum metric at other times including the present time are determined.
It is determined whether or not a bus exists between X5 degrees and the state with vines, and a signal indicating the determination result is applied to the integrator 50 and integrated.

The integral output of the integrator 50 is applied to a maximum value determiner 60. The maximum value determination result is applied to the phase memory 70, and the phase memory stores the phase at the time of maximum value determination. Phase memory device 7
A zero output is applied to one terminal of switch 80. A movable armature of the switch 80 is connected to a phase shift amount control terminal 103 of the phase shifter 10.

The switching signal generator 90 converts the phase control signal to the maximum value judgment value 60.
1 phase memory 70. and the other terminal of the switch 80, and generates a switching signal for the switch 80.

As shown in the example below, the transmission code for Viterbi decoding is such that for each information bit that is sequentially input to the transmitter, a plurality of bits that depend on a plurality of past information bits are output bits, jli The following output should not be configured,
The synchronization signal c
A signal (hereinafter simply referred to as a word synchronization signal) is applied to terminal 105. The word synchronization signal is passed through phase shifter lO to terminal 106.
and supplied to the Viterbi decoder 200.

A portion 200 surrounded by a broken line in FIG. 1 shows the basic configuration of a Viterbi decoder. The "state" specified by the generator 202 is configured using, for example, a counter. The metric domain of the branch is
Hot search from metric storage 205 □ 〇 branch selection which is added by adder 203 to the metric value corresponding to the specified state number outputted! 4204 selects a branch showing a large metric for each state from the metric values of each school inputted from the adder 202, supplies the selected metric to the metric storage 205, and outputs it to the synchronization circuit. The transmission bits corresponding to the branches well selected by the branch selector 204 are stored in the bus memory 206 and output to the transmission bits 101 corresponding to the converged branches.

FIG. 2 is a block diagram showing an example of an encoder that is part of the Viterbi decoder. Restraint length 3. A convolutional encoder with a coding rate of 10 is shown. The digital signal applied to the terminal 301 is 1
Each signal input is sequentially stored in shift registers 302-304. The outputs of the shift registers 3o2 303 and 304 are applied to a first exclusive OR circuit 305, and its output is output to a terminal 306.

The outputs of the shift registers 302 and 304 are applied to a second exclusive OR circuit 307, and its output is output to a terminal 308. The signals at terminals 306 and 308 become convolutional codes. This convolutional code may be transmitted as is as a two-column digital signal, or it may be converted into a serial signal by the parallel-to-serial converter 401 shown in the block diagram of FIG. 3 and then transmitted. .

The signals at terminals 306 and 308 in FIG. 2 are respectively applied to terminals 406 and 408 in FIG.
01 is converted into a second alignment signal and outputted to the terminal 402.

FIGS. 4(a), 4(b), and 4(C) are conceptual diagrams showing the state of synchronization when transmitted as a serial signal. (a) in the figure shows a signal applied to the terminal 301, and a new digital signal is applied every 2T. FIG. 3B shows the signal at the terminal 402 that has been convolutionally encoded and converted into a serial signal by the parallel-to-serial converter of FIG.

Since the coding rate is -F, a digital signal is output every T. On the receiving side, the signal (b) must be correctly applied to the Viterbi decoder at 1 word and 17 every 2T. If the separation between one word is shifted by T as shown in the same figure (C), there will be 6 words (1', 2).

(2,' 3)......, which has a different word structure from the original words (1, 1'), (2, 2')... , because Viterbi decoding is performed, correct decoding results cannot be obtained.

Note that even when the signal from terminal 306.3 (18 in FIG.
If a pair such as (terminal 3o8.terminal 3o6) is not received correctly in a pair of terminals 308 and 308, it will not be correctly decoded.

The signal at the terminal 402 is applied to the terminal 100 in FIG. 1 via a transmission path, and by observing whether there is a path between states with the maximum metric as in the present invention, the correct word structure can be established. That is, the ability to determine synchronization will be explained by taking as an example a case where the signal-to-noise ratio is good.

Figures 5a and 5b show trellis diagrams of the Viterbi decoder. FIG. 5(a) is an example of a trellis diagram when synchronized, and FIG. 5(b) is an example of a trellis diagram when not synchronized.

In Figure 5 (a) and (b), the black dot is the largest point) 1
Indicates a "state" with one mark, the thick line is the maximum number) II
Indicates the selected path for the book.

In the case of synchronization, the trellis of the path regarding the maximum metric is continuous, as shown in FIG. 5(a), and the maximum metric is the maximum value that the branch metric can take.

On the other hand, when it is not synchronized, it is almost equivalent to when the error in the transmission path is 50%, and as shown in Figure 5 (b), the sock trellis is not continuous. There are many cases.

If the trellis is not continuous in this way, it means that the metric of the next "state" leading to the "state" with the largest metric becomes the largest in the next time slot.

Therefore, when the states are synchronized, the percentage of paths that exist between the "states" with the maximum metric is large, and when they are not synchronized, the percentage is small. Therefore, by integrating the output of the path determination circuit 40 by the integrator 50 and obtaining all possible phases while removing fluctuation components, it is possible to determine whether the output is synchronous or asynchronous.

The process of the determination operation will be explained in more detail using the drawings.

Assume that a signal at terminal 402 is applied to terminal 100 in FIG. Assume that the Viterbi decoder starts operating and establishes synchronization at 19 weeks. At this time, the switching signal generator 90 generates a signal to turn the switch 80 downward, as shown by the broken line 1) in FIG. At the same time, as shown in the fruit J of (a), t. -1, the phase 10 phase control sends signals from 60 to 80.

Figures 6 (a), (b), (C), and (d) are conceptual diagrams for explaining the synchronization and asynchronous states.

The output of the integrator 50 changes as shown in FIG. 6(b).

interval t. Maximum value determiner 6 at eel end time t of -11
0 detects the integrator output m, stores it as the maximum value, and emits a signal for storing the phase in the first memory 70. As a result, phase 1 is stored in the phase memory. Next 1. -1. The switching signal generator sends a phase 2 signal from 60 to 80 within the range . The integrator output at this time changes as shown in FIG. 6(b). The maximum value judge is t
, the integrator output ml is detected and the previous value m
m compared to 1! is larger. The phase recorder/M unit 70 stores the phase 2 based on this determination result.

In this example, since there are two possible phase shapes of the convolutional code, the ratio axis process based on the maximum metric and minimum metric for all phases ends at time t. The switching signal generator 18 generates a switching signal IS-ji which causes the switch 80τ to be turned down as shown by the broken line in FIG.

FIG. 7 and FIG. 8 are block diagrams showing the first and second embodiments of the stabilizer, respectively.

In FIG. 7, the decoded signal at the end "Floo"
1 and output to terminal 104.

The word synchronization signal at terminal 105 is output as is to terminal 106, and the relative time relationship between the decoded signal and the word synchronization signal is adjusted. In FIG. 8, the decoded signal at terminal P100 is output as is to terminal 104. The word synchronization signal at terminal 1050 is phase-shifted by phase shift element 801 and output to terminal 106.

The above explanation has proceeded on the assumption that the signal to be decoded is a serial signal, but if the Viterbi decoder is configured to input parallel signals, Figure 9 shows the manual input to the Viterbi decoder. It is a block diagram showing an example of a phase shifter when -18 days are parallel. Switch 90 to connect the input signals of terminals 901 and 902 to switch 90.
3. Can be replaced by 904 1 positive and 1 tiger 90 (3
.

Although this embodiment has been described as synchronizing with the coding rate H numbers, it is clear that the present invention can also be applied to cases of other coding rates. moreover,
When the encoded signal is multiphase phase modulated and transmitted once, the carrier phase has the maximum metric, and even when there is uncertainty, the carrier phase has the highest proportion. By calculating the carrier wave phase, uncertainty in the carrier wave phase can be removed.

As described above in detail, the Viterbi decoder avoidance circuit according to the present invention enables word synchronization in the Viterbi decoder itself without using a synchronization signal from an external system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a synchronization circuit according to the present invention and a Viterbi decoder incorporating the same, FIG. 2 is a block diagram showing an example of a convolution encoder, and FIG. 3 is a block diagram showing an example of a convolution encoder. A block diagram showing a series transformer, Fig. 6 (
a), (b), (C), and (d) are 1. A conceptual diagram for explaining the signals of each part in FIG. 1, and FIGS. 7 to 9 are book diagrams each showing an example of a phase shifter. In the figure, lO is a phase shifter, 20 is a maximum met 1 knock determination circuit,
30 is a register, 40 is a bus determination circuit, 50 is an integrator, -60 is a maximum i1a determination circuit 70 is a phase memory,
80 is a switch, 90 is a switching signal generator, and 103 is a phase shift control terminal, respectively.

Claims (1)

[Claims] In a Viterbi decoder having a decoded signal input terminal, a decoded signal output terminal, an output terminal for a state number representing a possible internal state, and an output terminal for a +1 value corresponding to the state of the state number, A phase shifter having a phase shift amount control terminal, a circuit for inputting each of the above-mentioned metric values, a circuit for determining the maximum value (IJ book), and a circuit for determining the maximum value), storing the above-mentioned state number of the state corresponding to +1 vine. a bus judgment circuit for determining whether a /toss exists between the states corresponding to +1 vine, and an integrator whose input is the output of the judgment circuit; a maximum value judger which takes the integrator output as an input signal; a phase memory which stores the phase at the time of this maximum value judgment; the output of this phase memory is input to one selected terminal, and the selected terminal is A switch connected to the phase shift amount control terminal of the phase shifter and a phase control signal are supplied to the maximum value determiner, the phase memory and the other selected terminal of the switch, and a switching signal of the switch is supplied. A synchronous circuit for a Viterbi decoder, characterized in that the signal to be decoded is used as an input signal of the phase shifter, and the output signal of the phase shifter is used as an input signal of the Viterbi decoder.