JPS59126325A - Selective driving circuit - Google Patents
Selective driving circuitInfo
- Publication number
- JPS59126325A JPS59126325A JP25483A JP25483A JPS59126325A JP S59126325 A JPS59126325 A JP S59126325A JP 25483 A JP25483 A JP 25483A JP 25483 A JP25483 A JP 25483A JP S59126325 A JPS59126325 A JP S59126325A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- diode
- grounded
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001052 transient effect Effects 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
Landscapes
- Electrophotography Using Other Than Carlson'S Method (AREA)
- Electronic Switches (AREA)
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、選択駆動回路、特に多針電極を用いる静電記
録装置のその針電極を選択駆動するだめの回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selective driving circuit, and particularly to a circuit for selectively driving needle electrodes of an electrostatic recording apparatus using multi-needle electrodes.
静電記録装置は、電気信号を多針電極に書画状に印加す
ることによp記録体上に静電潜像を記録作成するもので
ある。この記録に際しては、電極を走査せずに電極に与
える信号を走査するようにすれば、記録速度が高速とな
ることから、最近ではこの記録方式が専ら用いられてい
る、ところで、この記録方式によると、高速度で選択さ
れた電極に所定の高電圧全印加すること、選択駆動回路
がその集積化上低消費電力の回路構成であることが必要
である。An electrostatic recording device records and creates an electrostatic latent image on a p-recording medium by applying electric signals to multi-needle electrodes in a calligraphic pattern. In this recording, if the signal applied to the electrode is scanned instead of scanning the electrode, the recording speed becomes faster, so this recording method has been exclusively used recently. In addition, it is necessary to apply a full predetermined high voltage to the selected electrodes at high speed, and the selection drive circuit must have a circuit configuration with low power consumption due to its integration.
しかし、従来のこの褌の選択駆動回路では、制御入力に
対する出力電気信号の立上りが遅いという欠点を有して
いる。これは、微小電圧の制御入力を以て高電圧の電気
信号の出力状態を制御するには、何等かのスイッチング
素子回路が介在せしめられるが、このスイッチング素子
回路の特性彦どに起因して出力の電気信号にその影響が
あられれるからである。However, this conventional loincloth selection drive circuit has the drawback that the rise of the output electric signal relative to the control input is slow. In order to control the output state of a high-voltage electrical signal using a micro-voltage control input, a switching element circuit of some kind is required, but due to the characteristics of this switching element circuit, the output electrical This is because the signal will be affected.
第1図は、従来のこの種の選択駆動回路の回路構成例を
示したものである。これによると、トランジスタTRI
がオン状態にあるとき、ツェナーダイオードD1によっ
てトランジスタTR2のペースにはツェナー電圧が印加
され、そのエミッタはダイオードD2に介して印加され
る■2によυペースに対して逆バイアスがかかった状態
となっておりトランジスタTR2はオフ状態にある。一
方、トランジスタTRIがオフ状態にあるときは、トラ
ンジスタTR2のペースには電源V、よシ抵抗R1を介
してペース電流が供給されるので、トランジスタTR2
はオン状態となる。この場合、トランジスタTR2がオ
フ状態よりオン状態となるとき、すなわちダイオードD
2.D3の中間接続点0が電圧値v2より V、に変化
する時にトランジスタTR2のペースに供給される電流
は上記抵抗R1を介して供給されるのみであり、またダ
イオードD3が存在することにより、このダイオードD
3のスイッチング動作による高速化の限界があった。FIG. 1 shows an example of the circuit configuration of a conventional selection drive circuit of this type. According to this, the transistor TRI
When is in the on state, a Zener voltage is applied to the pace of the transistor TR2 by the Zener diode D1, and its emitter is reverse biased with respect to the υ pace by ■2 applied through the diode D2. Therefore, the transistor TR2 is in an off state. On the other hand, when the transistor TRI is in the off state, the pace current is supplied to the pace of the transistor TR2 via the power supply V and the resistor R1, so the pace current is supplied to the pace of the transistor TR2.
is in the on state. In this case, when the transistor TR2 changes from the off state to the on state, that is, the diode D
2. When the intermediate connection point 0 of D3 changes from the voltage value v2 to V, the current supplied to the pace of the transistor TR2 is only supplied through the resistor R1, and the presence of the diode D3 prevents this. Diode D
There was a limit to how high the speed could be increased due to the switching operation of No. 3.
本発明は上記の点に鑑みなされたもので、上記0点で高
速スイッチングを行なうためダイオードD3を取り外す
と共にトランジスタTR2のエミッタ・ペース間にダイ
オードを挿入することにより高速立上がりパルスの供給
を可能とする選択駆動回路を提供することを目的とする
。The present invention has been made in view of the above points, and in order to perform high-speed switching at the 0 point, the diode D3 is removed and a diode is inserted between the emitter and pace of the transistor TR2, thereby making it possible to supply a high-speed rising pulse. The object of the present invention is to provide a selection drive circuit.
本発明の最適な実施例回路を第2図に示す。図に示すよ
うにトランジスタTR2のエミッタ・ベース間にダイオ
ードD4を挿入した。これによりトランジスタTR2の
オフよりオン状態となる時すなわちトランジスタTRI
のオン状態よりオフ状態となる時に抵抗R1を介して電
流を供給すると共にTRI 、Dl 、TR2の過渡現
象に対してダイオードD4を介して電流を供給し、TR
2のオフ時にペース・エミッタ間に高電位の逆バイアス
がかかるのを防止したスイッチング回路の高速化を実現
した。A preferred embodiment circuit of the present invention is shown in FIG. As shown in the figure, a diode D4 was inserted between the emitter and base of the transistor TR2. As a result, when the transistor TR2 is turned on from off, that is, the transistor TRI
A current is supplied through the resistor R1 when the state changes from the on state to the off state, and a current is supplied through the diode D4 in response to the transient phenomena of TRI, Dl, and TR2.
The speed of the switching circuit has been increased to prevent high-potential reverse bias from being applied between the pace emitter and the pace emitter when the 2 is turned off.
これにより第1図に示す回路のツェナーダイオードのツ
ェナー電圧を5V、V、を400V、V2を7■とした
場合、0点の約+6Vより+400■への立上りが約5
μ秒であったものが第2図の回路構成とすることに゛よ
り約3μ秒となった。さらにエネルギー蓄積要素である
コンデンサC1をツエナーダイオードD1の両端に接続
した第3図の構成’に取やトランジスタのスイッチング
時の過渡時にこのコンデンサC1よシエネルギーを供給
することにより、ツェナーダイオードD1の特性に左右
されることの少ない高速のスイッチング回路が実現し、
前記同様のV+ 、V2 、D 1にて立上りが約1μ
秒に減少し非常に高速でのスイッチング回路が実現した
。As a result, if the Zener voltage of the Zener diode in the circuit shown in Figure 1 is 5V, V is 400V, and V2 is 7■, the rise from the 0 point of approximately +6V to +400■ is approximately 5V.
By using the circuit configuration shown in FIG. 2, the current time was reduced to about 3 microseconds. Furthermore, in the configuration shown in Fig. 3 in which a capacitor C1, which is an energy storage element, is connected to both ends of the Zener diode D1, the characteristics of the Zener diode D1 can be improved by supplying energy from the capacitor C1 during transient switching of the transistor. A high-speed switching circuit that is less affected by
The rise is about 1μ at V+, V2, and D1 as above.
A switching circuit with extremely high speeds reduced to seconds has been realized.
定電圧源としてはツェナーダイオードD1に変えてダイ
オードの直列接続また抵抗分割によって定電圧を得ても
同様の効果が得られることはもちろんである。Of course, the same effect can be obtained by using a series connection of diodes or resistance division to obtain a constant voltage instead of using the Zener diode D1 as a constant voltage source.
またトランジスタに変えてFET 、VMO8。Also, replace the transistor with a FET, VMO8.
5MO8等で等節回路を形成しても同様である。The same is true even if an equal node circuit is formed using 5MO8 or the like.
また本発明は静電記録の多針駆動回路を例にとって説明
したが広くスイッチングを行なう回路構成に応用できる
ことももちろんである。Further, although the present invention has been described by taking a multi-stylus drive circuit for electrostatic recording as an example, it is of course applicable to a wide range of circuit configurations that perform switching.
以上説明した様に簡単な回路構成により極めて高速での
スイッチング回路が実現した。As explained above, an extremely high-speed switching circuit has been realized with a simple circuit configuration.
第1図は従来の回路側図、第2図は本実施例の選択駆動
回路図、第3図は他の実施例の選択駆動回路図である。
図において、Dl・・・ツェナーダイオード、D2〜D
4・・・スイッチングダイオード、TRI、TR2・・
・トランジスタ、C1・・・コンデンサ、R1−R5・
・・抵抗である。FIG. 1 is a side view of a conventional circuit, FIG. 2 is a selection drive circuit diagram of this embodiment, and FIG. 3 is a selection drive circuit diagram of another embodiment. In the figure, Dl... Zener diode, D2 to D
4...Switching diode, TRI, TR2...
・Transistor, C1...Capacitor, R1-R5・
...It is resistance.
Claims (1)
ーダイオードと第1の抵抗を介して電源KW続し、前記
ツェナーダイオードと第1の抵抗の接続点より第2の抵
抗を介してコレクタ接地形トランソスタ回路のペースに
接続し、該コレクタ接地形トランジスタのエミッタに第
1のダイオードのアノード端子を、ベースにカソード端
子を接続し、該コレクタ接地形トランソスタのエミッタ
より第3の抵抗金倉して前記エミッタ接地形トランジス
タのコレクタに接続し、前記コレクタ接地形トランジス
タのエミッタに前記エミッタ接地形トランジスタのオン
時に順方向接続となるように第2のダイオードを介して
一定の電圧を供メし、前記コレクタ接地形トランソスタ
のエミツ′りより出力を取シ出す構成としたことを特徴
とする選択駆動回路。The collector of the emitter grounded transistor circuit is connected to the power supply KW via the Zener diode and the first resistor, and the connection point between the Zener diode and the first resistor is connected to the collector grounded transistor circuit through the second resistor. The anode terminal of the first diode is connected to the emitter of the grounded collector transistor, the cathode terminal is connected to the base of the transistor, and a third resistor is connected to the emitter of the grounded collector transistor to connect the collector of the grounded emitter transistor. A constant voltage is applied to the emitter of the grounded collector transistor through a second diode so that the emitter of the grounded collector transistor is connected in a forward direction when the grounded emitter transistor is turned on. A selection drive circuit characterized in that the selection drive circuit is configured to output more output than the other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25483A JPS59126325A (en) | 1983-01-06 | 1983-01-06 | Selective driving circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25483A JPS59126325A (en) | 1983-01-06 | 1983-01-06 | Selective driving circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59126325A true JPS59126325A (en) | 1984-07-20 |
JPH0261816B2 JPH0261816B2 (en) | 1990-12-21 |
Family
ID=11468789
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25483A Granted JPS59126325A (en) | 1983-01-06 | 1983-01-06 | Selective driving circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59126325A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0219040A2 (en) * | 1985-10-18 | 1987-04-22 | International Business Machines Corporation | Circuit for the speeding-up of up-going transitions in TTL or DTL circuits under high capacitive load |
US5374858A (en) * | 1991-10-10 | 1994-12-20 | Texas Instruments Deutschland Gmbh | Bus driver circuit |
-
1983
- 1983-01-06 JP JP25483A patent/JPS59126325A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0219040A2 (en) * | 1985-10-18 | 1987-04-22 | International Business Machines Corporation | Circuit for the speeding-up of up-going transitions in TTL or DTL circuits under high capacitive load |
US5374858A (en) * | 1991-10-10 | 1994-12-20 | Texas Instruments Deutschland Gmbh | Bus driver circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0261816B2 (en) | 1990-12-21 |
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