JPS5912629A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS5912629A
JPS5912629A JP57121585A JP12158582A JPS5912629A JP S5912629 A JPS5912629 A JP S5912629A JP 57121585 A JP57121585 A JP 57121585A JP 12158582 A JP12158582 A JP 12158582A JP S5912629 A JPS5912629 A JP S5912629A
Authority
JP
Japan
Prior art keywords
field effect
gate
effect transistor
source
insulated gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57121585A
Other languages
Japanese (ja)
Inventor
Koichiro Okumura
奥村 孝一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57121585A priority Critical patent/JPS5912629A/en
Publication of JPS5912629A publication Critical patent/JPS5912629A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back

Abstract

PURPOSE:To charge a load of a large capacity up to a potential of a constant voltage power supply in high speed and to reduce the power consumption by stopping a positive feedback loop until its operation becomes important for operating efficiently the positive feedback loop. CONSTITUTION:A transistor(TR)T24 is kept conductive until a gate potential of a TRT23 goes to a value close to a value (Vcc-VT21) being the subtraction of the threshold voltage VT21 of a TRT21 from a power supply voltage Vcc, and the potentil at an output terminal 0 is kept to a value close to a ground level so as not to activate the positive feedback loop. When the TRT24 is conductive and the potential difference between the gate and the source of the TRT23 is as large as the (Vcc-VT21), the positive feedback loop is operated. Since the conductivity of the TRT23 is large in this case, the efficiency of the positive feedback is high and the load of the large capacity is charged up in high speed.

Description

【発明の詳細な説明】 本発明に半導体回路に閥するものである。[Detailed description of the invention] The present invention is directed to semiconductor circuits.

従来、この棟の回路として、第1図に示す回路が提案さ
れていた。まず第1図の従来の回路について構成及び動
作を詳細に説明することとする。
Conventionally, the circuit shown in Figure 1 has been proposed as a circuit for this building. First, the configuration and operation of the conventional circuit shown in FIG. 1 will be explained in detail.

第1図の従来の回路にドレインおよびゲートが定電源電
源vcc VC接続されたエンハンスメント型絶縁ゲー
ト電界効果トランジスタ(以下E−I GF’ETと略
す)T11と、ドレインがToのソースと接続され、ゲ
ートが入力端子Iと接続されソースが接地されたE−I
GFETT12 とドレインがVCG K接続され、ゲ
ートがT+tのソースに接続されたE−IGFET T
13と、ドレインがT13のソースに接続されると共に
出力端子Oとなり、ゲートが入力端チェと接続され、ソ
ースが接続されたE −IGFETT14と、 Tla
のゲートとソースの間に挿入された容fellにより構
成されている。第1図においてCLは出力端子Ovcつ
く負荷容量である。
In the conventional circuit of FIG. 1, there is an enhancement type insulated gate field effect transistor (hereinafter abbreviated as E-I GF'ET) T11 whose drain and gate are connected to a constant power supply Vcc VC, and whose drain is connected to the source of To. E-I whose gate is connected to input terminal I and whose source is grounded
GFET T12 and E-IGFET T whose drain is connected to VCG K and whose gate is connected to the source of T+t.
13, an E-IGFET T14 whose drain is connected to the source of T13 and becomes the output terminal O, whose gate is connected to the input terminal chain and whose source is connected, Tla
It is composed of a capacitor inserted between the gate and source of the transistor. In FIG. 1, CL is the load capacitance attached to the output terminal Ovc.

次に第1図の従来回路の動作について説明するが、説明
の都合上、第1図の従来回路にすべてNチャンネルの絶
縁ゲート電界効果トランジスタにより構成されているも
のとする。まず、入力端子Ix供給される入力信号がハ
イレベルからローレベルに変化するときは、T12およ
り1゛14は導通状態から非導通状態に変わり、’I’
llのソースの電位すなわち’l’1aのゲート電位は
ローレベルかラハイレペルに向かつて上昇してゆき、T
13の閾値電圧を越えると’l’1gは非導通状態から
導通状態VC変化し、T13のソースの電位、すなわち
出力端子0の電位に上昇する。Txsのソースの電位の
上昇分は結合容i C1lを介して1゛13のゲート電
位の上昇に寄与し、正帰還ルーズを形成し、T13のゲ
ート電位を定電圧電源Vccの電位(Vccレベル)よ
り高くしてやることができるので出力端子0にff V
ccレベルの出力を得ることができる。逆に入方端チェ
に供給される入力信号がローレベルからハイレベルに変
化する時は、T12とT14は非導通状態がら導通状態
へ、T13i導通状態がら非導通状態へと変化するので
出力端子Oの電位n Vccレベルから接地電位レベル
まで低下する。
Next, the operation of the conventional circuit shown in FIG. 1 will be described. For convenience of explanation, it is assumed that the conventional circuit shown in FIG. 1 is constructed entirely of N-channel insulated gate field effect transistors. First, when the input signal supplied to input terminal Ix changes from high level to low level, T12 to 1 and 14 change from a conductive state to a non-conductive state, and 'I'
The potential of the source of ll, that is, the gate potential of 'l'1a, increases toward the low level or the high level, and T
When the threshold voltage of T13 is exceeded, 'l'1g changes from a non-conductive state to a conductive state VC, and rises to the potential of the source of T13, that is, the potential of output terminal 0. The increase in the potential of the source of Txs contributes to the increase in the gate potential of 1゛13 via the coupling capacitor iC1l, forming a positive feedback loop, and changing the gate potential of T13 to the potential of the constant voltage power supply Vcc (Vcc level). Since it can be made higher, set ff V to the output terminal 0.
CC level output can be obtained. Conversely, when the input signal supplied to the input terminal changes from low level to high level, T12 and T14 change from a non-conducting state to a conducting state, and T13i changes from a conducting state to a non-conducting state, so that the output terminal The potential of O drops from the Vcc level to the ground potential level.

すなわち、第1図の従来回路はインバーターとして動作
し、出力のハイレベルr;c Vccレベルでスイッチ
ング時の過渡状態を除けば1゛13めるいばT14  
のいずれかのE−IGFB’l’が非導通状態にあるの
で消費電力も小さいという特徴があった。ところが第1
図の従来回路においては高速のスイッチング動作が要求
される場合には本質的に不適当な回路であることがわか
った。
That is, the conventional circuit shown in FIG. 1 operates as an inverter, and when the output is at a high level r;
Since either E-IGFB'l' is in a non-conducting state, power consumption is also low. However, the first
It has been found that the conventional circuit shown in the figure is essentially unsuitable when high-speed switching operation is required.

以下にその理由を記述する。The reason is described below.

第1図の従来回路において入力信号がハイレベルからロ
ーレベルに低下すると5T1att’lただちに非導通
状態となジ、’l’12が非導通状態となり、T11を
通して’l’tsのゲートを充電し、T13が導通状態
となると、同時に出力端子Oの電位すなわちIll 1
3のソースの電位に上昇を始め、C11を介してTs 
aのゲート電位を更に押し上げることにより正帰還ルー
プが働き始めるのであるが、このようにTlaが導通状
態となると同時に前記の正帰還ループが動作を開始する
ということが笑は正帰還ルーズの効率のは下をまねいて
いる。すなわち、T13が導通ずると出力端子Oの電位
も上昇し、Coを介してIll、3のゲート電位を押し
上げる正帰還ルーズが作動しはじめるが、T13のゲー
ト電位がVccレベルからTllの閾値電圧VTIIを
引いたイ倣Yet: −vr+りになるまでは正帰還ル
ープの有無に無関係にTllを通しての充電によt) 
T13のゲー[1j位を上昇させることができるのであ
り、その反面、本来正帰還ルーズによる’hsのゲート
電位の押し上げが必要となる、’1” 13のゲート電
位が(Vcc−VTII )以上となる領域に対しては
、すでに出力端子Oの電位が上昇しているためT13の
ゲートとソースの間の電位差が小さくなってしまい、l
’taの4電度を大きくとれない几め、正帰還ループの
効率が低下し、高速のスイッチングを不可能にするから
である。つまQ1正帰還ループを効率よく働かせ、大容
量の負荷CLを高速に充電、するためにはTI3のゲー
ト電位が(Vcc−VTI l)に達するまで出力端子
0の電位を接地レベル近くに保持l〜でおき、正帰還ル
ープによりT13のゲート電位を押し上げる必要がある
領域すなわちT13のゲート電位が(Vcc−VTII
)以上の領域においてT13のゲートとソースの間の電
位差を大きくとることによりIll 、 3の導電度を
上げる必要があるが、第1図の従来の回路では、T13
が導通すると出力端子Oの電位もただちに上昇するので
高速のスイッチングが得られないという欠点があった0 本発明の目的とするところは第1図の従来回路の欠点を
改良し、第1図の従来回路の持つ消費電力が小さいとい
う利点を損うことなく、シかも大容量の負荷を高速にV
ccレベルまで充電できる半導体回路を提供することV
Cある。
In the conventional circuit shown in FIG. 1, when the input signal falls from high level to low level, 5T1att'l immediately becomes non-conductive, 'l'12 becomes non-conductive, and the gate of 'l'ts is charged through T11. , T13 becomes conductive, at the same time the potential of the output terminal O, that is, Ill 1
Ts begins to rise to the potential of the source of 3, and Ts
By further raising the gate potential of a, the positive feedback loop starts working, but the fact that the positive feedback loop starts operating at the same time as Tla becomes conductive is the reason for the efficiency of the positive feedback loop. is looking down. That is, when T13 becomes conductive, the potential of the output terminal O also rises, and a positive feedback loose that pushes up the gate potential of Ill and 3 via Co begins to operate, but the gate potential of T13 decreases from the Vcc level to the threshold voltage of Tll, VTII. Yet: -vr+ is charged by charging through Tll regardless of the presence or absence of a positive feedback loop until it becomes t)
It is possible to raise the gate potential of T13 by about 1j, but on the other hand, it is necessary to push up the gate potential of 'hs by positive feedback loose. Since the potential of the output terminal O has already increased for the region where
This is because if the four electric currents of 'ta cannot be made large, the efficiency of the positive feedback loop decreases, making high-speed switching impossible. In other words, in order to make the Q1 positive feedback loop work efficiently and charge the large capacity load CL at high speed, the potential of the output terminal 0 must be kept close to the ground level until the gate potential of TI3 reaches (Vcc - VTI l). ~, the region where it is necessary to push up the gate potential of T13 by a positive feedback loop, that is, the gate potential of T13 is (Vcc-VTII
) In the above region, it is necessary to increase the conductivity of Ill, 3 by increasing the potential difference between the gate and source of T13, but in the conventional circuit shown in FIG.
When the circuit becomes conductive, the potential of the output terminal O rises immediately, which has the disadvantage that high-speed switching cannot be achieved.The purpose of the present invention is to improve the drawbacks of the conventional circuit shown in FIG. It is possible to quickly handle large-capacity loads without sacrificing the advantage of low power consumption of conventional circuits.
To provide a semiconductor circuit that can charge up to cc level
There is C.

本発明の半導体回路は、ドレインおよびゲートが定電圧
電源に接続されたエンノ1ンスメント型の第1の絶縁ゲ
ートを界効果トランジスタと、ドレインが前記第1の絶
縁ゲート電界効果トランジスタのソースと接続され、ゲ
ートを入力端子とし、ソースが接地されたエンノ1ンス
メント型の第2の絶縁ゲート電界効果トランジスタと、
ドレインが前記定電圧電源と接続され、ゲートが前記第
1の絶縁グー1[界効果トランジスタのソースに接続さ
れたエンハンスメント型あるいにティプレジョン型の第
3の絶縁ゲート電界効果トランジスタと、ドレインが前
記第3の絶縁ゲート電界効果トランジスタのソースと接
続されると共に出力端子となり、ソースが接地されたエ
ンハンスメント型の第4の絶縁ゲート電界効果トランジ
スタと、ソースが前記第2の絶縁ゲート電界効果トラジ
スタのゲートに接続され、ゲートが前記第1の絶縁ゲー
ト電界効果トランジスタのソースに接続され、ドレイン
が前記第4の絶縁ゲート電界効果トランジスタのゲート
に接続されたエンハンスメント型の第5の絶縁ゲート電
界効果トランジスタと、ドレインが前記定電8E電源に
接続され、ゲートが前記第2の絶縁ケート電界効果トラ
ンジスタのゲートに接続されソースが前記第4の絶縁グ
ー)K界効果トランジスタのゲートに接続されたエンハ
ンスメント型の第6の絶縁ゲート電界効果トランジスタ
と、一端が前記第3の絶縁ゲート電界効果トランジスタ
のゲートに接続され、他端が前記第3の絶縁ゲート電界
効果トランジスタのソースに接続された容量により構成
されたことを特徴とする。
In the semiconductor circuit of the present invention, a first insulated gate of an enforcement type whose drain and gate are connected to a constant voltage power supply is connected to a field effect transistor, and a drain is connected to a source of the first insulated gate field effect transistor. , a second insulated gate field effect transistor of an enforcement type, whose gate is an input terminal and whose source is grounded;
A third insulated gate field effect transistor of an enhancement type or tiplesion type whose drain is connected to the constant voltage power supply and whose gate is connected to the source of the first insulated gate field effect transistor 1 [the drain of which is connected to the source of the field effect transistor; is connected to the source of the third insulated gate field effect transistor and serves as an output terminal; a fourth enhancement type insulated gate field effect transistor whose source is grounded; and a fourth insulated gate field effect transistor whose source is connected to the second insulated gate field effect transistor. a fifth insulated gate field effect transistor of an enhancement type, the gate of which is connected to the gate of the first insulated gate field effect transistor, the gate of which is connected to the source of the first insulated gate field effect transistor, and whose drain is connected to the gate of the fourth insulated gate field effect transistor; an enhancement transistor having a drain connected to the constant voltage 8E power supply, a gate connected to the gate of the second insulated gate field effect transistor, and a source connected to the gate of the fourth insulated gate field effect transistor; and a capacitor having one end connected to the gate of the third insulated gate field effect transistor and the other end connected to the source of the third insulated gate field effect transistor. It is characterized by having been.

本発明の実施例の回路図である第2図を用いて本発明の
詳細な説明する。
The present invention will be described in detail using FIG. 2, which is a circuit diagram of an embodiment of the present invention.

第2図の本発明の実施例の回路は、ドレインとゲートが
定′小圧電源、VCC&′c接続されたE−IGF E
 T T21とドレインがT21のソースに接続され、
ゲートが入力端子Iに接続され、ソースが接地されfc
 E−IGFET T22 ト、ドレインがVcc V
CゲートがT21のソースに接続されたE −jGFE
T T23と、ドレインがT23のソースに接続される
と共に出力端子0となジソースが接地されたB−10F
ETT24とソースがT22のゲートに接続され、ゲー
トがT21のソースに接続され、ドレインがT24のゲ
ートvc接続されたE −IGFE’f’ T25のド
レインと接続され、ゲートがT22のゲートに接続され
、)”レインyjEVcc KH続’Gしfc E−4
GFET T26ト、T23のゲートとソースの間に挿
入された容量C21により構成されている。またCLr
[、出力端子0につく負荷容量である。
The circuit according to the embodiment of the present invention shown in FIG. 2 is an E-IGF E whose drain and gate are connected to a constant low voltage power supply, VCC
T T21 and the drain are connected to the source of T21,
The gate is connected to the input terminal I, the source is grounded, and fc
E-IGFET T22, drain is Vcc V
E −jGFE with C gate connected to the source of T21
T T23 and B-10F whose drain is connected to the source of T23 and whose output terminal is 0 and whose source is grounded.
E-IGFE'f' whose source is connected to the gate of T22, whose gate is connected to the source of T21, and whose drain is connected to the gate vc of T24; whose source is connected to the drain of T25, whose gate is connected to the gate of T22; ,)”RainyjEVcc KHzoku'Gshifc E-4
It is composed of a capacitor C21 inserted between the gate and source of GFET T26 and T23. Also CLr
[, is the load capacitance attached to output terminal 0.

次に本発明の回路の動作を第2図を用いて説明する。こ
の場合もすべてNチャンネルの絶縁ゲート甫1界効果ト
ランジスタを用いであるものとして説明を行なう01ず
入力端子lに供給される人力()lがハイレベルからロ
ーレベルに変化するときは、T22およびT26は非導
通状態となるが、T24は導通状態を維持しており、次
に’l’z1のソース電位即ちT23およびT2Bのゲ
ート電位が上昇し、′I゛25の閾値電圧とT23の閾
値電圧を越えるとほぼ同時にT23とT211 i非導
通状態から導通状態に変わるが、T24のゲート電位に
、T2sK碑軍度の小さいE−IG1=’ET f!I
、tばチャンネル1崩が小さく、チャンネル長が長いE
−IGFBTを使用すれば、T24のゲート電位の接地
電位へ向かっての牧電速度を遅くできるので出力端子O
の電位1qTzaが導通状態であっても接地レベルに近
い電位にとどめておくこtができる。T24のゲート電
位が更に低下し、T24の閾値電圧以下になるとT24
ぼ非導通状態となるので出力端子0の電位は上昇し、C
21fL介してT23のゲート電位を引き上げT230
4′RL度を更に深くし、出力端子により高い電圧を現
出せしめるという正帰還ループにより最終的に出力端子
Oが■CCレベルの電位にまで上昇するのは2.1図の
従来回路と同様である。ただ、本発明の回路の場合には
、T23とT211が導通状態になるのが同時でめり、
しかもT24のゲートの電荷の放電路はT25を通して
の路であるので’l’2sのチャンネル長及びチャンネ
ル幅を適当な値にとることにより、T23のゲート電位
がほぼ■CCt位からT21の閾値電圧VT21を引い
た値即ち(Vcc−VTRりに近い値となるまでT24
を導通状態のままにしておき、出力端子Oの電位を接地
レベルに近い値に保ち正帰還ループが動作しないように
しておくことが可能であるので、T24が非導通状態と
なり前述の正帰還ループが動作するときのT23のゲー
トとソースの間の電位差にほぼ(Vcc−VTRりと大
きく、T23の導電度が大きいので正帰還ループの効率
も高く、大容量の負荷を高速に充電するのに有利であり
、もちろん、正帰還ループの押し上げ効率が良いので、
出力端子0の電位は短時間に負荷容量CLをVccレベ
ルまで充電することができる。
Next, the operation of the circuit of the present invention will be explained using FIG. In this case as well, the explanation will be given assuming that all N-channel insulated gate field effect transistors are used. T26 becomes non-conductive, but T24 maintains the conductive state, and then the source potential of 'l'z1, that is, the gate potential of T23 and T2B rises, and the threshold voltage of 'I'25 and the threshold of T23 increase. When the voltage is exceeded, T23 and T211i change from non-conductive state to conductive state almost at the same time, but the gate potential of T24 is affected by E-IG1='ET f! I
, t has a small channel 1 collapse and a long channel length E
- If IGFBT is used, the speed at which the gate potential of T24 moves toward the ground potential can be slowed down, so the output terminal O
Even if the potential 1qTza is in a conductive state, it can be kept at a potential close to the ground level. When the gate potential of T24 further decreases and becomes below the threshold voltage of T24, T24
Since it becomes almost non-conductive, the potential of output terminal 0 rises and C
Raise the gate potential of T23 through 21fL T230
4' The positive feedback loop that further deepens the RL degree and causes a higher voltage to appear at the output terminal ultimately raises the potential of the output terminal O to the CC level, similar to the conventional circuit shown in Figure 2.1. It is. However, in the case of the circuit of the present invention, T23 and T211 become conductive at the same time,
Furthermore, since the discharge path of the charge at the gate of T24 is through T25, by setting the channel length and channel width of 'l'2s to appropriate values, the gate potential of T23 can be adjusted from approximately ■CCt to the threshold voltage of T21. T24 until the value obtained by subtracting VT21, that is, the value close to (Vcc - VTR)
Since it is possible to keep T24 in a conductive state and keep the potential of the output terminal O close to the ground level so that the positive feedback loop does not operate, T24 becomes non-conductive and the positive feedback loop described above is activated. The potential difference between the gate and source of T23 when it operates is as large as (Vcc - VTR), and the conductivity of T23 is high, so the efficiency of the positive feedback loop is high, and it is suitable for quickly charging a large capacity load. This is advantageous, and of course, the positive feedback loop has good pushing efficiency, so
The potential of the output terminal 0 can charge the load capacitor CL to the Vcc level in a short time.

逆に入力端チェに供給される入力信号がローレベルから
ハイレベルに変化するときには、T26が導通状態とな
り、T22が導通状態となり、Tzsrc非導通状態と
なるのでT23のゲート電位は接地レベルにT24のゲ
ートを位にハイレベルとなるのでT23は非導通状態、
T24は導通状態となる結果、出力端子Oの電位が■C
Cレベルから接地レベルへと変化するのは第1図の従来
回路の場合と同じであり、消費電力も従来回路と等しい
Conversely, when the input signal supplied to the input terminal CH changes from low level to high level, T26 becomes conductive, T22 becomes conductive, and Tzsrc becomes non-conductive, so the gate potential of T23 changes to the ground level T24 Since the gate becomes high level, T23 becomes non-conductive.
As a result of T24 becoming conductive, the potential of the output terminal O becomes ■C
The change from the C level to the ground level is the same as in the conventional circuit shown in FIG. 1, and the power consumption is also the same as in the conventional circuit.

以上に明らかにしたように、第1図の従来回路では早い
時期に正帰還ループが動作を始めるので押し上げの効率
が低下してしまい、しかもT13のゲートとソースの間
の電位差も小さくなるので正帰還ループの働きが重要と
なる時にその効率が低下してしまう几め、高速のスイッ
チング動作が阻害されるという欠点があったが、本発明
の半導体回路によれば、正帰還ループを、その働きが重
要となる時期まで停止させておくための回路上の工夫を
したために、正帰還ループは極めて効率良く働き、T2
3のゲートとソースの間の電位差が大きいままゲート電
位を押し上げることができるので大容量の負荷を高速V
cVCCレベルまで充電でき、しかも消費電力の小さい
回路を得ることができる。
As explained above, in the conventional circuit shown in Fig. 1, the positive feedback loop starts operating at an early stage, which reduces the efficiency of pushing up, and furthermore, the potential difference between the gate and source of T13 becomes small, so the positive feedback loop starts operating at an early stage. When the function of the feedback loop is important, its efficiency decreases and high-speed switching operation is inhibited, but according to the semiconductor circuit of the present invention, the positive feedback loop can be Because the circuit was devised to stop T2 until it becomes important, the positive feedback loop works extremely efficiently and
Since the gate potential can be pushed up while the potential difference between the gate and source of 3 is large, it is possible to handle large-capacitance loads at high speeds.
It is possible to obtain a circuit that can be charged to the cVCC level and has low power consumption.

尚、第2図の本発明の詳細な説明において、T23μE
−IGFETとして説明したがディルジョン型の絶縁ゲ
ート電界効果トランジスタを用いても動作の原理はまっ
たく同様で支障はない。ただこの場合a出力端子の電位
がローレベルにおるときにT23と′P24を通して定
常的に電流が流れるので消費電力が大きくなるという欠
′点があるが、その反面、ディグレション型絶縁ゲート
電界効釆トランジスタは同一寸法のE−IGFETに比
較して同一のゲート電位の場合は導電度が大きいのでよ
り高ノボの回路を実現できるという利点がめる0また説
明ではNチャンネルの絶縁ゲート電界効果トランジスタ
としたがPチャンネルの絶縁ゲート電界効果トランジス
タを用い7?+場合でも本発明の効果にNチャンネルの
場合と同様であることにもちろんでめる0
In addition, in the detailed explanation of the present invention in FIG. 2, T23μE
-IGFET has been described, but the principle of operation is exactly the same and there is no problem even if a Dilgeon type insulated gate field effect transistor is used. However, in this case, when the potential of the a output terminal is at a low level, a current flows steadily through T23 and 'P24, so the power consumption increases, but on the other hand, the degradation type insulated gate field effect Compared to an E-IGFET of the same size, the conductivity of the transistor is higher at the same gate potential, so it has the advantage of being able to realize a circuit with a higher voltage.In addition, in the explanation, it is an N-channel insulated gate field effect transistor. uses a P-channel insulated gate field effect transistor7? Of course, even in the + case, the effect of the present invention is the same as in the N channel case.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図μ従米回路の回路。巣2図V工本発明の半導体回
路の実施例の回路図0T21.  T22.  T23
゜T24 、  Tzs 、  TT26ばエンかンス
メント型絶縁ゲート電界効果トランジスタ。C21,C
LlI:l:容量である。
Figure 1 μ-dependent circuit circuit. Circuit diagram of an embodiment of the semiconductor circuit of the present invention 0T21. T22. T23
゜T24, Tzs, TT26 enhancement type insulated gate field effect transistor. C21,C
LlI:l: Capacity.

Claims (1)

【特許請求の範囲】[Claims] ドレインおよびゲートが定電圧電源に接続されたエンハ
ンスメント型の第1の絶縁ゲート電界効果トランジスタ
と、ドレインが前記第1の絶縁ゲート電界効果トランジ
スタのソースと接続され、ゲートを入力端子とし、ソー
スが接地されたエンハンスメント型V第2の絶縁ゲート
電界効果トランジスタと、ドレインが前記定電圧電源と
接続され、ゲートが前記第1の絶縁ゲート電界効果トラ
ンジスタのソースに接続されたエンハンスメント型ある
いはティグレション型の第3の絶縁ゲート電界効果トラ
ンジスタと、ドレインが前記第3の絶縁ゲート電界効果
トランジスタのソースと接続されると共に出力端子とな
り、ソースが接地されたエンハンスメント型の第4の絶
縁ゲート電界効果トランジスタと、ソースが前記第2の
絶縁ゲート電界効果トランジスタのゲートに接続されゲ
ートが前記第1の絶縁ゲート電界効果トランジスタのソ
ースに接続され、ドレインが前記第4の絶縁ゲート電界
効果トランジスタのゲートに接続されたエンハンスメン
ト型の第5の絶縁ケート電界効果トランジスタと、ドレ
インが前記定電圧電源と接続され、ゲートが前記第2の
絶縁ゲート電界効果トランジスタのゲートに接続され、
ソースが前記第4の絶縁ゲート電界効果トランジスタの
ゲートに接続されたエンハンスメント型の第6の絶縁ゲ
ート電界効果トランジスタと、一端が前記第3の絶縁ゲ
ート電界効果トランジスタのゲートに接続され、他端が
前記第3の絶縁ゲート電界効果トランジスタのソースに
接続された容量を有して構成されたことを特徴とする半
導体回路。
an enhancement type first insulated gate field effect transistor having a drain and a gate connected to a constant voltage power supply; a drain connected to the source of the first insulated gate field effect transistor, the gate serving as an input terminal, and the source being grounded; an enhancement type V second insulated gate field effect transistor, and an enhancement type or tigretion type V transistor whose drain is connected to the constant voltage power supply and whose gate is connected to the source of the first insulated gate field effect transistor. a fourth insulated gate field effect transistor of an enhancement type whose drain is connected to the source of the third insulated gate field effect transistor and serves as an output terminal, and whose source is grounded; is connected to the gate of the second insulated gate field effect transistor, the gate is connected to the source of the first insulated gate field effect transistor, and the drain is connected to the gate of the fourth insulated gate field effect transistor. a fifth insulated gate field effect transistor of the type, a drain connected to the constant voltage power supply and a gate connected to the gate of the second insulated gate field effect transistor;
an enhancement type sixth insulated gate field effect transistor having a source connected to the gate of the fourth insulated gate field effect transistor, one end connected to the gate of the third insulated gate field effect transistor, and the other end connected to the gate of the third insulated gate field effect transistor; A semiconductor circuit comprising a capacitor connected to the source of the third insulated gate field effect transistor.
JP57121585A 1982-07-13 1982-07-13 Semiconductor circuit Pending JPS5912629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57121585A JPS5912629A (en) 1982-07-13 1982-07-13 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57121585A JPS5912629A (en) 1982-07-13 1982-07-13 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS5912629A true JPS5912629A (en) 1984-01-23

Family

ID=14814880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57121585A Pending JPS5912629A (en) 1982-07-13 1982-07-13 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS5912629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296741A (en) * 2003-03-26 2004-10-21 Semiconductor Energy Lab Co Ltd Source follower or boot strap circuit, drive circuit provided therewith, and liquid crystal display device provided with the drive circuit
JP2018170780A (en) * 2018-06-15 2018-11-01 株式会社半導体エネルギー研究所 Electronic apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296741A (en) * 2003-03-26 2004-10-21 Semiconductor Energy Lab Co Ltd Source follower or boot strap circuit, drive circuit provided therewith, and liquid crystal display device provided with the drive circuit
US7701009B2 (en) 2003-03-26 2010-04-20 Semiconductor Energy Laboratory Co., Ltd Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
JP4531343B2 (en) * 2003-03-26 2010-08-25 株式会社半導体エネルギー研究所 Driving circuit
US8026551B2 (en) 2003-03-26 2011-09-27 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
US8952455B2 (en) 2003-03-26 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
JP2018170780A (en) * 2018-06-15 2018-11-01 株式会社半導体エネルギー研究所 Electronic apparatus

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