JPS59126281U

JPS59126281U - display device

Info

Publication number: JPS59126281U
Application number: JP14291883U
Authority: JP
Inventors: 服部　精一; 豊水野; 神田　邦男
Original assignee: ファナック株式会社
Priority date: 1983-09-14
Filing date: 1983-09-14
Publication date: 1984-08-25

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のグラフィックディスプレイ装置、第２図
は本考案によるグラフインクディスプレイ装置のブロッ
ク線図を示す。ＣＭニゲラフイックメモリ、ＡＥＭ：全消去モード信号
、ＣＲＴＣ：制御回路、ＶＭ：書込モード信号、ＡＣｉ
　：書込用アドレスカウンタ、ＲＡＤ：読出用アドレス
情報、ＭＣｌ　：モード制御回路、ＣＲＴ、陰極線管型
表示器。FIG. 1 is a block diagram of a conventional graphic display device, and FIG. 2 is a block diagram of a graphic ink display device according to the present invention. CM Nigella quick memory, AEM: All erase mode signal, CRTC: Control circuit, VM: Write mode signal, ACi
: Write address counter, RAD: Read address information, MCl: Mode control circuit, CRT, cathode ray tube display.

Claims

[Scope of utility model registration request]

a graphics memory; a write address generating means for writing information to the graphics memory; a write control circuit for providing information to be written to a selected address location of the graphics memory; and a write control circuit for repeatedly reading the contents of the graphics memory. a mode control circuit that generates a write mode signal in a write mode and an all erase mode signal in an all erase mode; a first AND circuit that adds an AND signal with the output to the graphic memory as a write address;
a second AND circuit that adds an AND signal of an inverted signal of the write signal of the mode control circuit and an output of the read address generating means to the graphic memory as a read address; a third AND circuit which receives the all erase signal and the output of the read address generating means; and a logical sum signal of the output of the third AND circuit and the output of the second AND circuit, which is input to the graphic memory. An OR circuit that adds
a circuit that sets the mode control circuit to an all erase mode, supplies erase information to the write control circuit, and writes erase information to all areas of the graphic memory using address information generated by the read address generating means; A display device comprising: