JPS59126268A - Bus gate for exclusive test purpose - Google Patents
Bus gate for exclusive test purposeInfo
- Publication number
- JPS59126268A JPS59126268A JP57226616A JP22661682A JPS59126268A JP S59126268 A JPS59126268 A JP S59126268A JP 57226616 A JP57226616 A JP 57226616A JP 22661682 A JP22661682 A JP 22661682A JP S59126268 A JPS59126268 A JP S59126268A
- Authority
- JP
- Japan
- Prior art keywords
- test
- bus3
- bus
- integrated circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は高密度集積回路の途中に挿入された出荷試験専
用のパスダートに関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a pass dart inserted in the middle of a high-density integrated circuit and used exclusively for shipping tests.
（２）従来技術と問題点
最近、論理回路の集積度が非常に高くなり、内部回路を
構成するダート数も多くなって来た−従って、従来のよ
うに入力ビンに多種類のテストパターンを加えて内部の
故障を検出する方式で ゛は、回路のすべての
部分を完全に検査することは困難である。特に途中の回
路がフィード・々ツクル−グを形成し、相互に関連を有
しているような場合には、入力ビンからイン、テストす
るテストパターンをよほどうまく工夫しないと、故障検
出率はある値以上には向上しにくくなる。(2) Prior art and problems Recently, the degree of integration of logic circuits has become extremely high, and the number of darts composing internal circuits has also increased. In addition, with the method of detecting internal failures, it is difficult to completely inspect all parts of the circuit. In particular, if the circuits in the middle form a feed group and are mutually related, the failure detection rate will be low unless the test pattern for inputting and testing from the input bin is carefully devised. It becomes difficult to improve beyond the value.
このように、効果的なテストパターンを短期間のうちに
、いかにして作成するかが、ＬＳＩ製造の際の最大の障
壁となっている。゛
（３）発明の目的
本発明の目的は、超高密度集積回路の正規のポンディン
グパッドとは別に、ＬＳＩチップ内部にテスト専用の・
フッドと、テスト専用・々スグートとを配置し、該回路
の最も適当と考えられる接続点から回路ネットをバスゲ
ートを介してテスト専用ノ９ッドに引き出して専用端子
とし、この専用端子の信号の出し入れにより回路の故障
検出率を向上させることにある〇
（４）発明の構成
本発明によれば、集積回路の正規・々ラド間に設けられ
たテスト専用ノ々ツドの直前に配置されたテスト専用パ
スダートであって、上記集積回路内路の所定の位置に接
続する引き出し線と該引き出し線を構成するダート素子
及び専用端子を有し、該専用端子の信号の出し入れによ
シ前記集積回路内の故障を検出するようにしたことを特
徴とするテスト専用バスダートが提供される。As described above, how to create an effective test pattern in a short period of time is the biggest hurdle in LSI manufacturing. (3) Purpose of the Invention The purpose of the present invention is to provide a dedicated pad for testing inside an LSI chip, in addition to the regular bonding pad of an ultra-high-density integrated circuit.
hood and a test-dedicated node, and connect the circuit net from the most appropriate connection point of the circuit to the test-dedicated node through the bus gate, making it a dedicated terminal, and then transmitting the signal of this dedicated terminal. 〇 (4) Structure of the invention According to the present invention, a test dedicated node provided between the regular and rads of an integrated circuit is placed immediately before the test dedicated node. A pass dirt for testing only, comprising a lead wire connected to a predetermined position of the internal path of the integrated circuit, a dart element constituting the lead wire, and a dedicated terminal, and capable of inputting and outputting signals from the dedicated terminal to the integrated circuit. A test-only bus dart is provided, which is characterized in that it detects failures within the bus.
（５）発明の実施例
以下、本発明を実施例によシ添付図面を参照して説明す
る。(5) Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.
第１図は本発明に係るテスト専用パスゲートを組み込ん
だ集積回路の構成図であシ、参照符号ａは内部ゲート領
域、ｂはテスト専用パッド、Ｃは正規の・ぐラドである
。FIG. 1 is a block diagram of an integrated circuit incorporating a test-only pass gate according to the present invention, in which reference numeral a is an internal gate region, b is a test-only pad, and C is a regular pad.
上記テスト専用・やラドｂの直前には第２図に示す具ス
ダートが配置されている。第１図との関係は端子ＢＵＳ
Ｉ 、 ＢＵＳ２ 、 ＢＵＳ３ 、 ＢＵＳＣＯＮＴ
Ｉ及び２が専用パッドｂに、端子ＲＥＳＥＴＩ 、 Ｃ
ＬＯＣＫＩ 、 ＤＡＴに１゜ＣＬＯＣＫ２ 、 ＤＡ
ＴＡ２ 、 ＣＬＯＣＫ３ 、０ＵＴＩが正規−ザッド
Ｃに、残シが内部ダート領域ａに、それぞれ対応してい
る。外部に引き出す回路ネットはＢＵＳ １のようにな
るべく多くのネットが集まってくる部分を選択するか、
または、フリップフロップのデータ入力のように回路の
玄イツチングスピードへの影響が可及的に少なくて済む
個所を選択する。A tool slide shown in FIG. 2 is placed immediately before the test-only rad b. The relationship with Figure 1 is the terminal BUS.
I, BUS2, BUS3, BUSCONT
I and 2 are dedicated pads b, terminals RESETI, C
LOCKI, 1°CLOCK2, DA to DAT
TA2, CLOCK3, and 0UTI correspond to regular-ZAD C, and remaining corresponds to internal dirt area a, respectively. For the circuit net to be drawn out to the outside, select a part where as many nets as possible are gathered, such as BUS 1, or
Alternatively, select a location such as the data input of a flip-flop that has as little influence on the circuit's bursting speed as possible.
上記第２図のパスゲートは次のように動作する。The pass gate of FIG. 2 above operates as follows.
先ずＢＵＳ １と２を出力状態にしてＢＵＳ ３のみを
入力状態にした場合、ＰＡＲＴＩ及び３の故障検出がで
きる。即ち、ＰＡＲＴＩに関しては、ＲＥＳＥＴＩ 、
ＣＬＯＣＫＩからＢＵＳＩまでの回路の良否、ＲＥＳ
ＥＴＩ 、 ＤＡＴＡＩ 。First, if BUS 1 and 2 are set to output state and only BUS 3 is set to input state, failure of PARTI and 3 can be detected. That is, for PARTI, RESETI,
Quality of circuit from CLOCKI to BUSI, RES
ETI, DATAI.
ＣＬＯＣＫ２ 、 ＤＡＴＡ２からＢＵＳ２までの回路
の良否がそれぞれ判定できる。ＰＡＲＴ３に関しては、
ＣＬＯＣＫ３゜ＢＵＳ３から０ＵＴＩまでの回路の良否
判定が可能である。The quality of the circuits from CLOCK2 and DATA2 to BUS2 can be determined. Regarding PART 3,
It is possible to judge the quality of the circuit from CLOCK3°BUS3 to 0UTI.
次に、ＢＵＳ １と２を入力状態にし、ＢＵＳ３のみを
出力状態にした場合にはＰＡＲＴ２のＣＨＥＣＫができ
る。即ちＢＵＳＩ 、 ＤＡＴＡＩ 、 ＣＬＯＣＫ２
、 ＢＵＳ２ 。Next, if BUS 1 and 2 are set to input state and only BUS 3 is set to output state, PART 2 can be checked. That is, BUSI, DATAI, CLOCK2
, BUS2.
ＣＬＯＣＫ３からＢＵＳ３までの回路の良否を判定でき
る。It is possible to judge the quality of the circuit from CLOCK3 to BUS3.
尚、一般的な動作状態では３−５ＴＡＴＥコントロール
端子ＢＵＳＣＯＮＴＩと２から信号を加え、ＢＵＳＩ
、 ２゜３のすべてを出力状態に保ち、ＢＵＳダートを
単なるＲＥＥＮＴＲＹとして使用する。In addition, under normal operating conditions, signals are applied from 3-5 TATE control terminals BUSCONTI and 2, and BUSI
, 2.3 are all kept in the output state and the BUS dart is used simply as a REENTRY.
（６）発明の効果
上記の通シ、本発明によればテスト専用バスダートを設
けたことに伴いＢＵＳＩ 、 ＢＵＳ２ 、 ＢＵＳ３
。(6) Effects of the Invention In accordance with the above, according to the present invention, the provision of test-only bus darts improves BUSI, BUS2, and BUS3.
.
ＢＵＳＣＯＮＴｌ、 ＢＴＪＳＣＯＮＴ２という端子が
増えるというデメリットはあるが、回路全体を大きく３
つの部分に分けてテストでき、テストパターン数が少な
くて済みかつ回路が単純化され、従って故障検出率は向
上する。また、高集積度ＬＳＩを新たに開発する際の納
期の短縮に役立つ。Although there is a disadvantage that the number of terminals BUSCONTl and BTJSCONT2 increases, the overall circuit can be reduced to 3.
The circuit can be tested in two parts, the number of test patterns is small, the circuit is simplified, and the fault detection rate is improved. It also helps shorten delivery times when developing new high-density LSIs.
第１図は本発明に係るテスト専用バスダートを組み込ん
だ回路の構成図、第２図は本発明グ〜トの構成図である
。
ＢＵＳＩ 、 ＢＵＳ２ 、 ＢＵＳ３ 、ＢＵＳＣ：
０ＮＴＩ、ＢＵＳＣ’０ＮＴ２・・・テスト専用端子。FIG. 1 is a block diagram of a circuit incorporating a test bus dart according to the present invention, and FIG. 2 is a block diagram of a gate of the present invention. BUSI, BUS2, BUS3, BUSC:
0NTI, BUSC'0NT2...Test-only terminal.
Claims (1)
ドの直前に配置されたテスト専用パスダートであって、
上記集積回路内部の所定の位置に接続する引き出し線と
一該引き出し線を構成するダート素子及び専用端子を有
し、該専用端子の信号の出し入れによシ前記集積回路内
の故障を検出するようにしたことを特徴とするテスト専
用バスゲート。A test-dedicated pass dart placed immediately before a test-dedicated pad provided between regular nodes of an integrated circuit,
It has a lead wire connected to a predetermined position inside the integrated circuit, a dirt element constituting the lead wire, and a dedicated terminal, and is configured to detect a failure in the integrated circuit by inputting and outputting signals from the dedicated terminal. A test-only bus gate featuring the following features:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226616A JPS59126268A (en) | 1982-12-27 | 1982-12-27 | Bus gate for exclusive test purpose |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226616A JPS59126268A (en) | 1982-12-27 | 1982-12-27 | Bus gate for exclusive test purpose |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59126268A true JPS59126268A (en) | 1984-07-20 |
| JPH0530227B2 JPH0530227B2 (en) | 1993-05-07 |
Family
ID=16847992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226616A Granted JPS59126268A (en) | 1982-12-27 | 1982-12-27 | Bus gate for exclusive test purpose |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59126268A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08163951A (en) * | 1994-12-14 | 1996-06-25 | Meishin Denki Kk | Preventing device for damage by bird |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4975279A (en) * | 1972-10-24 | 1974-07-19 | ||
| JPS55136969A (en) * | 1979-04-13 | 1980-10-25 | Mitsubishi Electric Corp | Circuit testing |
-
1982
- 1982-12-27 JP JP57226616A patent/JPS59126268A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4975279A (en) * | 1972-10-24 | 1974-07-19 | ||
| JPS55136969A (en) * | 1979-04-13 | 1980-10-25 | Mitsubishi Electric Corp | Circuit testing |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0530227B2 (en) | 1993-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2950475B2 (en) | Built-in self-test with memory | |
| US6516428B2 (en) | On-chip debug system | |
| JP4856429B2 (en) | On-chip circuit for bus inspection | |
| US6163867A (en) | Input-output pad testing using bi-directional pads | |
| US7982217B2 (en) | Semiconductor device and its test method | |
| JPH10283274A (en) | Method and device for testing memory | |
| KR20070109434A (en) | Method for open test and short test of semiconductor chip and semiconductor test system | |
| JP3092704B2 (en) | Large scale integrated circuit and its board test method | |
| US7240255B2 (en) | Area efficient BIST system for memories | |
| US6834366B2 (en) | Method of outputting internal information through test pin of semiconductor memory and output circuit thereof | |
| CN101727980A (en) | Multi-chip module | |
| EP0023413A1 (en) | Single Chip Microprocessor having means for selectively outputting instruction decoder control signals | |
| WO2002057802A1 (en) | Input/output continuity test mode circuit | |
| US6275428B1 (en) | Memory-embedded semiconductor integrated circuit device and method for testing same | |
| US7131033B1 (en) | Substrate configurable JTAG ID scheme | |
| US6493840B1 (en) | Testability architecture for modularized integrated circuits | |
| JPS59126268A (en) | Bus gate for exclusive test purpose | |
| US8176370B2 (en) | Method and system for direct access memory testing of an integrated circuit | |
| US20080028104A1 (en) | Semiconductor device and operation control method of semiconductor device | |
| US6442668B2 (en) | Bus control system | |
| JPS59168995A (en) | Memory | |
| US5815001A (en) | Integrated circuit board with built-in terminal connection testing circuitry | |
| JP3963259B2 (en) | Semiconductor device | |
| US6445205B1 (en) | Method of testing integrated circuits | |
| JPH0746130B2 (en) | LSI system |